diff options
author | Marek Olšák <[email protected]> | 2018-11-26 17:13:47 -0500 |
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committer | Marek Olšák <[email protected]> | 2018-11-28 20:20:27 -0500 |
commit | 27f99350751f8163487c641dfc430d81bc9312be (patch) | |
tree | 6240c8a1d0070c7e777641f112c113a63b2a8dc1 /src/gallium/winsys/amdgpu | |
parent | 6b554d863f05f77ed8fe0ba99e157b3558c5abc2 (diff) |
winsys/amdgpu: use optimal VM alignment for imported buffers
Window system buffers didn't use the optimal alignment.
Acked-by: Christian König <[email protected]>
Diffstat (limited to 'src/gallium/winsys/amdgpu')
-rw-r--r-- | src/gallium/winsys/amdgpu/drm/amdgpu_bo.c | 49 |
1 files changed, 29 insertions, 20 deletions
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c index e32e23361f4..ce6ebb1ac6f 100644 --- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c @@ -424,6 +424,27 @@ static void amdgpu_add_buffer_to_global_list(struct amdgpu_winsys_bo *bo) } } +static uint64_t amdgpu_get_optimal_vm_alignment(struct amdgpu_winsys *ws, + uint64_t size, unsigned alignment) +{ + uint64_t vm_alignment = alignment; + + /* Increase the VM alignment for faster address translation. */ + if (size >= ws->info.pte_fragment_size) + vm_alignment = MAX2(vm_alignment, ws->info.pte_fragment_size); + + /* Gfx9: Increase the VM alignment to the most significant bit set + * in the size for faster address translation. + */ + if (ws->info.chip_class >= GFX9) { + unsigned msb = util_last_bit64(size); /* 0 = no bit is set */ + uint64_t msb_alignment = msb ? 1ull << (msb - 1) : 0; + + vm_alignment = MAX2(vm_alignment, msb_alignment); + } + return vm_alignment; +} + static struct amdgpu_winsys_bo *amdgpu_create_bo(struct amdgpu_winsys *ws, uint64_t size, unsigned alignment, @@ -513,26 +534,12 @@ static struct amdgpu_winsys_bo *amdgpu_create_bo(struct amdgpu_winsys *ws, va_gap_size = ws->check_vm ? MAX2(4 * alignment, 64 * 1024) : 0; - uint64_t vm_alignment = alignment; - - /* Increase the VM alignment for faster address translation. */ - if (size >= ws->info.pte_fragment_size) - vm_alignment = MAX2(vm_alignment, ws->info.pte_fragment_size); - - /* Gfx9: Increase the VM alignment to the most significant bit set - * in the size for faster address translation. - */ - if (ws->info.chip_class >= GFX9) { - unsigned msb = util_last_bit64(size); /* 0 = no bit is set */ - uint64_t msb_alignment = msb ? 1ull << (msb - 1) : 0; - - vm_alignment = MAX2(vm_alignment, msb_alignment); - } - r = amdgpu_va_range_alloc(ws->dev, amdgpu_gpu_va_range_general, - size + va_gap_size, vm_alignment, 0, &va, &va_handle, + size + va_gap_size, + amdgpu_get_optimal_vm_alignment(ws, size, alignment), + 0, &va, &va_handle, (flags & RADEON_FLAG_32BIT ? AMDGPU_VA_RANGE_32_BIT : 0) | - AMDGPU_VA_RANGE_HIGH); + AMDGPU_VA_RANGE_HIGH); if (r) goto error_va_alloc; @@ -1455,8 +1462,10 @@ static struct pb_buffer *amdgpu_bo_from_handle(struct radeon_winsys *rws, goto error; r = amdgpu_va_range_alloc(ws->dev, amdgpu_gpu_va_range_general, - result.alloc_size, vm_alignment, 0, &va, &va_handle, - AMDGPU_VA_RANGE_HIGH); + result.alloc_size, + amdgpu_get_optimal_vm_alignment(ws, result.alloc_size, + vm_alignment), + 0, &va, &va_handle, AMDGPU_VA_RANGE_HIGH); if (r) goto error; |