diff options
| author | Xavi Zhang <[email protected]> | 2014-07-09 02:46:00 -0400 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2017-03-30 14:44:33 +0200 |
| commit | 3614999878fd1335e69ecb0d181a9f6d2b91e3f8 (patch) | |
| tree | d769ba917209ada212e53ac62b3a0c36ccb923a3 /src/gallium/winsys/amdgpu | |
| parent | c12e35065af693fcad866d2089adf277a6109683 (diff) | |
amdgpu/addrlib: Rewrite tile mode optmization code
Note: remove reference to degrade4Space and use opt4Space instead.
Diffstat (limited to 'src/gallium/winsys/amdgpu')
| -rw-r--r-- | src/gallium/winsys/amdgpu/drm/amdgpu_surface.c | 12 |
1 files changed, 5 insertions, 7 deletions
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c index abe2b2a67af..8632f0687fc 100644 --- a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c @@ -124,7 +124,6 @@ ADDR_HANDLE amdgpu_addr_create(struct amdgpu_winsys *ws) createFlags.value = 0; createFlags.useTileIndex = 1; - createFlags.degradeBaseLevel = 1; createFlags.useHtileSliceAlign = 1; addrCreateInput.chipEngine = CIASICIDGFXENGINE_SOUTHERNISLAND; @@ -401,11 +400,10 @@ static int amdgpu_surface_init(struct radeon_winsys *rws, /* Only degrade the tile mode for space if TC-compatible HTILE hasn't been * requested, because TC-compatible HTILE requires 2D tiling. */ - AddrSurfInfoIn.flags.degrade4Space = !AddrSurfInfoIn.flags.tcCompatible && - !AddrSurfInfoIn.flags.fmask && - tex->nr_samples <= 1 && - (flags & RADEON_SURF_OPTIMIZE_FOR_SPACE); - AddrSurfInfoIn.flags.opt4Space = AddrSurfInfoIn.flags.degrade4Space; + AddrSurfInfoIn.flags.opt4Space = !AddrSurfInfoIn.flags.tcCompatible && + !AddrSurfInfoIn.flags.fmask && + tex->nr_samples <= 1 && + (flags & RADEON_SURF_OPTIMIZE_FOR_SPACE); /* DCC notes: * - If we add MSAA support, keep in mind that CB can't decompress 8bpp @@ -447,7 +445,7 @@ static int amdgpu_surface_init(struct radeon_winsys *rws, AddrTileInfoIn.macroAspectRatio = surf->mtilea; AddrTileInfoIn.tileSplitBytes = surf->tile_split; AddrTileInfoIn.pipeConfig = surf->pipe_config + 1; /* +1 compared to GB_TILE_MODE */ - AddrSurfInfoIn.flags.degrade4Space = 0; + AddrSurfInfoIn.flags.opt4Space = 0; AddrSurfInfoIn.pTileInfo = &AddrTileInfoIn; /* If AddrSurfInfoIn.pTileInfo is set, Addrlib doesn't set |