summaryrefslogtreecommitdiffstats
path: root/src/gallium/winsys/amdgpu
diff options
context:
space:
mode:
authorJason Ekstrand <[email protected]>2017-12-14 22:10:10 -0800
committerJason Ekstrand <[email protected]>2018-01-25 13:58:55 -0800
commitdb682b8f0eafd3b9d58e736e9e2f520943a89942 (patch)
treea86988c40463da1ad380ea89801cba2ff91eef7c /src/gallium/winsys/amdgpu
parentaf9d4ce4805412f5fb830e4c3b0e3887dc69c96c (diff)
i965/fs: Reset the register file to VGRF in lower_integer_multiplication
18fde36ced4279f2577097a1a7d31b55f2f5f141 changed the way temporary registers were allocated in lower_integer_multiplication so that we allocate regs_written(inst) space and keep the stride of the original destination register. This was to ensure that any MUL which originally followed the CHV/BXT integer multiply regioning restrictions would continue to follow those restrictions even after lowering. This works fine except that I forgot to reset the register file to VGRF so, even though they were assigned a number from alloc.allocate(), they had the wrong register file. This caused some GLES 3.0 CTS tests to start failing on Sandy Bridge due to attempted reads from the MRF: ES3-CTS.functional.shaders.precision.int.highp_mul_fragment.snbm64 ES3-CTS.functional.shaders.precision.int.mediump_mul_fragment.snbm64 ES3-CTS.functional.shaders.precision.int.lowp_mul_fragment.snbm64 ES3-CTS.functional.shaders.precision.uint.highp_mul_fragment.snbm64 ES3-CTS.functional.shaders.precision.uint.mediump_mul_fragment.snbm64 ES3-CTS.functional.shaders.precision.uint.lowp_mul_fragment.snbm64 This commit remedies this problem by, instead of copying inst->dst and overwriting nr, just make a new register and set the region to match inst->dst. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103626 Fixes: 18fde36ced4279f2577097a1a7d31b55f2f5f141 Cc: "17.3" <[email protected]> Reviewed-by: Matt Turner <[email protected]>
Diffstat (limited to 'src/gallium/winsys/amdgpu')
0 files changed, 0 insertions, 0 deletions