diff options
| author | Marek Olšák <[email protected]> | 2016-11-11 21:14:03 +0100 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2016-11-21 21:44:35 +0100 |
| commit | 49fa4a4e600cbb35c43a85fab2ed4aac3e6acccf (patch) | |
| tree | 29c9e9b7a64153b182fe40eae4d85d79971bbef1 /src/gallium/winsys/amdgpu | |
| parent | 44a3f2ee0974003597b0574f99c2440361d61b35 (diff) | |
gallium/radeon: add RADEON_SURF_OPTIMIZE_FOR_SPACE
FORCE_TILING should disable it. It has no effect now, but that may change
soon.
Tested-by: Edmondo Tommasina <[email protected]>
Reviewed-by: Nicolai Hähnle <[email protected]>
Diffstat (limited to 'src/gallium/winsys/amdgpu')
| -rw-r--r-- | src/gallium/winsys/amdgpu/drm/amdgpu_surface.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c index d65dae72661..d8ab28b36fd 100644 --- a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c @@ -402,7 +402,9 @@ static int amdgpu_surface_init(struct radeon_winsys *rws, * requested, because TC-compatible HTILE requires 2D tiling. */ AddrSurfInfoIn.flags.degrade4Space = !AddrSurfInfoIn.flags.tcCompatible && - !(flags & RADEON_SURF_FMASK); + !AddrSurfInfoIn.flags.fmask && + tex->nr_samples <= 1 && + (flags & RADEON_SURF_OPTIMIZE_FOR_SPACE); /* DCC notes: * - If we add MSAA support, keep in mind that CB can't decompress 8bpp |