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authorMarek Olšák <[email protected]>2016-06-08 20:24:21 +0200
committerMarek Olšák <[email protected]>2016-06-14 20:22:16 +0200
commit789618e3b4619225f1e86d52f7b692bf6eb866eb (patch)
treea9fe13e713627cb7d6c3bae7881b3e8325a991ff /src/gallium/winsys/amdgpu
parent63c5d5c6c46c8472ee7a8241a0f80f13d79cb8cd (diff)
gallium/radeon: add micro_tile_mode to radeon_surf
for easier access Reviewed-by: Nicolai Hähnle <[email protected]>
Diffstat (limited to 'src/gallium/winsys/amdgpu')
-rw-r--r--src/gallium/winsys/amdgpu/drm/amdgpu_surface.c15
1 files changed, 15 insertions, 0 deletions
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
index 9f52588c147..a45bcb0f776 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
@@ -255,6 +255,20 @@ static int compute_level(struct amdgpu_winsys *ws,
return 0;
}
+#define G_009910_MICRO_TILE_MODE(x) (((x) >> 0) & 0x03)
+#define G_009910_MICRO_TILE_MODE_NEW(x) (((x) >> 22) & 0x07)
+
+static void set_micro_tile_mode(struct radeon_surf *surf,
+ struct radeon_info *info)
+{
+ uint32_t tile_mode = info->si_tile_mode_array[surf->tiling_index[0]];
+
+ if (info->chip_class >= CIK)
+ surf->micro_tile_mode = G_009910_MICRO_TILE_MODE_NEW(tile_mode);
+ else
+ surf->micro_tile_mode = G_009910_MICRO_TILE_MODE(tile_mode);
+}
+
static int amdgpu_surface_init(struct radeon_winsys *rws,
struct radeon_surf *surf)
{
@@ -411,6 +425,7 @@ static int amdgpu_surface_init(struct radeon_winsys *rws,
if (level == 0) {
surf->bo_alignment = AddrSurfInfoOut.baseAlign;
surf->pipe_config = AddrSurfInfoOut.pTileInfo->pipeConfig - 1;
+ set_micro_tile_mode(surf, &ws->info);
/* For 2D modes only. */
if (AddrSurfInfoOut.tileMode >= ADDR_TM_2D_TILED_THIN1) {