diff options
| author | Marek Olšák <[email protected]> | 2016-10-23 21:26:43 +0200 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2016-10-26 13:02:58 +0200 |
| commit | 2a2e53757796b3fed3119cb033e5cf5144843850 (patch) | |
| tree | 760336dd10360929fb72761c9d5d9a2d88e48a31 /src/gallium/winsys/amdgpu | |
| parent | 67a44c97afb72812639039eb4594592c91c9ead5 (diff) | |
gallium/radeon: rename bo_size -> surf_size, bo_alignment -> surf_alignment
these names were misleading.
Reviewed-by: Nicolai Hähnle <[email protected]>
Diffstat (limited to 'src/gallium/winsys/amdgpu')
| -rw-r--r-- | src/gallium/winsys/amdgpu/drm/amdgpu_surface.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c index e6a26188677..27c425cd0ac 100644 --- a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c @@ -189,7 +189,7 @@ static int compute_level(struct amdgpu_winsys *ws, } surf_level = is_stencil ? &surf->stencil_level[level] : &surf->level[level]; - surf_level->offset = align64(surf->bo_size, AddrSurfInfoOut->baseAlign); + surf_level->offset = align64(surf->surf_size, AddrSurfInfoOut->baseAlign); surf_level->slice_size = AddrSurfInfoOut->sliceSize; surf_level->pitch_bytes = AddrSurfInfoOut->pitch * (is_stencil ? 1 : surf->bpe); surf_level->nblk_x = AddrSurfInfoOut->pitch; @@ -214,7 +214,7 @@ static int compute_level(struct amdgpu_winsys *ws, else surf->tiling_index[level] = AddrSurfInfoOut->tileIndex; - surf->bo_size = surf_level->offset + AddrSurfInfoOut->surfSize; + surf->surf_size = surf_level->offset + AddrSurfInfoOut->surfSize; /* Clear DCC fields at the beginning. */ surf_level->dcc_offset = 0; @@ -484,7 +484,7 @@ static int amdgpu_surface_init(struct radeon_winsys *rws, } } - surf->bo_size = 0; + surf->surf_size = 0; surf->dcc_size = 0; surf->dcc_alignment = 1; surf->htile_size = 0; @@ -499,7 +499,7 @@ static int amdgpu_surface_init(struct radeon_winsys *rws, return r; if (level == 0) { - surf->bo_alignment = AddrSurfInfoOut.baseAlign; + surf->surf_alignment = AddrSurfInfoOut.baseAlign; surf->pipe_config = AddrSurfInfoOut.pTileInfo->pipeConfig - 1; set_micro_tile_mode(surf, &ws->info); @@ -552,7 +552,7 @@ static int amdgpu_surface_init(struct radeon_winsys *rws, * complicated. */ if (surf->dcc_size && tex->last_level > 0) { - surf->dcc_size = align64(surf->bo_size >> 8, + surf->dcc_size = align64(surf->surf_size >> 8, ws->info.pipe_interleave_bytes * ws->info.num_tile_pipes); } |