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authorBas Nieuwenhuizen <[email protected]>2016-04-14 02:11:07 +0200
committerBas Nieuwenhuizen <[email protected]>2016-04-19 18:10:30 +0200
commit7201230582e060aa2eb79c825d3188b437ef7bb8 (patch)
tree86498170f28ccec8bbc85b302d9b7cc205d26081 /src/gallium/winsys/amdgpu
parent7997b5f005d4051e84bf64d6d1294f3da5076e5a (diff)
winsys/amdgpu: Enlarge const IB size.
Necessary to prevent performance regressions due to extra flushing. Probably should enlarge it even further when also updating uniforms through the CE, but this seems large enough for now. v2: Add preamble IB. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
Diffstat (limited to 'src/gallium/winsys/amdgpu')
-rw-r--r--src/gallium/winsys/amdgpu/drm/amdgpu_cs.c28
1 files changed, 20 insertions, 8 deletions
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
index 01826603912..69902c45e65 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
@@ -199,14 +199,26 @@ amdgpu_ctx_query_reset_status(struct radeon_winsys_ctx *rwctx)
/* COMMAND SUBMISSION */
static bool amdgpu_get_new_ib(struct radeon_winsys *ws, struct amdgpu_ib *ib,
- struct amdgpu_cs_ib_info *info)
+ struct amdgpu_cs_ib_info *info, unsigned ib_type)
{
/* Small IBs are better than big IBs, because the GPU goes idle quicker
* and there is less waiting for buffers and fences. Proof:
* http://www.phoronix.com/scan.php?page=article&item=mesa-111-si&num=1
*/
- const unsigned buffer_size = 128 * 1024 * 4;
- const unsigned ib_size = 20 * 1024 * 4;
+ unsigned buffer_size, ib_size;
+
+ switch (ib_type) {
+ case IB_CONST_PREAMBLE:
+ buffer_size = 4 * 1024 * 4;
+ ib_size = 1024 * 4;
+ case IB_CONST:
+ buffer_size = 512 * 1024 * 4;
+ ib_size = 128 * 1024 * 4;
+ break;
+ case IB_MAIN:
+ buffer_size = 128 * 1024 * 4;
+ ib_size = 20 * 1024 * 4;
+ }
ib->base.cdw = 0;
ib->base.buf = NULL;
@@ -350,7 +362,7 @@ amdgpu_cs_create(struct radeon_winsys_ctx *rwctx,
return NULL;
}
- if (!amdgpu_get_new_ib(&ctx->ws->base, &cs->main, &cs->ib[IB_MAIN])) {
+ if (!amdgpu_get_new_ib(&ctx->ws->base, &cs->main, &cs->ib[IB_MAIN], IB_MAIN)) {
amdgpu_destroy_cs_context(cs);
FREE(cs);
return NULL;
@@ -373,7 +385,7 @@ amdgpu_cs_add_const_ib(struct radeon_winsys_cs *rcs)
if (cs->ring_type != RING_GFX || cs->const_ib.ib_mapped)
return NULL;
- if (!amdgpu_get_new_ib(&ws->base, &cs->const_ib, &cs->ib[IB_CONST]))
+ if (!amdgpu_get_new_ib(&ws->base, &cs->const_ib, &cs->ib[IB_CONST], IB_CONST))
return NULL;
cs->request.number_of_ibs = 2;
@@ -760,12 +772,12 @@ static void amdgpu_cs_flush(struct radeon_winsys_cs *rcs,
cleanup:
amdgpu_cs_context_cleanup(cs);
- amdgpu_get_new_ib(&ws->base, &cs->main, &cs->ib[IB_MAIN]);
+ amdgpu_get_new_ib(&ws->base, &cs->main, &cs->ib[IB_MAIN], IB_MAIN);
if (cs->const_ib.ib_mapped)
- amdgpu_get_new_ib(&ws->base, &cs->const_ib, &cs->ib[IB_CONST]);
+ amdgpu_get_new_ib(&ws->base, &cs->const_ib, &cs->ib[IB_CONST], IB_CONST);
if (cs->const_preamble_ib.ib_mapped)
amdgpu_get_new_ib(&ws->base, &cs->const_preamble_ib,
- &cs->ib[IB_CONST_PREAMBLE]);
+ &cs->ib[IB_CONST_PREAMBLE], IB_CONST_PREAMBLE);
ws->num_cs_flushes++;
}