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| author | Marek Olšák <[email protected]> | 2019-12-12 21:09:50 -0500 |
|---|---|---|
| committer | Marge Bot <[email protected]> | 2019-12-16 20:06:07 +0000 |
| commit | 378444ce90b073d639c7c6877bfb062a35ac04cd (patch) | |
| tree | 5f07819bc472fcbbfc5143f32656b958f7f39e5b /src/gallium/tests/trivial | |
| parent | 4846aeaf572db40e612c042205d45174aa6e2d5f (diff) | |
radeonsi: allow generating VS prologs with 0 inputs
If "ls_vgpr_fix" is set, we use a prolog, but it can have 0 inputs.
Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3095>
Diffstat (limited to 'src/gallium/tests/trivial')
0 files changed, 0 insertions, 0 deletions