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authorIlia Mirkin <[email protected]>2015-09-06 04:51:29 -0400
committerIlia Mirkin <[email protected]>2015-09-08 17:13:12 -0400
commit39df725f731f75f488c75a4910169beb352213fb (patch)
treeda200929fb83393e34d1679648ad6754e9b7cafe /src/gallium/state_trackers/xa/xa-indent
parenta3b0b3fda5bd4fcedc84ef21bad5ddbe591a1cfb (diff)
nvc0: always emit a full shader colormask
Indications are that if the colormask indicates a single bit set on fermi, that value will always be read from $r0 instead of a potentially higher register (if e.g. green is set). Not to upset the counting logic, always set the header up with a full color mask for each RT. Such a situation can basically only ever happen with generated blit shaders. Fixes the following piglit on Fermi (Kepler is unaffected): fbo-stencil blit GL_DEPTH32F_STENCIL8 Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.6 11.0" <[email protected]>
Diffstat (limited to 'src/gallium/state_trackers/xa/xa-indent')
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