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authorAxel Davy <[email protected]>2015-01-14 12:33:21 +0100
committerAxel Davy <[email protected]>2015-02-06 00:07:19 +0100
commit0a4aaf1d411360c2a557fb016ffcb41f2701b9a2 (patch)
tree2167058c8079475a18db08dfb6a42e0e6848ade4 /src/gallium/state_trackers/nine
parentbf0adf248f3562e6fb205b31d14f650ab0a14c8e (diff)
st/nine: Implement AMD alpha to coverage
This D3D hack is supposed to be supported by all AMD SM2+ cards. Apps use it without checking if they are on AMD. Reviewed-by: Tiziano Bacocco <[email protected]> Signed-off-by: Axel Davy <[email protected]>
Diffstat (limited to 'src/gallium/state_trackers/nine')
-rw-r--r--src/gallium/state_trackers/nine/device9.c17
-rw-r--r--src/gallium/state_trackers/nine/nine_pipe.c2
-rw-r--r--src/gallium/state_trackers/nine/nine_state.c3
-rw-r--r--src/gallium/state_trackers/nine/nine_state.h3
4 files changed, 20 insertions, 5 deletions
diff --git a/src/gallium/state_trackers/nine/device9.c b/src/gallium/state_trackers/nine/device9.c
index a446c8f233c..63f9f16586e 100644
--- a/src/gallium/state_trackers/nine/device9.c
+++ b/src/gallium/state_trackers/nine/device9.c
@@ -2049,6 +2049,9 @@ NineDevice9_ResolveZ( struct NineDevice9 *This )
return D3D_OK;
}
+#define ALPHA_TO_COVERAGE_ENABLE MAKEFOURCC('A', '2', 'M', '1')
+#define ALPHA_TO_COVERAGE_DISABLE MAKEFOURCC('A', '2', 'M', '0')
+
HRESULT WINAPI
NineDevice9_SetRenderState( struct NineDevice9 *This,
D3DRENDERSTATETYPE State,
@@ -2059,8 +2062,18 @@ NineDevice9_SetRenderState( struct NineDevice9 *This,
DBG("This=%p State=%u(%s) Value=%08x\n", This,
State, nine_d3drs_to_string(State), Value);
- if (State == D3DRS_POINTSIZE && Value == RESZ_CODE)
- return NineDevice9_ResolveZ(This);
+ /* Amd hacks (equivalent to GL extensions) */
+ if (State == D3DRS_POINTSIZE) {
+ if (Value == RESZ_CODE)
+ return NineDevice9_ResolveZ(This);
+
+ if (Value == ALPHA_TO_COVERAGE_ENABLE ||
+ Value == ALPHA_TO_COVERAGE_DISABLE) {
+ state->rs[NINED3DRS_ALPHACOVERAGE] = (Value == ALPHA_TO_COVERAGE_ENABLE);
+ state->changed.group |= NINE_STATE_BLEND;
+ return D3D_OK;
+ }
+ }
user_assert(State < Elements(state->rs), D3DERR_INVALIDCALL);
diff --git a/src/gallium/state_trackers/nine/nine_pipe.c b/src/gallium/state_trackers/nine/nine_pipe.c
index 8543b27b838..0da0b20263d 100644
--- a/src/gallium/state_trackers/nine/nine_pipe.c
+++ b/src/gallium/state_trackers/nine/nine_pipe.c
@@ -146,7 +146,7 @@ nine_convert_blend_state(struct cso_context *ctx, const DWORD *rs)
blend.dither = !!rs[D3DRS_DITHERENABLE];
/* blend.alpha_to_one = 0; */
- /* blend.alpha_to_coverage = 0; */ /* XXX */
+ blend.alpha_to_coverage = !!rs[NINED3DRS_ALPHACOVERAGE];
blend.rt[0].blend_enable = !!rs[D3DRS_ALPHABLENDENABLE];
if (blend.rt[0].blend_enable) {
diff --git a/src/gallium/state_trackers/nine/nine_state.c b/src/gallium/state_trackers/nine/nine_state.c
index 972ed1f40be..1e533354d64 100644
--- a/src/gallium/state_trackers/nine/nine_state.c
+++ b/src/gallium/state_trackers/nine/nine_state.c
@@ -957,7 +957,8 @@ static const DWORD nine_render_state_defaults[NINED3DRS_LAST + 1] =
[D3DRS_DESTBLENDALPHA] = D3DBLEND_ZERO,
[D3DRS_BLENDOPALPHA] = D3DBLENDOP_ADD,
[NINED3DRS_VSPOINTSIZE] = FALSE,
- [NINED3DRS_RTMASK] = 0xf
+ [NINED3DRS_RTMASK] = 0xf,
+ [NINED3DRS_ALPHACOVERAGE] = FALSE
};
static const DWORD nine_tex_stage_state_defaults[NINED3DTSS_LAST + 1] =
{
diff --git a/src/gallium/state_trackers/nine/nine_state.h b/src/gallium/state_trackers/nine/nine_state.h
index 6e94e68ef1e..0cb293396d6 100644
--- a/src/gallium/state_trackers/nine/nine_state.h
+++ b/src/gallium/state_trackers/nine/nine_state.h
@@ -34,9 +34,10 @@
#define NINED3DRS_VSPOINTSIZE (D3DRS_BLENDOPALPHA + 1)
#define NINED3DRS_RTMASK (D3DRS_BLENDOPALPHA + 2)
#define NINED3DRS_ZBIASSCALE (D3DRS_BLENDOPALPHA + 3)
+#define NINED3DRS_ALPHACOVERAGE (D3DRS_BLENDOPALPHA + 4)
#define D3DRS_LAST D3DRS_BLENDOPALPHA
-#define NINED3DRS_LAST NINED3DRS_ZBIASSCALE /* 212 */
+#define NINED3DRS_LAST NINED3DRS_ALPHACOVERAGE /* 213 */
#define NINED3DSAMP_LAST NINED3DSAMP_SHADOW /* 15 */
#define NINED3DTSS_LAST D3DTSS_CONSTANT
#define NINED3DTS_LAST D3DTS_WORLDMATRIX(255)