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authorBas Nieuwenhuizen <[email protected]>2016-03-25 02:06:50 +0100
committerBas Nieuwenhuizen <[email protected]>2016-04-02 01:51:13 +0200
commit1a5c8c24b5791efa02a7beefa4ba1c49ae033c73 (patch)
treec63783871510b1ba41d5a12f187f51a336a6b79a /src/gallium/state_trackers/clover
parentbe5899dcf9a337548d8095a00060d4451b0df222 (diff)
gallium: distinguish between shader IR in get_compute_param
For radeonsi, native and TGSI use different compilers and this results in different limits for different IR's. The set we strictly need for radeonsi is only the MAX_BLOCK_SIZE and MAX_THREADS_PER_BLOCK params, but I added a few others as shader related that seemed like they would also typically depend on the compiler. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
Diffstat (limited to 'src/gallium/state_trackers/clover')
-rw-r--r--src/gallium/state_trackers/clover/core/device.cpp31
1 files changed, 17 insertions, 14 deletions
diff --git a/src/gallium/state_trackers/clover/core/device.cpp b/src/gallium/state_trackers/clover/core/device.cpp
index 1be2f6413f4..39f39f436c6 100644
--- a/src/gallium/state_trackers/clover/core/device.cpp
+++ b/src/gallium/state_trackers/clover/core/device.cpp
@@ -30,11 +30,12 @@ using namespace clover;
namespace {
template<typename T>
std::vector<T>
- get_compute_param(pipe_screen *pipe, pipe_compute_cap cap) {
- int sz = pipe->get_compute_param(pipe, cap, NULL);
+ get_compute_param(pipe_screen *pipe, pipe_shader_ir ir_format,
+ pipe_compute_cap cap) {
+ int sz = pipe->get_compute_param(pipe, ir_format, cap, NULL);
std::vector<T> v(sz / sizeof(T));
- pipe->get_compute_param(pipe, cap, &v.front());
+ pipe->get_compute_param(pipe, ir_format, cap, &v.front());
return v;
}
}
@@ -115,19 +116,19 @@ device::max_samplers() const {
cl_ulong
device::max_mem_global() const {
- return get_compute_param<uint64_t>(pipe,
+ return get_compute_param<uint64_t>(pipe, ir_format(),
PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE)[0];
}
cl_ulong
device::max_mem_local() const {
- return get_compute_param<uint64_t>(pipe,
+ return get_compute_param<uint64_t>(pipe, ir_format(),
PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE)[0];
}
cl_ulong
device::max_mem_input() const {
- return get_compute_param<uint64_t>(pipe,
+ return get_compute_param<uint64_t>(pipe, ir_format(),
PIPE_COMPUTE_CAP_MAX_INPUT_SIZE)[0];
}
@@ -146,30 +147,30 @@ device::max_const_buffers() const {
size_t
device::max_threads_per_block() const {
return get_compute_param<uint64_t>(
- pipe, PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK)[0];
+ pipe, ir_format(), PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK)[0];
}
cl_ulong
device::max_mem_alloc_size() const {
- return get_compute_param<uint64_t>(pipe,
+ return get_compute_param<uint64_t>(pipe, ir_format(),
PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE)[0];
}
cl_uint
device::max_clock_frequency() const {
- return get_compute_param<uint32_t>(pipe,
+ return get_compute_param<uint32_t>(pipe, ir_format(),
PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY)[0];
}
cl_uint
device::max_compute_units() const {
- return get_compute_param<uint32_t>(pipe,
+ return get_compute_param<uint32_t>(pipe, ir_format(),
PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS)[0];
}
bool
device::image_support() const {
- return get_compute_param<uint32_t>(pipe,
+ return get_compute_param<uint32_t>(pipe, ir_format(),
PIPE_COMPUTE_CAP_IMAGES_SUPPORTED)[0];
}
@@ -181,13 +182,15 @@ device::has_doubles() const {
std::vector<size_t>
device::max_block_size() const {
- auto v = get_compute_param<uint64_t>(pipe, PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE);
+ auto v = get_compute_param<uint64_t>(pipe, ir_format(),
+ PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE);
return { v.begin(), v.end() };
}
cl_uint
device::subgroup_size() const {
- return get_compute_param<uint32_t>(pipe, PIPE_COMPUTE_CAP_SUBGROUP_SIZE)[0];
+ return get_compute_param<uint32_t>(pipe, ir_format(),
+ PIPE_COMPUTE_CAP_SUBGROUP_SIZE)[0];
}
std::string
@@ -209,7 +212,7 @@ device::ir_format() const {
std::string
device::ir_target() const {
std::vector<char> target = get_compute_param<char>(
- pipe, PIPE_COMPUTE_CAP_IR_TARGET);
+ pipe, ir_format(), PIPE_COMPUTE_CAP_IR_TARGET);
return { target.data() };
}