diff options
| author | Marek Olšák <[email protected]> | 2018-07-25 00:41:48 -0400 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2018-08-29 15:31:41 -0400 |
| commit | 8f6e06d1608bff31165511787a06da8c635e6da0 (patch) | |
| tree | c4f492d663755c46fa10f9d70d9e53a0c746264d /src/gallium/include | |
| parent | d8033d4083d341f3351c8ca929935617b9b16f3a (diff) | |
gallium: add TGSI_MEMORY_STREAM_CACHE_POLICY
For internal radeonsi shaders.
Diffstat (limited to 'src/gallium/include')
| -rw-r--r-- | src/gallium/include/pipe/p_shader_tokens.h | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/src/gallium/include/pipe/p_shader_tokens.h b/src/gallium/include/pipe/p_shader_tokens.h index 08ed08156e7..bef826f23b5 100644 --- a/src/gallium/include/pipe/p_shader_tokens.h +++ b/src/gallium/include/pipe/p_shader_tokens.h @@ -790,16 +790,20 @@ struct tgsi_dst_register #define TGSI_MEMORY_COHERENT (1 << 0) #define TGSI_MEMORY_RESTRICT (1 << 1) #define TGSI_MEMORY_VOLATILE (1 << 2) +/* The "stream" cache policy will minimize memory cache usage if other + * memory operations need the cache. + */ +#define TGSI_MEMORY_STREAM_CACHE_POLICY (1 << 3) /** * Specifies the type of memory access to do for the LOAD/STORE instruction. */ struct tgsi_instruction_memory { - unsigned Qualifier : 3; /* TGSI_MEMORY_ */ + unsigned Qualifier : 4; /* TGSI_MEMORY_ */ unsigned Texture : 8; /* only for images: TGSI_TEXTURE_ */ unsigned Format : 10; /* only for images: PIPE_FORMAT_ */ - unsigned Padding : 11; + unsigned Padding : 10; }; #define TGSI_MEMBAR_SHADER_BUFFER (1 << 0) |