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authorEric Anholt <[email protected]>2017-07-27 12:05:56 -0700
committerEric Anholt <[email protected]>2017-10-10 10:45:22 -0700
commitac0051a5075879970f12f614890c9c6d732663b6 (patch)
tree39a723409f8052a04dce2a5b1d2c9bfac2ba6be7 /src/gallium/include
parent4aa700e0e09d694ecae60ee04b11ca6e7458afe7 (diff)
gallium: Create a new PIPE_CAP_TILE_RASTER_ORDER for vc4.
Because vc4 can control the order that tiles are rasterized in, we can use it to implement overlapping blits using normal drawing and GL_ARB_texture_barrier, as long as we can tell the kernel what order to render the tiles in. This commit introduces the core gallium support, vc4 changes will follow. v2: Fix on the simulator. v3: Add the cap (disabled) to other drivers, add rst docs for the cap. v4: Rebase on PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS v5: Drop vc4 changes from this commit, for clarity. Reviewed-by: Nicolai Hähnle <[email protected]> (v3)
Diffstat (limited to 'src/gallium/include')
-rw-r--r--src/gallium/include/pipe/p_defines.h1
-rw-r--r--src/gallium/include/pipe/p_state.h10
2 files changed, 11 insertions, 0 deletions
diff --git a/src/gallium/include/pipe/p_defines.h b/src/gallium/include/pipe/p_defines.h
index 212c4af8f70..11af6c8d0d8 100644
--- a/src/gallium/include/pipe/p_defines.h
+++ b/src/gallium/include/pipe/p_defines.h
@@ -778,6 +778,7 @@ enum pipe_cap
PIPE_CAP_MEMOBJ,
PIPE_CAP_LOAD_CONSTBUF,
PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS,
+ PIPE_CAP_TILE_RASTER_ORDER,
};
#define PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50 (1 << 0)
diff --git a/src/gallium/include/pipe/p_state.h b/src/gallium/include/pipe/p_state.h
index 86c7751eb18..10bf678652d 100644
--- a/src/gallium/include/pipe/p_state.h
+++ b/src/gallium/include/pipe/p_state.h
@@ -125,6 +125,16 @@ struct pipe_rasterizer_state
unsigned rasterizer_discard:1;
/**
+ * Exposed by PIPE_CAP_TILE_RASTER_ORDER. When true,
+ * tile_raster_order_increasing_* indicate the order that the rasterizer
+ * should render tiles, to meet the requirements of
+ * GL_MESA_tile_raster_order.
+ */
+ unsigned tile_raster_order_fixed:1;
+ unsigned tile_raster_order_increasing_x:1;
+ unsigned tile_raster_order_increasing_y:1;
+
+ /**
* When false, depth clipping is disabled and the depth value will be
* clamped later at the per-pixel level before depth testing.
* This depends on PIPE_CAP_DEPTH_CLIP_DISABLE.