gallium/radeon: move pre-GFX9 radeon_bo_metadata.* to u.legacy.*

Reviewed-by: Nicolai Hähnle <[email protected]>

3 files changed, 57 insertions, 45 deletions

diff --git a/src/gallium/drivers/r300/r300_texture.c b/src/gallium/drivers/r300/r300_texture.c
index 32cbdcdb341..c202fbe9423 100644
--- a/src/gallium/drivers/r300/r300_texture.c
+++ b/src/gallium/drivers/r300/r300_texture.c
@@ -1132,9 +1132,9 @@ r300_texture_create_object(struct r300_screen *rscreen,
                 util_format_is_depth_or_stencil(base->format) ? "depth" : "color");
     }
 
-    tiling.microtile = tex->tex.microtile;
-    tiling.macrotile = tex->tex.macrotile[0];
-    tiling.stride = tex->tex.stride_in_bytes[0];
+    tiling.u.legacy.microtile = tex->tex.microtile;
+    tiling.u.legacy.macrotile = tex->tex.macrotile[0];
+    tiling.u.legacy.stride = tex->tex.stride_in_bytes[0];
     rws->buffer_set_metadata(tex->buf, &tiling);
 
     return tex;
@@ -1195,20 +1195,20 @@ struct pipe_resource *r300_texture_from_handle(struct pipe_screen *screen,
 
     /* Enforce a microtiled zbuffer. */
     if (util_format_is_depth_or_stencil(base->format) &&
-        tiling.microtile == RADEON_LAYOUT_LINEAR) {
+        tiling.u.legacy.microtile == RADEON_LAYOUT_LINEAR) {
         switch (util_format_get_blocksize(base->format)) {
             case 4:
-                tiling.microtile = RADEON_LAYOUT_TILED;
+                tiling.u.legacy.microtile = RADEON_LAYOUT_TILED;
                 break;
 
             case 2:
-                tiling.microtile = RADEON_LAYOUT_SQUARETILED;
+                tiling.u.legacy.microtile = RADEON_LAYOUT_SQUARETILED;
                 break;
         }
     }
 
     return (struct pipe_resource*)
-           r300_texture_create_object(rscreen, base, tiling.microtile, tiling.macrotile,
+           r300_texture_create_object(rscreen, base, tiling.u.legacy.microtile, tiling.u.legacy.macrotile,
                                       stride, buffer);
 }
 
diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c
index ece1e806e3e..353e942aaa2 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -281,24 +281,29 @@ static int r600_init_surface(struct r600_common_screen *rscreen,
 	return 0;
 }
 
-static void r600_texture_init_metadata(struct r600_texture *rtex,
+static void r600_texture_init_metadata(struct r600_common_screen *rscreen,
+				       struct r600_texture *rtex,
 				       struct radeon_bo_metadata *metadata)
 {
 	struct radeon_surf *surface = &rtex->surface;
 
 	memset(metadata, 0, sizeof(*metadata));
-	metadata->microtile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_1D ?
-				   RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
-	metadata->macrotile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_2D ?
-				   RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
-	metadata->pipe_config = surface->u.legacy.pipe_config;
-	metadata->bankw = surface->u.legacy.bankw;
-	metadata->bankh = surface->u.legacy.bankh;
-	metadata->tile_split = surface->u.legacy.tile_split;
-	metadata->mtilea = surface->u.legacy.mtilea;
-	metadata->num_banks = surface->u.legacy.num_banks;
-	metadata->stride = surface->u.legacy.level[0].nblk_x * surface->bpe;
-	metadata->scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
+
+	if (rscreen->chip_class >= GFX9) {
+	} else {
+		metadata->u.legacy.microtile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_1D ?
+					   RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
+		metadata->u.legacy.macrotile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_2D ?
+					   RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
+		metadata->u.legacy.pipe_config = surface->u.legacy.pipe_config;
+		metadata->u.legacy.bankw = surface->u.legacy.bankw;
+		metadata->u.legacy.bankh = surface->u.legacy.bankh;
+		metadata->u.legacy.tile_split = surface->u.legacy.tile_split;
+		metadata->u.legacy.mtilea = surface->u.legacy.mtilea;
+		metadata->u.legacy.num_banks = surface->u.legacy.num_banks;
+		metadata->u.legacy.stride = surface->u.legacy.level[0].nblk_x * surface->bpe;
+		metadata->u.legacy.scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
+	}
 }
 
 static void r600_eliminate_fast_color_clear(struct r600_common_context *rctx,
@@ -526,7 +531,7 @@ static boolean r600_texture_get_handle(struct pipe_screen* screen,
 
 		/* Set metadata. */
 		if (!res->is_shared || update_metadata) {
-			r600_texture_init_metadata(rtex, &metadata);
+			r600_texture_init_metadata(rscreen, rtex, &metadata);
 			if (rscreen->query_opaque_metadata)
 				rscreen->query_opaque_metadata(rscreen, rtex,
 							       &metadata);
@@ -1265,22 +1270,25 @@ static struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen
 
 	rscreen->ws->buffer_get_metadata(buf, &metadata);
 
-	surface.u.legacy.pipe_config = metadata.pipe_config;
-	surface.u.legacy.bankw = metadata.bankw;
-	surface.u.legacy.bankh = metadata.bankh;
-	surface.u.legacy.tile_split = metadata.tile_split;
-	surface.u.legacy.mtilea = metadata.mtilea;
-	surface.u.legacy.num_banks = metadata.num_banks;
-
-	if (metadata.macrotile == RADEON_LAYOUT_TILED)
-		array_mode = RADEON_SURF_MODE_2D;
-	else if (metadata.microtile == RADEON_LAYOUT_TILED)
-		array_mode = RADEON_SURF_MODE_1D;
-	else
-		array_mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
+	if (rscreen->chip_class >= GFX9) {
+	} else {
+		surface.u.legacy.pipe_config = metadata.u.legacy.pipe_config;
+		surface.u.legacy.bankw = metadata.u.legacy.bankw;
+		surface.u.legacy.bankh = metadata.u.legacy.bankh;
+		surface.u.legacy.tile_split = metadata.u.legacy.tile_split;
+		surface.u.legacy.mtilea = metadata.u.legacy.mtilea;
+		surface.u.legacy.num_banks = metadata.u.legacy.num_banks;
+
+		if (metadata.u.legacy.macrotile == RADEON_LAYOUT_TILED)
+			array_mode = RADEON_SURF_MODE_2D;
+		else if (metadata.u.legacy.microtile == RADEON_LAYOUT_TILED)
+			array_mode = RADEON_SURF_MODE_1D;
+		else
+			array_mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
+	}
 
 	r = r600_init_surface(rscreen, &surface, templ, array_mode, stride,
-			      offset, true, metadata.scanout, false, false);
+			      offset, true, metadata.u.legacy.scanout, false, false);
 	if (r) {
 		return NULL;
 	}
diff --git a/src/gallium/drivers/radeon/radeon_winsys.h b/src/gallium/drivers/radeon/radeon_winsys.h
index bfc067d7639..e25f60cb904 100644
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -237,16 +237,20 @@ struct radeon_bo_metadata {
     /* Tiling flags describing the texture layout for display code
      * and DRI sharing.
      */
-    enum radeon_bo_layout   microtile;
-    enum radeon_bo_layout   macrotile;
-    unsigned                pipe_config;
-    unsigned                bankw;
-    unsigned                bankh;
-    unsigned                tile_split;
-    unsigned                mtilea;
-    unsigned                num_banks;
-    unsigned                stride;
-    bool                    scanout;
+    union {
+        struct {
+            enum radeon_bo_layout   microtile;
+            enum radeon_bo_layout   macrotile;
+            unsigned                pipe_config;
+            unsigned                bankw;
+            unsigned                bankh;
+            unsigned                tile_split;
+            unsigned                mtilea;
+            unsigned                num_banks;
+            unsigned                stride;
+            bool                    scanout;
+        } legacy;
+    } u;
 
     /* Additional metadata associated with the buffer, in bytes.
      * The maximum size is 64 * 4. This is opaque for the winsys & kernel.