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authorGuido Günther <agx@sigxcpu.org>2018-09-17 16:06:57 +0200
committerLucas Stach <l.stach@pengutronix.de>2018-11-15 16:38:35 +0100
commitab5653680e169434a730ff23f3facdae0ca2632d (patch)
tree559792dec62183935a2ed33f0ba10fb689bf2935 /src/gallium/drivers
parent52368ef83a1b9998707cdc1703e38768a8c5b06d (diff)
etnaviv: Make sure rs alignment checks match
etna_resource_alloc and etna_resource_from_handle currently use different checks. This leads to etna_resource_from_handle:492: target=2, format=PIPE_FORMAT_B8G8R8X8_UNORM, 1080x1920x1, array_size=1, last_level=0, nr_samples=0, usage=0, bind=8000a, flags=0 etna_resource_from_handle:541: BO stride 4320 is too small for RS engine width padding (4352, format PIPE_FORMAT_B8G8R8X8_UNORM) since etna_resource_from_handle wants to be aligned to a 16 byte boundary while the etna_resource_alloc does not. Adjust the two checks by using a common function. Broken by baff59ebf07a114f95ad66d1f54e4b1f409eebee Signed-off-by: Guido Günther <guido.gunther@puri.sm> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Diffstat (limited to 'src/gallium/drivers')
-rw-r--r--src/gallium/drivers/etnaviv/etnaviv_resource.c19
1 files changed, 13 insertions, 6 deletions
diff --git a/src/gallium/drivers/etnaviv/etnaviv_resource.c b/src/gallium/drivers/etnaviv/etnaviv_resource.c
index 3808c293e6e..c0091288030 100644
--- a/src/gallium/drivers/etnaviv/etnaviv_resource.c
+++ b/src/gallium/drivers/etnaviv/etnaviv_resource.c
@@ -176,6 +176,15 @@ setup_miptree(struct etna_resource *rsc, unsigned paddingX, unsigned paddingY,
return size;
}
+/* Is rs alignment needed? */
+static bool is_rs_align(struct etna_screen *screen,
+ const struct pipe_resource *tmpl)
+{
+ return screen->specs.use_blt ? false : (
+ VIV_FEATURE(screen, chipMinorFeatures1, TEXTURE_HALIGN) ||
+ !etna_resource_sampler_only(tmpl));
+}
+
/* Create a new resource object, using the given template info */
struct pipe_resource *
etna_resource_alloc(struct pipe_screen *pscreen, unsigned layout,
@@ -217,11 +226,9 @@ etna_resource_alloc(struct pipe_screen *pscreen, unsigned layout,
* resolve engine's width. If not, we must not align resources used
* only for textures. If this GPU uses the BLT engine, never do RS align.
*/
- bool rs_align = screen->specs.use_blt ? false : (
- VIV_FEATURE(screen, chipMinorFeatures1, TEXTURE_HALIGN) ||
- !etna_resource_sampler_only(templat));
- etna_layout_multiple(layout, screen->specs.pixel_pipes, rs_align, &paddingX,
- &paddingY, &halign);
+ etna_layout_multiple(layout, screen->specs.pixel_pipes,
+ is_rs_align (screen, templat),
+ &paddingX, &paddingY, &halign);
assert(paddingX && paddingY);
} else {
/* Compressed textures are padded to their block size, but we don't have
@@ -519,7 +526,7 @@ etna_resource_from_handle(struct pipe_screen *pscreen,
/* Determine padding of the imported resource. */
unsigned paddingX = 0, paddingY = 0;
etna_layout_multiple(rsc->layout, screen->specs.pixel_pipes,
- VIV_FEATURE(screen, chipMinorFeatures1, TEXTURE_HALIGN),
+ is_rs_align(screen, tmpl),
&paddingX, &paddingY, &rsc->halign);
if (!screen->specs.use_blt)