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authorAlex Deucher <[email protected]>2015-11-13 16:21:09 -0500
committerAlex Deucher <[email protected]>2015-11-16 10:09:34 -0500
commit5b37d8b50cfc9a390f8320557a332a3c75b91953 (patch)
treef879917f2678710c70867f0d2991b75d075191ea /src/gallium/drivers
parent2ca018cb65e1001e890f3dccbe65f757ed8da3f8 (diff)
radeonsi: use proper GRBM_GFX_INDEX offset for CI+
The offset is different on CI and newer. Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
Diffstat (limited to 'src/gallium/drivers')
-rw-r--r--src/gallium/drivers/radeonsi/si_state.c16
1 files changed, 12 insertions, 4 deletions
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index 93847d5ec2f..f0f87da46ea 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -3256,21 +3256,29 @@ si_write_harvested_raster_configs(struct si_context *sctx,
}
}
- /* GRBM_GFX_INDEX is privileged on VI */
- if (sctx->b.chip_class <= CIK)
+ /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
+ if (sctx->b.chip_class < CIK)
si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
SE_INDEX(se) | SH_BROADCAST_WRITES |
INSTANCE_BROADCAST_WRITES);
+ else
+ si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
+ S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) |
+ S_030800_INSTANCE_BROADCAST_WRITES(1));
si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
if (sctx->b.chip_class >= CIK)
si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
}
- /* GRBM_GFX_INDEX is privileged on VI */
- if (sctx->b.chip_class <= CIK)
+ /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
+ if (sctx->b.chip_class < CIK)
si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
SE_BROADCAST_WRITES | SH_BROADCAST_WRITES |
INSTANCE_BROADCAST_WRITES);
+ else
+ si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
+ S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
+ S_030800_INSTANCE_BROADCAST_WRITES(1));
}
static void si_init_config(struct si_context *sctx)