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authorIlia Mirkin <[email protected]>2017-10-09 20:42:59 -0400
committerIlia Mirkin <[email protected]>2017-10-09 20:42:59 -0400
commitce6da2a02632cc81373b5e26881c02872e80c30b (patch)
tree4f69b816e68e4b048c411b7a6a518f3842d9ae66 /src/gallium/drivers
parent8ee6828df7f5d04715caf8b0433ca24c0e1a6ba1 (diff)
nv50/ir: fix 64-bit integer shifts
TGSI was adjusted to always pass in 64-bit integers but nouveau was left with the old semantics. Update to the new thing. Fixes: d10fbe5159 (st/glsl_to_tgsi: fix 64-bit integer bit shifts) Reported-by: Karol Herbst <[email protected]> Cc: [email protected]
Diffstat (limited to 'src/gallium/drivers')
-rw-r--r--src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp4
1 files changed, 3 insertions, 1 deletions
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
index 27806057c5b..34351dab518 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
@@ -4028,7 +4028,9 @@ Converter::handleInstruction(const struct tgsi_full_instruction *insn)
tmp[0] = fetchSrc(0, c);
tmp[1] = fetchSrc(0, c + 1);
mkOp2(OP_MERGE, TYPE_U64, src0, tmp[0], tmp[1]);
- src1 = fetchSrc(1, c / 2);
+ // Theoretically src1 is a 64-bit value but in practice only the low
+ // bits matter. The IR expects this to be a 32-bit value.
+ src1 = fetchSrc(1, c);
mkOp2(op, dstTy, dst, src0, src1);
mkSplit(&dst0[c], 4, dst);
c++;