radeonsi: disable alpha-to-coverage for integer colorbuffers

Reviewed-by: Michel Dänzer <[email protected]>

2 files changed, 9 insertions, 1 deletions

diff --git a/src/gallium/drivers/radeonsi/radeonsi_shader.h b/src/gallium/drivers/radeonsi/radeonsi_shader.h
index d12892b3b6a..6c6b96e033a 100644
--- a/src/gallium/drivers/radeonsi/radeonsi_shader.h
+++ b/src/gallium/drivers/radeonsi/radeonsi_shader.h
@@ -145,6 +145,7 @@ struct si_pipe_shader {
 	unsigned			spi_ps_input_ena;
 	unsigned			spi_shader_col_format;
 	unsigned			cb_shader_mask;
+	bool				cb0_is_integer;
 	unsigned			sprite_coord_enable;
 	unsigned			so_strides[4];
 	union si_shader_key		key;
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
index ceaead0b71a..6be10c84cc9 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -136,7 +136,9 @@ static void si_pipe_shader_ps(struct pipe_context *ctx, struct si_pipe_shader *s
 
 	si_pm4_inval_shader_cache(pm4);
 
-	db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
+	db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
+			    S_02880C_ALPHA_TO_MASK_DISABLE(rctx->fb_cb0_is_integer);
+
 	for (i = 0; i < shader->shader.ninput; i++) {
 		switch (shader->shader.input[i].name) {
 		case TGSI_SEMANTIC_POSITION:
@@ -256,6 +258,7 @@ static void si_pipe_shader_ps(struct pipe_context *ctx, struct si_pipe_shader *s
 
 	si_pm4_set_reg(pm4, R_02880C_DB_SHADER_CONTROL, db_shader_control);
 
+	shader->cb0_is_integer = rctx->fb_cb0_is_integer;
 	shader->sprite_coord_enable = rctx->sprite_coord_enable;
 	si_pm4_bind_state(rctx, ps, shader->pm4);
 }
@@ -445,6 +448,10 @@ static void si_update_derived_state(struct r600_context *rctx)
 
 		ps_dirty = 0;
 	}
+	if (rctx->ps_shader->current->cb0_is_integer != rctx->fb_cb0_is_integer) {
+		si_pipe_shader_ps(ctx, rctx->ps_shader->current);
+		ps_dirty = 1;
+	}
 
 	if (ps_dirty) {
 		si_pm4_bind_state(rctx, ps, rctx->ps_shader->current->pm4);