diff options
| author | Michel Dänzer <[email protected]> | 2012-08-28 15:59:30 +0200 |
|---|---|---|
| committer | Michel Dänzer <[email protected]> | 2012-08-28 20:27:23 +0200 |
| commit | 70f9dbe298043f0e3914e6956ddcc0a098f7eca3 (patch) | |
| tree | 4487f3a6c7b5742b47ee08872a4fcae8c42912aa /src/gallium/drivers | |
| parent | 16e42a5dd065c09f6d561537009639906b22ce45 (diff) | |
radeon/llvm: Handle TGSI KIL opcode for SI.
Fixes piglit fp-kil and glBitmap() with radeonsi.
Signed-off-by: Michel Dänzer <[email protected]>
Reviewed-by: Tom Stellard <[email protected]>
Diffstat (limited to 'src/gallium/drivers')
| -rw-r--r-- | src/gallium/drivers/radeon/SIISelLowering.cpp | 35 | ||||
| -rw-r--r-- | src/gallium/drivers/radeon/SIISelLowering.h | 2 | ||||
| -rw-r--r-- | src/gallium/drivers/radeon/SIInstructions.td | 7 |
3 files changed, 44 insertions, 0 deletions
diff --git a/src/gallium/drivers/radeon/SIISelLowering.cpp b/src/gallium/drivers/radeon/SIISelLowering.cpp index 092c2fa67e2..31876bfd262 100644 --- a/src/gallium/drivers/radeon/SIISelLowering.cpp +++ b/src/gallium/drivers/radeon/SIISelLowering.cpp @@ -129,6 +129,9 @@ MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter( case AMDGPU::SI_INTERP_CONST: LowerSI_INTERP_CONST(MI, *BB, I); break; + case AMDGPU::SI_KIL: + LowerSI_KIL(MI, *BB, I, MRI); + break; case AMDGPU::SI_V_CNDLT: LowerSI_V_CNDLT(MI, *BB, I, MRI); break; @@ -193,6 +196,38 @@ void SITargetLowering::LowerSI_INTERP_CONST(MachineInstr *MI, MI->eraseFromParent(); } +void SITargetLowering::LowerSI_KIL(MachineInstr *MI, MachineBasicBlock &BB, + MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const +{ + // Clear this pixel from the exec mask if the operand is negative + BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::V_CMPX_LE_F32_e32), + AMDGPU::VCC) + .addReg(AMDGPU::SREG_LIT_0) + .addOperand(MI->getOperand(0)); + + // If the exec mask is non-zero, skip the next two instructions + BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::S_CBRANCH_EXECNZ)) + .addImm(3) + .addReg(AMDGPU::EXEC); + + // Exec mask is zero: Export to NULL target... + BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::EXP)) + .addImm(0) + .addImm(0x09) // V_008DFC_SQ_EXP_NULL + .addImm(0) + .addImm(1) + .addImm(1) + .addReg(AMDGPU::SREG_LIT_0) + .addReg(AMDGPU::SREG_LIT_0) + .addReg(AMDGPU::SREG_LIT_0) + .addReg(AMDGPU::SREG_LIT_0); + + // ... and terminate wavefront + BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::S_ENDPGM)); + + MI->eraseFromParent(); +} + void SITargetLowering::LowerSI_V_CNDLT(MachineInstr *MI, MachineBasicBlock &BB, MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const { diff --git a/src/gallium/drivers/radeon/SIISelLowering.h b/src/gallium/drivers/radeon/SIISelLowering.h index cf655a1dce7..9609311e814 100644 --- a/src/gallium/drivers/radeon/SIISelLowering.h +++ b/src/gallium/drivers/radeon/SIISelLowering.h @@ -33,6 +33,8 @@ class SITargetLowering : public AMDGPUTargetLowering MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const; void LowerSI_INTERP_CONST(MachineInstr *MI, MachineBasicBlock &BB, MachineBasicBlock::iterator I) const; + void LowerSI_KIL(MachineInstr *MI, MachineBasicBlock &BB, + MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const; void LowerSI_V_CNDLT(MachineInstr *MI, MachineBasicBlock &BB, MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const; diff --git a/src/gallium/drivers/radeon/SIInstructions.td b/src/gallium/drivers/radeon/SIInstructions.td index ee4c8f5a36f..11bc8012fbd 100644 --- a/src/gallium/drivers/radeon/SIInstructions.td +++ b/src/gallium/drivers/radeon/SIInstructions.td @@ -959,6 +959,13 @@ def SI_INTERP_CONST : InstSI < imm:$attr, SReg_32:$params))] >; +def SI_KIL : InstSI < + (outs), + (ins VReg_32:$src), + "SI_KIL $src", + [(int_AMDGPU_kill VReg_32:$src)] +>; + } // end usesCustomInserter // SI Psuedo branch instructions. These are used by the CFG structurizer pass |