vc4: Load the tile buffer before incrementally drawing.

We will want to occasionally disable this again when we do clear support.

v2: Squash with the previous commit (I accidentally committed at two
    stages of writing the change)

2 files changed, 50 insertions, 27 deletions

diff --git a/src/gallium/drivers/vc4/vc4_draw.c b/src/gallium/drivers/vc4/vc4_draw.c
index 932ea6535df..1d7956d1d4f 100644
--- a/src/gallium/drivers/vc4/vc4_draw.c
+++ b/src/gallium/drivers/vc4/vc4_draw.c
@@ -32,8 +32,11 @@
 
 static void
 vc4_rcl_tile_calls(struct vc4_context *vc4,
+                   struct vc4_surface *csurf,
                    uint32_t xtiles, uint32_t ytiles)
 {
+        struct vc4_resource *ctex = vc4_resource(csurf->base.texture);
+
         for (int x = 0; x < xtiles; x++) {
                 for (int y = 0; y < ytiles; y++) {
                         cl_u8(&vc4->rcl, VC4_PACKET_TILE_COORDINATES);
@@ -41,6 +44,15 @@ vc4_rcl_tile_calls(struct vc4_context *vc4,
                         cl_u8(&vc4->rcl, y);
 
                         cl_start_reloc(&vc4->rcl, 1);
+                        cl_u8(&vc4->rcl, VC4_PACKET_LOAD_TILE_BUFFER_GENERAL);
+                        cl_u8(&vc4->rcl,
+                              VC4_LOADSTORE_TILE_BUFFER_COLOR |
+                              VC4_LOADSTORE_TILE_BUFFER_FORMAT_RASTER);
+                        cl_u8(&vc4->rcl,
+                              VC4_LOADSTORE_TILE_BUFFER_RGBA8888);
+                        cl_reloc(vc4, &vc4->rcl, ctex->bo, csurf->offset);
+
+                        cl_start_reloc(&vc4->rcl, 1);
                         cl_u8(&vc4->rcl, VC4_PACKET_BRANCH_TO_SUB_LIST);
                         cl_reloc(vc4, &vc4->rcl, vc4->tile_alloc,
                                  (y * xtiles + x) * 32);
@@ -222,15 +234,17 @@ vc4_draw_vbo(struct pipe_context *pctx, const struct pipe_draw_info *info)
 
         // Do a store of the first tile to force the tile buffer to be cleared
         /* XXX: I think these two packets may be unnecessary. */
-        cl_u8(&vc4->rcl, VC4_PACKET_TILE_COORDINATES);
-        cl_u8(&vc4->rcl, 0);
-        cl_u8(&vc4->rcl, 0);
-
-        cl_u8(&vc4->rcl, VC4_PACKET_STORE_TILE_BUFFER_GENERAL);
-        cl_u16(&vc4->rcl, 0); // Store nothing (just clear)
-        cl_u32(&vc4->rcl, 0); // no address is needed
+        if (0) {
+                cl_u8(&vc4->rcl, VC4_PACKET_TILE_COORDINATES);
+                cl_u8(&vc4->rcl, 0);
+                cl_u8(&vc4->rcl, 0);
+
+                cl_u8(&vc4->rcl, VC4_PACKET_STORE_TILE_BUFFER_GENERAL);
+                cl_u16(&vc4->rcl, 0); // Store nothing (just clear)
+                cl_u32(&vc4->rcl, 0); // no address is needed
+        }
 
-        vc4_rcl_tile_calls(vc4, tilew, tileh);
+        vc4_rcl_tile_calls(vc4, csurf, tilew, tileh);
 
         vc4_flush(pctx);
 }
diff --git a/src/gallium/drivers/vc4/vc4_packet.h b/src/gallium/drivers/vc4/vc4_packet.h
index e74411a6a21..cc378667778 100644
--- a/src/gallium/drivers/vc4/vc4_packet.h
+++ b/src/gallium/drivers/vc4/vc4_packet.h
@@ -76,42 +76,51 @@ enum vc4_packet {
 } __attribute__ ((__packed__));
 
 /** @{
- * byte 2 of VC4_PACKET_STORE_TILE_BUFFER_GENERAL (low bits of the
- * address)
+ *
+ * byte 2 of VC4_PACKET_STORE_TILE_BUFFER_GENERAL and
+ * VC4_PACKET_LOAD_TILE_BUFFER_GENERAL (low bits of the address)
  */
 
-#define VC4_STORE_TILE_BUFFER_DISABLE_FULL_VG_MASK_DUMP (1 << 2)
-#define VC4_STORE_TILE_BUFFER_DISABLE_FULL_ZS_DUMP      (1 << 1)
-#define VC4_STORE_TILE_BUFFER_DISABLE_FULL_COLOR_DUMP   (1 << 0)
+#define VC4_LOADSTORE_TILE_BUFFER_DISABLE_FULL_VG_MASK (1 << 2)
+#define VC4_LOADSTORE_TILE_BUFFER_DISABLE_FULL_ZS      (1 << 1)
+#define VC4_LOADSTORE_TILE_BUFFER_DISABLE_FULL_COLOR   (1 << 0)
 
 /** @} */
 
-/** @{ byte 1 of VC4_PACKET_STORE_TILE_BUFFER_GENERAL */
+/** @{
+ *
+ * byte 1 of VC4_PACKET_STORE_TILE_BUFFER_GENERAL and
+ * VC4_PACKET_LOAD_TILE_BUFFER_GENERAL
+ */
 #define VC4_STORE_TILE_BUFFER_DISABLE_VG_MASK_CLEAR (1 << 7)
 #define VC4_STORE_TILE_BUFFER_DISABLE_ZS_CLEAR     (1 << 6)
 #define VC4_STORE_TILE_BUFFER_DISABLE_COLOR_CLEAR  (1 << 5)
 #define VC4_STORE_TILE_BUFFER_DISABLE_SWAP         (1 << 4)
 
-#define VC4_STORE_TILE_BUFFER_RGBA8888             (0 << 0)
-#define VC4_STORE_TILE_BUFFER_BGR565_DITHER        (1 << 0)
-#define VC4_STORE_TILE_BUFFER_BGR565               (2 << 0)
+#define VC4_LOADSTORE_TILE_BUFFER_RGBA8888         (0 << 0)
+#define VC4_LOADSTORE_TILE_BUFFER_BGR565_DITHER    (1 << 0)
+#define VC4_LOADSTORE_TILE_BUFFER_BGR565           (2 << 0)
 /** @} */
 
-/** @{ byte 0 of VC4_PACKET_STORE_TILE_BUFFER_GENERAL */
+/** @{
+ *
+ * byte 0 of VC4_PACKET_STORE_TILE_BUFFER_GENERAL and
+ * VC4_PACKET_LOAD_TILE_BUFFER_GENERAL
+ */
 #define VC4_STORE_TILE_BUFFER_MODE_SAMPLE0         (0 << 6)
 #define VC4_STORE_TILE_BUFFER_MODE_DECIMATE_X4     (1 << 6)
 #define VC4_STORE_TILE_BUFFER_MODE_DECIMATE_X16    (2 << 6)
 
-#define VC4_STORE_TILE_BUFFER_FORMAT_RASTER        (0 << 4)
-#define VC4_STORE_TILE_BUFFER_FORMAT_T             (1 << 4)
-#define VC4_STORE_TILE_BUFFER_FORMAT_LT            (2 << 4)
+#define VC4_LOADSTORE_TILE_BUFFER_FORMAT_RASTER    (0 << 4)
+#define VC4_LOADSTORE_TILE_BUFFER_FORMAT_T         (1 << 4)
+#define VC4_LOADSTORE_TILE_BUFFER_FORMAT_LT        (2 << 4)
 
-#define VC4_STORE_TILE_BUFFER_NONE                 (0 << 0)
-#define VC4_STORE_TILE_BUFFER_COLOR                (1 << 0)
-#define VC4_STORE_TILE_BUFFER_ZS                   (2 << 0)
-#define VC4_STORE_TILE_BUFFER_Z                    (3 << 0)
-#define VC4_STORE_TILE_BUFFER_VG_MASK              (4 << 0)
-#define VC4_STORE_TILE_BUFFER_FULL                 (5 << 0)
+#define VC4_LOADSTORE_TILE_BUFFER_NONE             (0 << 0)
+#define VC4_LOADSTORE_TILE_BUFFER_COLOR            (1 << 0)
+#define VC4_LOADSTORE_TILE_BUFFER_ZS               (2 << 0)
+#define VC4_LOADSTORE_TILE_BUFFER_Z                (3 << 0)
+#define VC4_LOADSTORE_TILE_BUFFER_VG_MASK          (4 << 0)
+#define VC4_LOADSTORE_TILE_BUFFER_FULL             (5 << 0)
 /** @} */
 
 #define VC4_INDEX_BUFFER_U8                        (0 << 4)