diff options
| author | Chia-I Wu <[email protected]> | 2014-04-13 23:37:04 +0800 |
|---|---|---|
| committer | Chia-I Wu <[email protected]> | 2014-04-14 20:45:04 +0800 |
| commit | 6c6bd796adda4173ebaf494d6cd2a96d511f1ea3 (patch) | |
| tree | b6b98c120b5864cec8ef4a5192a2a504fc225bd7 /src/gallium/drivers | |
| parent | 01e3e82a56310932667c60bcca9cc9fdfd8b87c4 (diff) | |
ilo: scripted conversion to genhw headers
Hopefully my four hundred line sed script is correct.
Diffstat (limited to 'src/gallium/drivers')
25 files changed, 1626 insertions, 1626 deletions
diff --git a/src/gallium/drivers/ilo/ilo_3d_pipeline.c b/src/gallium/drivers/ilo/ilo_3d_pipeline.c index e5f82d0a580..1f18bbbedfe 100644 --- a/src/gallium/drivers/ilo/ilo_3d_pipeline.c +++ b/src/gallium/drivers/ilo/ilo_3d_pipeline.c @@ -236,7 +236,7 @@ ilo_3d_pipeline_emit_flush(struct ilo_3d_pipeline *p) } /** - * Emit PIPE_CONTROL with PIPE_CONTROL_WRITE_TIMESTAMP post-sync op. + * Emit PIPE_CONTROL with GEN6_PIPE_CONTROL_WRITE_TIMESTAMP post-sync op. */ void ilo_3d_pipeline_emit_write_timestamp(struct ilo_3d_pipeline *p, @@ -247,7 +247,7 @@ ilo_3d_pipeline_emit_write_timestamp(struct ilo_3d_pipeline *p, } /** - * Emit PIPE_CONTROL with PIPE_CONTROL_WRITE_DEPTH_COUNT post-sync op. + * Emit PIPE_CONTROL with GEN6_PIPE_CONTROL_WRITE_PS_DEPTH_COUNT post-sync op. */ void ilo_3d_pipeline_emit_write_depth_count(struct ilo_3d_pipeline *p, diff --git a/src/gallium/drivers/ilo/ilo_3d_pipeline_gen6.c b/src/gallium/drivers/ilo/ilo_3d_pipeline_gen6.c index 744666072eb..bba35bc758e 100644 --- a/src/gallium/drivers/ilo/ilo_3d_pipeline_gen6.c +++ b/src/gallium/drivers/ilo/ilo_3d_pipeline_gen6.c @@ -67,8 +67,8 @@ gen6_wa_pipe_control_post_sync(struct ilo_3d_pipeline *p, * The workaround below necessitates this workaround. */ gen6_emit_PIPE_CONTROL(p->dev, - PIPE_CONTROL_CS_STALL | - PIPE_CONTROL_STALL_AT_SCOREBOARD, + GEN6_PIPE_CONTROL_CS_STALL | + GEN6_PIPE_CONTROL_PIXEL_SCOREBOARD_STALL, NULL, 0, false, p->cp); /* the caller will emit the post-sync op */ @@ -86,7 +86,7 @@ gen6_wa_pipe_control_post_sync(struct ilo_3d_pipeline *p, * PIPE_CONTROL with any non-zero post-sync-op is required." */ gen6_emit_PIPE_CONTROL(p->dev, - PIPE_CONTROL_WRITE_IMMEDIATE, + GEN6_PIPE_CONTROL_WRITE_IMM, p->workaround_bo, 0, false, p->cp); } @@ -106,8 +106,8 @@ gen6_wa_pipe_control_wm_multisample_flush(struct ilo_3d_pipeline *p) * Depth Flush prior to this command." */ gen6_emit_PIPE_CONTROL(p->dev, - PIPE_CONTROL_DEPTH_CACHE_FLUSH | - PIPE_CONTROL_CS_STALL, + GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH | + GEN6_PIPE_CONTROL_CS_STALL, 0, 0, false, p->cp); } @@ -124,15 +124,15 @@ gen6_wa_pipe_control_wm_depth_flush(struct ilo_3d_pipeline *p) * commands. */ gen6_emit_PIPE_CONTROL(p->dev, - PIPE_CONTROL_DEPTH_STALL, + GEN6_PIPE_CONTROL_DEPTH_STALL, NULL, 0, false, p->cp); gen6_emit_PIPE_CONTROL(p->dev, - PIPE_CONTROL_DEPTH_CACHE_FLUSH, + GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH, NULL, 0, false, p->cp); gen6_emit_PIPE_CONTROL(p->dev, - PIPE_CONTROL_DEPTH_STALL, + GEN6_PIPE_CONTROL_DEPTH_STALL, NULL, 0, false, p->cp); } @@ -153,7 +153,7 @@ gen6_wa_pipe_control_wm_max_threads_stall(struct ilo_3d_pipeline *p) * value in this field (Maximum Number of Threads in 3DSTATE_WM)" */ gen6_emit_PIPE_CONTROL(p->dev, - PIPE_CONTROL_STALL_AT_SCOREBOARD, + GEN6_PIPE_CONTROL_PIXEL_SCOREBOARD_STALL, NULL, 0, false, p->cp); } @@ -171,9 +171,9 @@ gen6_wa_pipe_control_vs_const_flush(struct ilo_3d_pipeline *p) * buffered by VS FF, to the point that the FF dies. */ gen6_emit_PIPE_CONTROL(p->dev, - PIPE_CONTROL_DEPTH_STALL | - PIPE_CONTROL_INSTRUCTION_FLUSH | - PIPE_CONTROL_STATE_CACHE_INVALIDATE, + GEN6_PIPE_CONTROL_DEPTH_STALL | + GEN6_PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE | + GEN6_PIPE_CONTROL_STATE_CACHE_INVALIDATE, NULL, 0, false, p->cp); } @@ -1487,13 +1487,13 @@ ilo_3d_pipeline_emit_flush_gen6(struct ilo_3d_pipeline *p) gen6_wa_pipe_control_post_sync(p, false); gen6_emit_PIPE_CONTROL(p->dev, - PIPE_CONTROL_INSTRUCTION_FLUSH | - PIPE_CONTROL_WRITE_FLUSH | - PIPE_CONTROL_DEPTH_CACHE_FLUSH | - PIPE_CONTROL_VF_CACHE_INVALIDATE | - PIPE_CONTROL_TC_FLUSH | - PIPE_CONTROL_NO_WRITE | - PIPE_CONTROL_CS_STALL, + GEN6_PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE | + GEN6_PIPE_CONTROL_RENDER_CACHE_FLUSH | + GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH | + GEN6_PIPE_CONTROL_VF_CACHE_INVALIDATE | + GEN6_PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | + GEN6_PIPE_CONTROL_WRITE_NONE | + GEN6_PIPE_CONTROL_CS_STALL, 0, 0, false, p->cp); } @@ -1505,7 +1505,7 @@ ilo_3d_pipeline_emit_write_timestamp_gen6(struct ilo_3d_pipeline *p, gen6_wa_pipe_control_post_sync(p, true); gen6_emit_PIPE_CONTROL(p->dev, - PIPE_CONTROL_WRITE_TIMESTAMP, + GEN6_PIPE_CONTROL_WRITE_TIMESTAMP, bo, index * sizeof(uint64_t), true, p->cp); } @@ -1518,8 +1518,8 @@ ilo_3d_pipeline_emit_write_depth_count_gen6(struct ilo_3d_pipeline *p, gen6_wa_pipe_control_post_sync(p, false); gen6_emit_PIPE_CONTROL(p->dev, - PIPE_CONTROL_DEPTH_STALL | - PIPE_CONTROL_WRITE_DEPTH_COUNT, + GEN6_PIPE_CONTROL_DEPTH_STALL | + GEN6_PIPE_CONTROL_WRITE_PS_DEPTH_COUNT, bo, index * sizeof(uint64_t), true, p->cp); } @@ -1529,16 +1529,16 @@ ilo_3d_pipeline_emit_write_statistics_gen6(struct ilo_3d_pipeline *p, struct intel_bo *bo, int index) { uint32_t regs[] = { - IA_VERTICES_COUNT, - IA_PRIMITIVES_COUNT, - VS_INVOCATION_COUNT, - GS_INVOCATION_COUNT, - GS_PRIMITIVES_COUNT, - CL_INVOCATION_COUNT, - CL_PRIMITIVES_COUNT, - PS_INVOCATION_COUNT, - p->dev->gen >= ILO_GEN(7) ? HS_INVOCATION_COUNT : 0, - p->dev->gen >= ILO_GEN(7) ? DS_INVOCATION_COUNT : 0, + GEN6_REG_IA_VERTICES_COUNT, + GEN6_REG_IA_PRIMITIVES_COUNT, + GEN6_REG_VS_INVOCATION_COUNT, + GEN6_REG_GS_INVOCATION_COUNT, + GEN6_REG_GS_PRIMITIVES_COUNT, + GEN6_REG_CL_INVOCATION_COUNT, + GEN6_REG_CL_PRIMITIVES_COUNT, + GEN6_REG_PS_INVOCATION_COUNT, + p->dev->gen >= ILO_GEN(7) ? GEN6_REG_HS_INVOCATION_COUNT : 0, + p->dev->gen >= ILO_GEN(7) ? GEN6_REG_DS_INVOCATION_COUNT : 0, 0, }; int i; @@ -1589,13 +1589,13 @@ gen6_rectlist_wm(struct ilo_3d_pipeline *p, switch (blitter->op) { case ILO_BLITTER_RECTLIST_CLEAR_ZS: - hiz_op = GEN6_WM_DEPTH_CLEAR; + hiz_op = GEN6_WM_DW4_DEPTH_CLEAR; break; case ILO_BLITTER_RECTLIST_RESOLVE_Z: - hiz_op = GEN6_WM_DEPTH_RESOLVE; + hiz_op = GEN6_WM_DW4_DEPTH_RESOLVE; break; case ILO_BLITTER_RECTLIST_RESOLVE_HIZ: - hiz_op = GEN6_WM_HIERARCHICAL_DEPTH_RESOLVE; + hiz_op = GEN6_WM_DW4_HIZ_RESOLVE; break; default: hiz_op = 0; diff --git a/src/gallium/drivers/ilo/ilo_3d_pipeline_gen7.c b/src/gallium/drivers/ilo/ilo_3d_pipeline_gen7.c index 1c99655d026..e1be5e7ca47 100644 --- a/src/gallium/drivers/ilo/ilo_3d_pipeline_gen7.c +++ b/src/gallium/drivers/ilo/ilo_3d_pipeline_gen7.c @@ -44,7 +44,7 @@ gen7_wa_pipe_control_cs_stall(struct ilo_3d_pipeline *p, bool change_depth_state) { struct intel_bo *bo = NULL; - uint32_t dw1 = PIPE_CONTROL_CS_STALL; + uint32_t dw1 = GEN6_PIPE_CONTROL_CS_STALL; assert(p->dev->gen == ILO_GEN(7) || p->dev->gen == ILO_GEN(7.5)); @@ -81,10 +81,10 @@ gen7_wa_pipe_control_cs_stall(struct ilo_3d_pipeline *p, */ if (change_multisample_state) - dw1 |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; + dw1 |= GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH; if (change_depth_state) { - dw1 |= PIPE_CONTROL_WRITE_IMMEDIATE; + dw1 |= GEN6_PIPE_CONTROL_WRITE_IMM; bo = p->workaround_bo; } @@ -106,8 +106,8 @@ gen7_wa_pipe_control_vs_depth_stall(struct ilo_3d_pipeline *p) * needs to be sent before any combination of VS associated 3DSTATE." */ gen6_emit_PIPE_CONTROL(p->dev, - PIPE_CONTROL_DEPTH_STALL | - PIPE_CONTROL_WRITE_IMMEDIATE, + GEN6_PIPE_CONTROL_DEPTH_STALL | + GEN6_PIPE_CONTROL_WRITE_IMM, p->workaround_bo, 0, false, p->cp); } @@ -145,18 +145,18 @@ gen7_wa_pipe_control_wm_depth_stall(struct ilo_3d_pipeline *p, * (e.g., via a preceding MI_FLUSH)." */ gen6_emit_PIPE_CONTROL(p->dev, - PIPE_CONTROL_DEPTH_STALL, + GEN6_PIPE_CONTROL_DEPTH_STALL, NULL, 0, false, p->cp); if (!change_depth_buffer) return; gen6_emit_PIPE_CONTROL(p->dev, - PIPE_CONTROL_DEPTH_CACHE_FLUSH, + GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH, NULL, 0, false, p->cp); gen6_emit_PIPE_CONTROL(p->dev, - PIPE_CONTROL_DEPTH_STALL, + GEN6_PIPE_CONTROL_DEPTH_STALL, NULL, 0, false, p->cp); } @@ -173,7 +173,7 @@ gen7_wa_pipe_control_ps_max_threads_stall(struct ilo_3d_pipeline *p) * Pixel Scoreboard set is required to be issued." */ gen6_emit_PIPE_CONTROL(p->dev, - PIPE_CONTROL_STALL_AT_SCOREBOARD, + GEN6_PIPE_CONTROL_PIXEL_SCOREBOARD_STALL, NULL, 0, false, p->cp); } @@ -726,13 +726,13 @@ gen7_rectlist_wm(struct ilo_3d_pipeline *p, switch (blitter->op) { case ILO_BLITTER_RECTLIST_CLEAR_ZS: - hiz_op = GEN7_WM_DEPTH_CLEAR; + hiz_op = GEN7_WM_DW1_DEPTH_CLEAR; break; case ILO_BLITTER_RECTLIST_RESOLVE_Z: - hiz_op = GEN7_WM_DEPTH_RESOLVE; + hiz_op = GEN7_WM_DW1_DEPTH_RESOLVE; break; case ILO_BLITTER_RECTLIST_RESOLVE_HIZ: - hiz_op = GEN7_WM_HIERARCHICAL_DEPTH_RESOLVE; + hiz_op = GEN7_WM_DW1_HIZ_RESOLVE; break; default: hiz_op = 0; diff --git a/src/gallium/drivers/ilo/ilo_blitter_blt.c b/src/gallium/drivers/ilo/ilo_blitter_blt.c index 57eaa902439..7cc017d2453 100644 --- a/src/gallium/drivers/ilo/ilo_blitter_blt.c +++ b/src/gallium/drivers/ilo/ilo_blitter_blt.c @@ -95,9 +95,9 @@ static uint32_t gen6_translate_blt_value_mask(enum gen6_blt_mask value_mask) { switch (value_mask) { - case GEN6_BLT_MASK_8: return BR13_8; - case GEN6_BLT_MASK_16: return BR13_565; - default: return BR13_8888; + case GEN6_BLT_MASK_8: return GEN6_BLITTER_BR13_FORMAT_8; + case GEN6_BLT_MASK_16: return GEN6_BLITTER_BR13_FORMAT_565; + default: return GEN6_BLITTER_BR13_FORMAT_8888; } } @@ -105,10 +105,10 @@ static uint32_t gen6_translate_blt_write_mask(enum gen6_blt_mask write_mask) { switch (write_mask) { - case GEN6_BLT_MASK_32: return XY_BLT_WRITE_RGB | - XY_BLT_WRITE_ALPHA; - case GEN6_BLT_MASK_32_LO: return XY_BLT_WRITE_RGB; - case GEN6_BLT_MASK_32_HI: return XY_BLT_WRITE_ALPHA; + case GEN6_BLT_MASK_32: return GEN6_BLITTER_BR00_WRITE_RGB | + GEN6_BLITTER_BR00_WRITE_A; + case GEN6_BLT_MASK_32_LO: return GEN6_BLITTER_BR00_WRITE_RGB; + case GEN6_BLT_MASK_32_HI: return GEN6_BLITTER_BR00_WRITE_A; default: return 0; } } @@ -185,7 +185,7 @@ gen6_emit_XY_COLOR_BLT(struct ilo_dev_info *dev, dst_pitch_shift = 0; } else { - dw0 |= XY_DST_TILED; + dw0 |= GEN6_BLITTER_BR00_DST_TILED; dst_align = (dst_tiling == INTEL_TILING_Y) ? 128 : 512; /* in dwords when tiled */ @@ -284,7 +284,7 @@ gen6_emit_XY_SRC_COPY_BLT(struct ilo_dev_info *dev, dst_pitch_shift = 0; } else { - dw0 |= XY_DST_TILED; + dw0 |= GEN6_BLITTER_BR00_DST_TILED; dst_align = (dst_tiling == INTEL_TILING_Y) ? 128 : 512; /* in dwords when tiled */ @@ -296,7 +296,7 @@ gen6_emit_XY_SRC_COPY_BLT(struct ilo_dev_info *dev, src_pitch_shift = 0; } else { - dw0 |= XY_SRC_TILED; + dw0 |= GEN6_BLITTER_BR00_SRC_TILED; src_align = (src_tiling == INTEL_TILING_Y) ? 128 : 512; /* in dwords when tiled */ @@ -352,23 +352,23 @@ ilo_blitter_blt_begin(struct ilo_blitter *blitter, int max_cmd_size, if (!intel_winsys_can_submit_bo(ilo->winsys, aper_check, count)) ilo_cp_flush(ilo->cp, "out of aperture"); - /* set BCS_SWCTRL */ + /* set GEN6_REG_BCS_SWCTRL */ swctrl = 0x0; if (dst_tiling == INTEL_TILING_Y) { - swctrl |= BCS_SWCTRL_DST_Y << 16 | - BCS_SWCTRL_DST_Y; + swctrl |= GEN6_REG_BCS_SWCTRL_DST_TILING_Y << 16 | + GEN6_REG_BCS_SWCTRL_DST_TILING_Y; } if (src && src_tiling == INTEL_TILING_Y) { - swctrl |= BCS_SWCTRL_SRC_Y << 16 | - BCS_SWCTRL_SRC_Y; + swctrl |= GEN6_REG_BCS_SWCTRL_SRC_TILING_Y << 16 | + GEN6_REG_BCS_SWCTRL_SRC_TILING_Y; } if (swctrl) { /* * Most clients expect BLT engine to be stateless. If we have to set - * BCS_SWCTRL to a non-default value, we have to set it back in the same + * GEN6_REG_BCS_SWCTRL to a non-default value, we have to set it back in the same * batch buffer. */ if (ilo_cp_space(ilo->cp) < (4 + 3) * 2 + max_cmd_size) @@ -383,9 +383,9 @@ ilo_blitter_blt_begin(struct ilo_blitter *blitter, int max_cmd_size, * this bit (Tile Y Destination/Source)." */ gen6_emit_MI_FLUSH_DW(ilo->dev, ilo->cp); - gen6_emit_MI_LOAD_REGISTER_IMM(ilo->dev, BCS_SWCTRL, swctrl, ilo->cp); + gen6_emit_MI_LOAD_REGISTER_IMM(ilo->dev, GEN6_REG_BCS_SWCTRL, swctrl, ilo->cp); - swctrl &= ~(BCS_SWCTRL_DST_Y | BCS_SWCTRL_SRC_Y); + swctrl &= ~(GEN6_REG_BCS_SWCTRL_DST_TILING_Y | GEN6_REG_BCS_SWCTRL_SRC_TILING_Y); } return swctrl; @@ -396,10 +396,10 @@ ilo_blitter_blt_end(struct ilo_blitter *blitter, uint32_t swctrl) { struct ilo_context *ilo = blitter->ilo; - /* set BCS_SWCTRL back */ + /* set GEN6_REG_BCS_SWCTRL back */ if (swctrl) { gen6_emit_MI_FLUSH_DW(ilo->dev, ilo->cp); - gen6_emit_MI_LOAD_REGISTER_IMM(ilo->dev, BCS_SWCTRL, swctrl, ilo->cp); + gen6_emit_MI_LOAD_REGISTER_IMM(ilo->dev, GEN6_REG_BCS_SWCTRL, swctrl, ilo->cp); ilo_cp_assert_no_implicit_flush(ilo->cp, false); } diff --git a/src/gallium/drivers/ilo/ilo_blitter_rectlist.c b/src/gallium/drivers/ilo/ilo_blitter_rectlist.c index 3df985ee85a..4efdeb80e4f 100644 --- a/src/gallium/drivers/ilo/ilo_blitter_rectlist.c +++ b/src/gallium/drivers/ilo/ilo_blitter_rectlist.c @@ -74,10 +74,10 @@ ilo_blitter_set_invariants(struct ilo_blitter *blitter) /* override first VE to be VUE header */ ve_init_cso_with_components(blitter->ilo->dev, - BRW_VE1_COMPONENT_STORE_0, /* Reserved */ - BRW_VE1_COMPONENT_STORE_0, /* Render Target Array Index */ - BRW_VE1_COMPONENT_STORE_0, /* Viewport Index */ - BRW_VE1_COMPONENT_STORE_0, /* Point Width */ + GEN6_VFCOMP_STORE_0, /* Reserved */ + GEN6_VFCOMP_STORE_0, /* Render Target Array Index */ + GEN6_VFCOMP_STORE_0, /* Viewport Index */ + GEN6_VFCOMP_STORE_0, /* Point Width */ &blitter->ve.cso[0]); /* a rectangle has 3 vertices in a RECTLIST */ diff --git a/src/gallium/drivers/ilo/ilo_format.c b/src/gallium/drivers/ilo/ilo_format.c index a69f94d91a1..ed285de29c4 100644 --- a/src/gallium/drivers/ilo/ilo_format.c +++ b/src/gallium/drivers/ilo/ilo_format.c @@ -89,225 +89,225 @@ struct surface_format_info { */ const struct surface_format_info surface_formats[] = { /* smpl filt shad CK RT AB VB SO color */ - SF( Y, 50, x, x, Y, Y, Y, Y, x, BRW_SURFACEFORMAT_R32G32B32A32_FLOAT) - SF( Y, x, x, x, Y, x, Y, Y, x, BRW_SURFACEFORMAT_R32G32B32A32_SINT) - SF( Y, x, x, x, Y, x, Y, Y, x, BRW_SURFACEFORMAT_R32G32B32A32_UINT) - SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32B32A32_UNORM) - SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32B32A32_SNORM) - SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R64G64_FLOAT) - SF( Y, 50, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R32G32B32X32_FLOAT) - SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32B32A32_SSCALED) - SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32B32A32_USCALED) - SF( x, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R32G32B32A32_SFIXED) - SF( x, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R64G64_PASSTHRU) - SF( Y, 50, x, x, x, x, Y, Y, x, BRW_SURFACEFORMAT_R32G32B32_FLOAT) - SF( Y, x, x, x, x, x, Y, Y, x, BRW_SURFACEFORMAT_R32G32B32_SINT) - SF( Y, x, x, x, x, x, Y, Y, x, BRW_SURFACEFORMAT_R32G32B32_UINT) - SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32B32_UNORM) - SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32B32_SNORM) - SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32B32_SSCALED) - SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32B32_USCALED) - SF( x, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R32G32B32_SFIXED) - SF( Y, Y, x, x, Y, 45, Y, x, 60, BRW_SURFACEFORMAT_R16G16B16A16_UNORM) - SF( Y, Y, x, x, Y, 60, Y, x, x, BRW_SURFACEFORMAT_R16G16B16A16_SNORM) - SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R16G16B16A16_SINT) - SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R16G16B16A16_UINT) - SF( Y, Y, x, x, Y, Y, Y, x, x, BRW_SURFACEFORMAT_R16G16B16A16_FLOAT) - SF( Y, 50, x, x, Y, Y, Y, Y, x, BRW_SURFACEFORMAT_R32G32_FLOAT) - SF( Y, x, x, x, Y, x, Y, Y, x, BRW_SURFACEFORMAT_R32G32_SINT) - SF( Y, x, x, x, Y, x, Y, Y, x, BRW_SURFACEFORMAT_R32G32_UINT) - SF( Y, 50, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_R32_FLOAT_X8X24_TYPELESS) - SF( Y, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_X32_TYPELESS_G8X24_UINT) - SF( Y, 50, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_L32A32_FLOAT) - SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32_UNORM) - SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32_SNORM) - SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R64_FLOAT) - SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R16G16B16X16_UNORM) - SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R16G16B16X16_FLOAT) - SF( Y, 50, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_A32X32_FLOAT) - SF( Y, 50, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_L32X32_FLOAT) - SF( Y, 50, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_I32X32_FLOAT) - SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16G16B16A16_SSCALED) - SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16G16B16A16_USCALED) - SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32_SSCALED) - SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32G32_USCALED) - SF( x, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R32G32_SFIXED) - SF( x, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R64_PASSTHRU) - SF( Y, Y, x, Y, Y, Y, Y, x, 60, BRW_SURFACEFORMAT_B8G8R8A8_UNORM) - SF( Y, Y, x, x, Y, Y, x, x, x, BRW_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB) + SF( Y, 50, x, x, Y, Y, Y, Y, x, GEN6_FORMAT_R32G32B32A32_FLOAT) + SF( Y, x, x, x, Y, x, Y, Y, x, GEN6_FORMAT_R32G32B32A32_SINT) + SF( Y, x, x, x, Y, x, Y, Y, x, GEN6_FORMAT_R32G32B32A32_UINT) + SF( x, x, x, x, x, x, Y, x, x, GEN6_FORMAT_R32G32B32A32_UNORM) + SF( x, x, x, x, x, x, Y, x, x, GEN6_FORMAT_R32G32B32A32_SNORM) + SF( x, x, x, x, x, x, Y, x, x, GEN6_FORMAT_R64G64_FLOAT) + SF( Y, 50, x, x, x, x, x, x, x, GEN6_FORMAT_R32G32B32X32_FLOAT) + SF( x, x, x, x, x, x, Y, x, x, GEN6_FORMAT_R32G32B32A32_SSCALED) + SF( x, x, x, x, x, x, Y, x, x, GEN6_FORMAT_R32G32B32A32_USCALED) + SF( x, x, x, x, x, x, x, x, x, GEN6_FORMAT_R32G32B32A32_SFIXED) + SF( x, x, x, x, x, x, x, x, x, GEN6_FORMAT_R64G64_PASSTHRU) + SF( Y, 50, x, x, x, x, Y, Y, x, GEN6_FORMAT_R32G32B32_FLOAT) + SF( Y, x, x, x, x, x, Y, Y, x, GEN6_FORMAT_R32G32B32_SINT) + SF( Y, x, x, x, x, x, Y, Y, x, GEN6_FORMAT_R32G32B32_UINT) + SF( x, x, x, x, x, x, Y, x, x, GEN6_FORMAT_R32G32B32_UNORM) + SF( x, x, x, x, x, x, Y, x, x, GEN6_FORMAT_R32G32B32_SNORM) + SF( x, x, x, x, x, x, Y, x, x, GEN6_FORMAT_R32G32B32_SSCALED) + SF( x, x, x, x, x, x, Y, x, x, GEN6_FORMAT_R32G32B32_USCALED) + SF( x, x, x, x, x, x, x, x, x, GEN6_FORMAT_R32G32B32_SFIXED) + SF( Y, Y, x, x, Y, 45, Y, x, 60, GEN6_FORMAT_R16G16B16A16_UNORM) + SF( Y, Y, x, x, Y, 60, Y, x, x, GEN6_FORMAT_R16G16B16A16_SNORM) + SF( Y, x, x, x, Y, x, Y, x, x, GEN6_FORMAT_R16G16B16A16_SINT) + SF( Y, x, x, x, Y, x, Y, x, x, GEN6_FORMAT_R16G16B16A16_UINT) + SF( Y, Y, x, x, Y, Y, Y, x, x, GEN6_FORMAT_R16G16B16A16_FLOAT) + SF( Y, 50, x, x, Y, Y, Y, Y, x, GEN6_FORMAT_R32G32_FLOAT) + SF( Y, x, x, x, Y, x, Y, Y, x, GEN6_FORMAT_R32G32_SINT) + SF( Y, x, x, x, Y, x, Y, Y, x, GEN6_FORMAT_R32G32_UINT) + SF( Y, 50, Y, x, x, x, x, x, x, GEN6_FORMAT_R32_FLOAT_X8X24_TYPELESS) + SF( Y, x, x, x, x, x, x, x, x, GEN6_FORMAT_X32_TYPELESS_G8X24_UINT) + SF( Y, 50, x, x, x, x, x, x, x, GEN6_FORMAT_L32A32_FLOAT) + SF( x, x, x, x, x, x, Y, x, x, GEN6_FORMAT_R32G32_UNORM) + SF( x, x, x, x, x, x, Y, x, x, GEN6_FORMAT_R32G32_SNORM) + SF( x, x, x, x, x, x, Y, x, x, GEN6_FORMAT_R64_FLOAT) + SF( Y, Y, x, x, x, x, x, x, x, GEN6_FORMAT_R16G16B16X16_UNORM) + SF( Y, Y, x, x, x, x, x, x, x, GEN6_FORMAT_R16G16B16X16_FLOAT) + SF( Y, 50, x, x, x, x, x, x, x, GEN6_FORMAT_A32X32_FLOAT) + SF( Y, 50, x, x, x, x, x, x, x, GEN6_FORMAT_L32X32_FLOAT) + SF( Y, 50, x, x, x, x, x, x, x, GEN6_FORMAT_I32X32_FLOAT) + SF( x, x, x, x, x, x, Y, x, x, GEN6_FORMAT_R16G16B16A16_SSCALED) + SF( x, x, x, x, x, x, Y, x, x, GEN6_FORMAT_R16G16B16A16_USCALED) + SF( x, x, x, x, x, x, Y, x, x, GEN6_FORMAT_R32G32_SSCALED) + SF( x, x, x, x, x, x, Y, x, x, GEN6_FORMAT_R32G32_USCALED) + SF( x, x, x, x, x, x, x, x, x, GEN6_FORMAT_R32G32_SFIXED) + SF( x, x, x, x, x, x, x, x, x, GEN6_FORMAT_R64_PASSTHRU) + SF( Y, Y, x, Y, Y, Y, Y, x, 60, GEN6_FORMAT_B8G8R8A8_UNORM) + SF( Y, Y, x, x, Y, Y, x, x, x, GEN6_FORMAT_B8G8R8A8_UNORM_SRGB) /* smpl filt shad CK RT AB VB SO color */ - SF( Y, Y, x, x, Y, Y, Y, x, 60, BRW_SURFACEFORMAT_R10G10B10A2_UNORM) - SF( Y, Y, x, x, x, x, x, x, 60, BRW_SURFACEFORMAT_R10G10B10A2_UNORM_SRGB) - SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R10G10B10A2_UINT) - SF( Y, Y, x, x, x, Y, Y, x, x, BRW_SURFACEFORMAT_R10G10B10_SNORM_A2_UNORM) - SF( Y, Y, x, x, Y, Y, Y, x, 60, BRW_SURFACEFORMAT_R8G8B8A8_UNORM) - SF( Y, Y, x, x, Y, Y, x, x, 60, BRW_SURFACEFORMAT_R8G8B8A8_UNORM_SRGB) - SF( Y, Y, x, x, Y, 60, Y, x, x, BRW_SURFACEFORMAT_R8G8B8A8_SNORM) - SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R8G8B8A8_SINT) - SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R8G8B8A8_UINT) - SF( Y, Y, x, x, Y, 45, Y, x, x, BRW_SURFACEFORMAT_R16G16_UNORM) - SF( Y, Y, x, x, Y, 60, Y, x, x, BRW_SURFACEFORMAT_R16G16_SNORM) - SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R16G16_SINT) - SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R16G16_UINT) - SF( Y, Y, x, x, Y, Y, Y, x, x, BRW_SURFACEFORMAT_R16G16_FLOAT) - SF( Y, Y, x, x, Y, Y, x, x, 60, BRW_SURFACEFORMAT_B10G10R10A2_UNORM) - SF( Y, Y, x, x, Y, Y, x, x, 60, BRW_SURFACEFORMAT_B10G10R10A2_UNORM_SRGB) - SF( Y, Y, x, x, Y, Y, Y, x, x, BRW_SURFACEFORMAT_R11G11B10_FLOAT) - SF( Y, x, x, x, Y, x, Y, Y, x, BRW_SURFACEFORMAT_R32_SINT) - SF( Y, x, x, x, Y, x, Y, Y, x, BRW_SURFACEFORMAT_R32_UINT) - SF( Y, 50, Y, x, Y, Y, Y, Y, x, BRW_SURFACEFORMAT_R32_FLOAT) - SF( Y, 50, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_R24_UNORM_X8_TYPELESS) - SF( Y, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_X24_TYPELESS_G8_UINT) - SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_L16A16_UNORM) - SF( Y, 50, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_I24X8_UNORM) - SF( Y, 50, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_L24X8_UNORM) - SF( Y, 50, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_A24X8_UNORM) - SF( Y, 50, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_I32_FLOAT) - SF( Y, 50, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_L32_FLOAT) - SF( Y, 50, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_A32_FLOAT) - SF( Y, Y, x, Y, x, x, x, x, 60, BRW_SURFACEFORMAT_B8G8R8X8_UNORM) - SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_B8G8R8X8_UNORM_SRGB) - SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R8G8B8X8_UNORM) - SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R8G8B8X8_UNORM_SRGB) - SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R9G9B9E5_SHAREDEXP) - SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_B10G10R10X2_UNORM) - SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_L16A16_FLOAT) - SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32_UNORM) - SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32_SNORM) + SF( Y, Y, x, x, Y, Y, Y, x, 60, GEN6_FORMAT_R10G10B10A2_UNORM) + SF( Y, Y, x, x, x, x, x, x, 60, GEN6_FORMAT_R10G10B10A2_UNORM_SRGB) + SF( Y, x, x, x, Y, x, Y, x, x, GEN6_FORMAT_R10G10B10A2_UINT) + SF( Y, Y, x, x, x, Y, Y, x, x, GEN6_FORMAT_R10G10B10_SNORM_A2_UNORM) + SF( Y, Y, x, x, Y, Y, Y, x, 60, GEN6_FORMAT_R8G8B8A8_UNORM) + SF( Y, Y, x, x, Y, Y, x, x, 60, GEN6_FORMAT_R8G8B8A8_UNORM_SRGB) + SF( Y, Y, x, x, Y, 60, Y, x, x, GEN6_FORMAT_R8G8B8A8_SNORM) + SF( Y, x, x, x, Y, x, Y, x, x, GEN6_FORMAT_R8G8B8A8_SINT) + SF( Y, x, x, x, Y, x, Y, x, x, GEN6_FORMAT_R8G8B8A8_UINT) + SF( Y, Y, x, x, Y, 45, Y, x, x, GEN6_FORMAT_R16G16_UNORM) + SF( Y, Y, x, x, Y, 60, Y, x, x, GEN6_FORMAT_R16G16_SNORM) + SF( Y, x, x, x, Y, x, Y, x, x, GEN6_FORMAT_R16G16_SINT) + SF( Y, x, x, x, Y, x, Y, x, x, GEN6_FORMAT_R16G16_UINT) + SF( Y, Y, x, x, Y, Y, Y, x, x, GEN6_FORMAT_R16G16_FLOAT) + SF( Y, Y, x, x, Y, Y, x, x, 60, GEN6_FORMAT_B10G10R10A2_UNORM) + SF( Y, Y, x, x, Y, Y, x, x, 60, GEN6_FORMAT_B10G10R10A2_UNORM_SRGB) + SF( Y, Y, x, x, Y, Y, Y, x, x, GEN6_FORMAT_R11G11B10_FLOAT) + SF( Y, x, x, x, Y, x, Y, Y, x, GEN6_FORMAT_R32_SINT) + SF( Y, x, x, x, Y, x, Y, Y, x, GEN6_FORMAT_R32_UINT) + SF( Y, 50, Y, x, Y, Y, Y, Y, x, GEN6_FORMAT_R32_FLOAT) + SF( Y, 50, Y, x, x, x, x, x, x, GEN6_FORMAT_R24_UNORM_X8_TYPELESS) + SF( Y, x, x, x, x, x, x, x, x, GEN6_FORMAT_X24_TYPELESS_G8_UINT) + SF( Y, Y, x, x, x, x, x, x, x, GEN6_FORMAT_L16A16_UNORM) + SF( Y, 50, Y, x, x, x, x, x, x, GEN6_FORMAT_I24X8_UNORM) + SF( Y, 50, Y, x, x, x, x, x, x, GEN6_FORMAT_L24X8_UNORM) + SF( Y, 50, Y, x, x, x, x, x, x, GEN6_FORMAT_A24X8_UNORM) + SF( Y, 50, Y, x, x, x, x, x, x, GEN6_FORMAT_I32_FLOAT) + SF( Y, 50, Y, x, x, x, x, x, x, GEN6_FORMAT_L32_FLOAT) + SF( Y, 50, Y, x, x, x, x, x, x, GEN6_FORMAT_A32_FLOAT) + SF( Y, Y, x, Y, x, x, x, x, 60, GEN6_FORMAT_B8G8R8X8_UNORM) + SF( Y, Y, x, x, x, x, x, x, x, GEN6_FORMAT_B8G8R8X8_UNORM_SRGB) + SF( Y, Y, x, x, x, x, x, x, x, GEN6_FORMAT_R8G8B8X8_UNORM) + SF( Y, Y, x, x, x, x, x, x, x, GEN6_FORMAT_R8G8B8X8_UNORM_SRGB) + SF( Y, Y, x, x, x, x, x, x, x, GEN6_FORMAT_R9G9B9E5_SHAREDEXP) + SF( Y, Y, x, x, x, x, x, x, x, GEN6_FORMAT_B10G10R10X2_UNORM) + SF( Y, Y, x, x, x, x, x, x, x, GEN6_FORMAT_L16A16_FLOAT) + SF( x, x, x, x, x, x, Y, x, x, GEN6_FORMAT_R32_UNORM) + SF( x, x, x, x, x, x, Y, x, x, GEN6_FORMAT_R32_SNORM) /* smpl filt shad CK RT AB VB SO color */ - SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R10G10B10X2_USCALED) - SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8G8B8A8_SSCALED) - SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8G8B8A8_USCALED) - SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16G16_SSCALED) - SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16G16_USCALED) - SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32_SSCALED) - SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R32_USCALED) - SF( Y, Y, x, Y, Y, Y, x, x, x, BRW_SURFACEFORMAT_B5G6R5_UNORM) - SF( Y, Y, x, x, Y, Y, x, x, x, BRW_SURFACEFORMAT_B5G6R5_UNORM_SRGB) - SF( Y, Y, x, Y, Y, Y, x, x, x, BRW_SURFACEFORMAT_B5G5R5A1_UNORM) - SF( Y, Y, x, x, Y, Y, x, x, x, BRW_SURFACEFORMAT_B5G5R5A1_UNORM_SRGB) - SF( Y, Y, x, Y, Y, Y, x, x, x, BRW_SURFACEFORMAT_B4G4R4A4_UNORM) - SF( Y, Y, x, x, Y, Y, x, x, x, BRW_SURFACEFORMAT_B4G4R4A4_UNORM_SRGB) - SF( Y, Y, x, x, Y, Y, Y, x, x, BRW_SURFACEFORMAT_R8G8_UNORM) - SF( Y, Y, x, Y, Y, 60, Y, x, x, BRW_SURFACEFORMAT_R8G8_SNORM) - SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R8G8_SINT) - SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R8G8_UINT) - SF( Y, Y, Y, x, Y, 45, Y, x, 70, BRW_SURFACEFORMAT_R16_UNORM) - SF( Y, Y, x, x, Y, 60, Y, x, x, BRW_SURFACEFORMAT_R16_SNORM) - SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R16_SINT) - SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R16_UINT) - SF( Y, Y, x, x, Y, Y, Y, x, x, BRW_SURFACEFORMAT_R16_FLOAT) - SF(50, 50, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_A8P8_UNORM_PALETTE0) - SF(50, 50, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_A8P8_UNORM_PALETTE1) - SF( Y, Y, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_I16_UNORM) - SF( Y, Y, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_L16_UNORM) - SF( Y, Y, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_A16_UNORM) - SF( Y, Y, x, Y, x, x, x, x, x, BRW_SURFACEFORMAT_L8A8_UNORM) - SF( Y, Y, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_I16_FLOAT) - SF( Y, Y, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_L16_FLOAT) - SF( Y, Y, Y, x, x, x, x, x, x, BRW_SURFACEFORMAT_A16_FLOAT) - SF(45, 45, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_L8A8_UNORM_SRGB) - SF( Y, Y, x, Y, x, x, x, x, x, BRW_SURFACEFORMAT_R5G5_SNORM_B6_UNORM) - SF( x, x, x, x, Y, Y, x, x, x, BRW_SURFACEFORMAT_B5G5R5X1_UNORM) - SF( x, x, x, x, Y, Y, x, x, x, BRW_SURFACEFORMAT_B5G5R5X1_UNORM_SRGB) - SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8G8_SSCALED) - SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8G8_USCALED) + SF( x, x, x, x, x, x, Y, x, x, GEN6_FORMAT_R10G10B10X2_USCALED) + SF( x, x, x, x, x, x, Y, x, x, GEN6_FORMAT_R8G8B8A8_SSCALED) + SF( x, x, x, x, x, x, Y, x, x, GEN6_FORMAT_R8G8B8A8_USCALED) + SF( x, x, x, x, x, x, Y, x, x, GEN6_FORMAT_R16G16_SSCALED) + SF( x, x, x, x, x, x, Y, x, x, GEN6_FORMAT_R16G16_USCALED) + SF( x, x, x, x, x, x, Y, x, x, GEN6_FORMAT_R32_SSCALED) + SF( x, x, x, x, x, x, Y, x, x, GEN6_FORMAT_R32_USCALED) + SF( Y, Y, x, Y, Y, Y, x, x, x, GEN6_FORMAT_B5G6R5_UNORM) + SF( Y, Y, x, x, Y, Y, x, x, x, GEN6_FORMAT_B5G6R5_UNORM_SRGB) + SF( Y, Y, x, Y, Y, Y, x, x, x, GEN6_FORMAT_B5G5R5A1_UNORM) + SF( Y, Y, x, x, Y, Y, x, x, x, GEN6_FORMAT_B5G5R5A1_UNORM_SRGB) + SF( Y, Y, x, Y, Y, Y, x, x, x, GEN6_FORMAT_B4G4R4A4_UNORM) + SF( Y, Y, x, x, Y, Y, x, x, x, GEN6_FORMAT_B4G4R4A4_UNORM_SRGB) + SF( Y, Y, x, x, Y, Y, Y, x, x, GEN6_FORMAT_R8G8_UNORM) + SF( Y, Y, x, Y, Y, 60, Y, x, x, GEN6_FORMAT_R8G8_SNORM) + SF( Y, x, x, x, Y, x, Y, x, x, GEN6_FORMAT_R8G8_SINT) + SF( Y, x, x, x, Y, x, Y, x, x, GEN6_FORMAT_R8G8_UINT) + SF( Y, Y, Y, x, Y, 45, Y, x, 70, GEN6_FORMAT_R16_UNORM) + SF( Y, Y, x, x, Y, 60, Y, x, x, GEN6_FORMAT_R16_SNORM) + SF( Y, x, x, x, Y, x, Y, x, x, GEN6_FORMAT_R16_SINT) + SF( Y, x, x, x, Y, x, Y, x, x, GEN6_FORMAT_R16_UINT) + SF( Y, Y, x, x, Y, Y, Y, x, x, GEN6_FORMAT_R16_FLOAT) + SF(50, 50, x, x, x, x, x, x, x, GEN6_FORMAT_A8P8_UNORM_PALETTE0) + SF(50, 50, x, x, x, x, x, x, x, GEN6_FORMAT_A8P8_UNORM_PALETTE1) + SF( Y, Y, Y, x, x, x, x, x, x, GEN6_FORMAT_I16_UNORM) + SF( Y, Y, Y, x, x, x, x, x, x, GEN6_FORMAT_L16_UNORM) + SF( Y, Y, Y, x, x, x, x, x, x, GEN6_FORMAT_A16_UNORM) + SF( Y, Y, x, Y, x, x, x, x, x, GEN6_FORMAT_L8A8_UNORM) + SF( Y, Y, Y, x, x, x, x, x, x, GEN6_FORMAT_I16_FLOAT) + SF( Y, Y, Y, x, x, x, x, x, x, GEN6_FORMAT_L16_FLOAT) + SF( Y, Y, Y, x, x, x, x, x, x, GEN6_FORMAT_A16_FLOAT) + SF(45, 45, x, x, x, x, x, x, x, GEN6_FORMAT_L8A8_UNORM_SRGB) + SF( Y, Y, x, Y, x, x, x, x, x, GEN6_FORMAT_R5G5_SNORM_B6_UNORM) + SF( x, x, x, x, Y, Y, x, x, x, GEN6_FORMAT_B5G5R5X1_UNORM) + SF( x, x, x, x, Y, Y, x, x, x, GEN6_FORMAT_B5G5R5X1_UNORM_SRGB) + SF( x, x, x, x, x, x, Y, x, x, GEN6_FORMAT_R8G8_SSCALED) + SF( x, x, x, x, x, x, Y, x, x, GEN6_FORMAT_R8G8_USCALED) /* smpl filt shad CK RT AB VB SO color */ - SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16_SSCALED) - SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16_USCALED) - SF(50, 50, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_P8A8_UNORM_PALETTE0) - SF(50, 50, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_P8A8_UNORM_PALETTE1) - SF( x, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_A1B5G5R5_UNORM) - SF( x, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_A4B4G4R4_UNORM) - SF( x, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_L8A8_UINT) - SF( x, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_L8A8_SINT) - SF( Y, Y, x, 45, Y, Y, Y, x, x, BRW_SURFACEFORMAT_R8_UNORM) - SF( Y, Y, x, x, Y, 60, Y, x, x, BRW_SURFACEFORMAT_R8_SNORM) - SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R8_SINT) - SF( Y, x, x, x, Y, x, Y, x, x, BRW_SURFACEFORMAT_R8_UINT) - SF( Y, Y, x, Y, Y, Y, x, x, x, BRW_SURFACEFORMAT_A8_UNORM) - SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_I8_UNORM) - SF( Y, Y, x, Y, x, x, x, x, x, BRW_SURFACEFORMAT_L8_UNORM) - SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_P4A4_UNORM) - SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_A4P4_UNORM) - SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8_SSCALED) - SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8_USCALED) - SF(45, 45, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_P8_UNORM_PALETTE0) - SF(45, 45, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_L8_UNORM_SRGB) - SF(45, 45, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_P8_UNORM_PALETTE1) - SF(45, 45, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_P4A4_UNORM_PALETTE1) - SF(45, 45, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_A4P4_UNORM_PALETTE1) - SF( x, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_Y8_SNORM) - SF( x, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_L8_UINT) - SF( x, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_L8_SINT) - SF( x, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_I8_UINT) - SF( x, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_I8_SINT) - SF(45, 45, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_DXT1_RGB_SRGB) - SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R1_UINT) - SF( Y, Y, x, Y, Y, x, x, x, 60, BRW_SURFACEFORMAT_YCRCB_NORMAL) - SF( Y, Y, x, Y, Y, x, x, x, 60, BRW_SURFACEFORMAT_YCRCB_SWAPUVY) - SF(45, 45, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_P2_UNORM_PALETTE0) - SF(45, 45, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_P2_UNORM_PALETTE1) - SF( Y, Y, x, Y, x, x, x, x, x, BRW_SURFACEFORMAT_BC1_UNORM) - SF( Y, Y, x, Y, x, x, x, x, x, BRW_SURFACEFORMAT_BC2_UNORM) - SF( Y, Y, x, Y, x, x, x, x, x, BRW_SURFACEFORMAT_BC3_UNORM) - SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_BC4_UNORM) - SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_BC5_UNORM) - SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_BC1_UNORM_SRGB) - SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_BC2_UNORM_SRGB) - SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_BC3_UNORM_SRGB) - SF( Y, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_MONO8) - SF( Y, Y, x, x, Y, x, x, x, 60, BRW_SURFACEFORMAT_YCRCB_SWAPUV) - SF( Y, Y, x, x, Y, x, x, x, 60, BRW_SURFACEFORMAT_YCRCB_SWAPY) - SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_DXT1_RGB) + SF( x, x, x, x, x, x, Y, x, x, GEN6_FORMAT_R16_SSCALED) + SF( x, x, x, x, x, x, Y, x, x, GEN6_FORMAT_R16_USCALED) + SF(50, 50, x, x, x, x, x, x, x, GEN6_FORMAT_P8A8_UNORM_PALETTE0) + SF(50, 50, x, x, x, x, x, x, x, GEN6_FORMAT_P8A8_UNORM_PALETTE1) + SF( x, x, x, x, x, x, x, x, x, GEN6_FORMAT_A1B5G5R5_UNORM) + SF( x, x, x, x, x, x, x, x, x, GEN6_FORMAT_A4B4G4R4_UNORM) + SF( x, x, x, x, x, x, x, x, x, GEN6_FORMAT_L8A8_UINT) + SF( x, x, x, x, x, x, x, x, x, GEN6_FORMAT_L8A8_SINT) + SF( Y, Y, x, 45, Y, Y, Y, x, x, GEN6_FORMAT_R8_UNORM) + SF( Y, Y, x, x, Y, 60, Y, x, x, GEN6_FORMAT_R8_SNORM) + SF( Y, x, x, x, Y, x, Y, x, x, GEN6_FORMAT_R8_SINT) + SF( Y, x, x, x, Y, x, Y, x, x, GEN6_FORMAT_R8_UINT) + SF( Y, Y, x, Y, Y, Y, x, x, x, GEN6_FORMAT_A8_UNORM) + SF( Y, Y, x, x, x, x, x, x, x, GEN6_FORMAT_I8_UNORM) + SF( Y, Y, x, Y, x, x, x, x, x, GEN6_FORMAT_L8_UNORM) + SF( Y, Y, x, x, x, x, x, x, x, GEN6_FORMAT_P4A4_UNORM_PALETTE0) + SF( Y, Y, x, x, x, x, x, x, x, GEN6_FORMAT_A4P4_UNORM_PALETTE0) + SF( x, x, x, x, x, x, Y, x, x, GEN6_FORMAT_R8_SSCALED) + SF( x, x, x, x, x, x, Y, x, x, GEN6_FORMAT_R8_USCALED) + SF(45, 45, x, x, x, x, x, x, x, GEN6_FORMAT_P8_UNORM_PALETTE0) + SF(45, 45, x, x, x, x, x, x, x, GEN6_FORMAT_L8_UNORM_SRGB) + SF(45, 45, x, x, x, x, x, x, x, GEN6_FORMAT_P8_UNORM_PALETTE1) + SF(45, 45, x, x, x, x, x, x, x, GEN6_FORMAT_P4A4_UNORM_PALETTE1) + SF(45, 45, x, x, x, x, x, x, x, GEN6_FORMAT_A4P4_UNORM_PALETTE1) + SF( x, x, x, x, x, x, x, x, x, GEN6_FORMAT_Y8_UNORM) + SF( x, x, x, x, x, x, x, x, x, GEN6_FORMAT_L8_UINT) + SF( x, x, x, x, x, x, x, x, x, GEN6_FORMAT_L8_SINT) + SF( x, x, x, x, x, x, x, x, x, GEN6_FORMAT_I8_UINT) + SF( x, x, x, x, x, x, x, x, x, GEN6_FORMAT_I8_SINT) + SF(45, 45, x, x, x, x, x, x, x, GEN6_FORMAT_DXT1_RGB_SRGB) + SF( Y, Y, x, x, x, x, x, x, x, GEN6_FORMAT_R1_UNORM) + SF( Y, Y, x, Y, Y, x, x, x, 60, GEN6_FORMAT_YCRCB_NORMAL) + SF( Y, Y, x, Y, Y, x, x, x, 60, GEN6_FORMAT_YCRCB_SWAPUVY) + SF(45, 45, x, x, x, x, x, x, x, GEN6_FORMAT_P2_UNORM_PALETTE0) + SF(45, 45, x, x, x, x, x, x, x, GEN6_FORMAT_P2_UNORM_PALETTE1) + SF( Y, Y, x, Y, x, x, x, x, x, GEN6_FORMAT_BC1_UNORM) + SF( Y, Y, x, Y, x, x, x, x, x, GEN6_FORMAT_BC2_UNORM) + SF( Y, Y, x, Y, x, x, x, x, x, GEN6_FORMAT_BC3_UNORM) + SF( Y, Y, x, x, x, x, x, x, x, GEN6_FORMAT_BC4_UNORM) + SF( Y, Y, x, x, x, x, x, x, x, GEN6_FORMAT_BC5_UNORM) + SF( Y, Y, x, x, x, x, x, x, x, GEN6_FORMAT_BC1_UNORM_SRGB) + SF( Y, Y, x, x, x, x, x, x, x, GEN6_FORMAT_BC2_UNORM_SRGB) + SF( Y, Y, x, x, x, x, x, x, x, GEN6_FORMAT_BC3_UNORM_SRGB) + SF( Y, x, x, x, x, x, x, x, x, GEN6_FORMAT_MONO8) + SF( Y, Y, x, x, Y, x, x, x, 60, GEN6_FORMAT_YCRCB_SWAPUV) + SF( Y, Y, x, x, Y, x, x, x, 60, GEN6_FORMAT_YCRCB_SWAPY) + SF( Y, Y, x, x, x, x, x, x, x, GEN6_FORMAT_DXT1_RGB) /* smpl filt shad CK RT AB VB SO color */ - SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_FXT1) - SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8G8B8_UNORM) - SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8G8B8_SNORM) - SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8G8B8_SSCALED) - SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R8G8B8_USCALED) - SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R64G64B64A64_FLOAT) - SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R64G64B64_FLOAT) - SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_BC4_SNORM) - SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_BC5_SNORM) - SF(50, 50, x, x, x, x, 60, x, x, BRW_SURFACEFORMAT_R16G16B16_FLOAT) - SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16G16B16_UNORM) - SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16G16B16_SNORM) - SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16G16B16_SSCALED) - SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16G16B16_USCALED) - SF(70, 70, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_BC6H_SF16) - SF(70, 70, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_BC7_UNORM) - SF(70, 70, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_BC7_UNORM_SRGB) - SF(70, 70, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_BC6H_UF16) - SF( x, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_PLANAR_420_8) - SF( x, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R8G8B8_UNORM_SRGB) - SF( x, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_ETC1_RGB8) - SF( x, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_ETC2_RGB8) - SF( x, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_EAC_R11) - SF( x, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_EAC_RG11) - SF( x, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_EAC_SIGNED_R11) - SF( x, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_EAC_SIGNED_RG11) - SF( x, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_ETC2_SRGB8) - SF( x, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R16G16B16_UINT) - SF( x, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R16G16B16_SINT) - SF( x, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R32_SFIXED) - SF( x, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R10G10B10A2_SNORM) - SF( x, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R10G10B10A2_USCALED) - SF( x, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R10G10B10A2_SSCALED) - SF( x, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R10G10B10A2_SINT) - SF( x, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_B10G10R10A2_SNORM) - SF( x, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_B10G10R10A2_USCALED) - SF( x, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_B10G10R10A2_SSCALED) - SF( x, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_B10G10R10A2_UINT) - SF( x, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_B10G10R10A2_SINT) - SF( x, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R64G64B64A64_PASSTHRU) - SF( x, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R64G64B64_PASSTHRU) - SF( x, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_ETC2_RGB8_PTA) - SF( x, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_ETC2_SRGB8_PTA) - SF( x, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_ETC2_EAC_RGBA8) - SF( x, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_ETC2_EAC_SRGB8_A8) - SF( x, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R8G8B8_UINT) - SF( x, x, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_R8G8B8_SINT) + SF( Y, Y, x, x, x, x, x, x, x, GEN6_FORMAT_FXT1) + SF( x, x, x, x, x, x, Y, x, x, GEN6_FORMAT_R8G8B8_UNORM) + SF( x, x, x, x, x, x, Y, x, x, GEN6_FORMAT_R8G8B8_SNORM) + SF( x, x, x, x, x, x, Y, x, x, GEN6_FORMAT_R8G8B8_SSCALED) + SF( x, x, x, x, x, x, Y, x, x, GEN6_FORMAT_R8G8B8_USCALED) + SF( x, x, x, x, x, x, Y, x, x, GEN6_FORMAT_R64G64B64A64_FLOAT) + SF( x, x, x, x, x, x, Y, x, x, GEN6_FORMAT_R64G64B64_FLOAT) + SF( Y, Y, x, x, x, x, x, x, x, GEN6_FORMAT_BC4_SNORM) + SF( Y, Y, x, x, x, x, x, x, x, GEN6_FORMAT_BC5_SNORM) + SF(50, 50, x, x, x, x, 60, x, x, GEN6_FORMAT_R16G16B16_FLOAT) + SF( x, x, x, x, x, x, Y, x, x, GEN6_FORMAT_R16G16B16_UNORM) + SF( x, x, x, x, x, x, Y, x, x, GEN6_FORMAT_R16G16B16_SNORM) + SF( x, x, x, x, x, x, Y, x, x, GEN6_FORMAT_R16G16B16_SSCALED) + SF( x, x, x, x, x, x, Y, x, x, GEN6_FORMAT_R16G16B16_USCALED) + SF(70, 70, x, x, x, x, x, x, x, GEN6_FORMAT_BC6H_SF16) + SF(70, 70, x, x, x, x, x, x, x, GEN6_FORMAT_BC7_UNORM) + SF(70, 70, x, x, x, x, x, x, x, GEN6_FORMAT_BC7_UNORM_SRGB) + SF(70, 70, x, x, x, x, x, x, x, GEN6_FORMAT_BC6H_UF16) + SF( x, x, x, x, x, x, x, x, x, GEN6_FORMAT_PLANAR_420_8) + SF( x, x, x, x, x, x, x, x, x, GEN6_FORMAT_R8G8B8_UNORM_SRGB) + SF( x, x, x, x, x, x, x, x, x, GEN6_FORMAT_ETC1_RGB8) + SF( x, x, x, x, x, x, x, x, x, GEN6_FORMAT_ETC2_RGB8) + SF( x, x, x, x, x, x, x, x, x, GEN6_FORMAT_EAC_R11) + SF( x, x, x, x, x, x, x, x, x, GEN6_FORMAT_EAC_RG11) + SF( x, x, x, x, x, x, x, x, x, GEN6_FORMAT_EAC_SIGNED_R11) + SF( x, x, x, x, x, x, x, x, x, GEN6_FORMAT_EAC_SIGNED_RG11) + SF( x, x, x, x, x, x, x, x, x, GEN6_FORMAT_ETC2_SRGB8) + SF( x, x, x, x, x, x, x, x, x, GEN6_FORMAT_R16G16B16_UINT) + SF( x, x, x, x, x, x, x, x, x, GEN6_FORMAT_R16G16B16_SINT) + SF( x, x, x, x, x, x, x, x, x, GEN6_FORMAT_R32_SFIXED) + SF( x, x, x, x, x, x, x, x, x, GEN6_FORMAT_R10G10B10A2_SNORM) + SF( x, x, x, x, x, x, x, x, x, GEN6_FORMAT_R10G10B10A2_USCALED) + SF( x, x, x, x, x, x, x, x, x, GEN6_FORMAT_R10G10B10A2_SSCALED) + SF( x, x, x, x, x, x, x, x, x, GEN6_FORMAT_R10G10B10A2_SINT) + SF( x, x, x, x, x, x, x, x, x, GEN6_FORMAT_B10G10R10A2_SNORM) + SF( x, x, x, x, x, x, x, x, x, GEN6_FORMAT_B10G10R10A2_USCALED) + SF( x, x, x, x, x, x, x, x, x, GEN6_FORMAT_B10G10R10A2_SSCALED) + SF( x, x, x, x, x, x, x, x, x, GEN6_FORMAT_B10G10R10A2_UINT) + SF( x, x, x, x, x, x, x, x, x, GEN6_FORMAT_B10G10R10A2_SINT) + SF( x, x, x, x, x, x, x, x, x, GEN6_FORMAT_R64G64B64A64_PASSTHRU) + SF( x, x, x, x, x, x, x, x, x, GEN6_FORMAT_R64G64B64_PASSTHRU) + SF( x, x, x, x, x, x, x, x, x, GEN6_FORMAT_ETC2_RGB8_PTA) + SF( x, x, x, x, x, x, x, x, x, GEN6_FORMAT_ETC2_SRGB8_PTA) + SF( x, x, x, x, x, x, x, x, x, GEN6_FORMAT_ETC2_EAC_RGBA8) + SF( x, x, x, x, x, x, x, x, x, GEN6_FORMAT_ETC2_EAC_SRGB8_A8) + SF( x, x, x, x, x, x, x, x, x, GEN6_FORMAT_R8G8B8_UINT) + SF( x, x, x, x, x, x, x, x, x, GEN6_FORMAT_R8G8B8_SINT) }; #undef x #undef Y @@ -343,21 +343,21 @@ ilo_translate_color_format(enum pipe_format format) { static const int format_mapping[PIPE_FORMAT_COUNT] = { [PIPE_FORMAT_NONE] = 0, - [PIPE_FORMAT_B8G8R8A8_UNORM] = BRW_SURFACEFORMAT_B8G8R8A8_UNORM, - [PIPE_FORMAT_B8G8R8X8_UNORM] = BRW_SURFACEFORMAT_B8G8R8X8_UNORM, + [PIPE_FORMAT_B8G8R8A8_UNORM] = GEN6_FORMAT_B8G8R8A8_UNORM, + [PIPE_FORMAT_B8G8R8X8_UNORM] = GEN6_FORMAT_B8G8R8X8_UNORM, [PIPE_FORMAT_A8R8G8B8_UNORM] = 0, [PIPE_FORMAT_X8R8G8B8_UNORM] = 0, - [PIPE_FORMAT_B5G5R5A1_UNORM] = BRW_SURFACEFORMAT_B5G5R5A1_UNORM, - [PIPE_FORMAT_B4G4R4A4_UNORM] = BRW_SURFACEFORMAT_B4G4R4A4_UNORM, - [PIPE_FORMAT_B5G6R5_UNORM] = BRW_SURFACEFORMAT_B5G6R5_UNORM, - [PIPE_FORMAT_R10G10B10A2_UNORM] = BRW_SURFACEFORMAT_R10G10B10A2_UNORM, - [PIPE_FORMAT_L8_UNORM] = BRW_SURFACEFORMAT_L8_UNORM, - [PIPE_FORMAT_A8_UNORM] = BRW_SURFACEFORMAT_A8_UNORM, - [PIPE_FORMAT_I8_UNORM] = BRW_SURFACEFORMAT_I8_UNORM, - [PIPE_FORMAT_L8A8_UNORM] = BRW_SURFACEFORMAT_L8A8_UNORM, - [PIPE_FORMAT_L16_UNORM] = BRW_SURFACEFORMAT_L16_UNORM, - [PIPE_FORMAT_UYVY] = BRW_SURFACEFORMAT_YCRCB_SWAPUVY, - [PIPE_FORMAT_YUYV] = BRW_SURFACEFORMAT_YCRCB_NORMAL, + [PIPE_FORMAT_B5G5R5A1_UNORM] = GEN6_FORMAT_B5G5R5A1_UNORM, + [PIPE_FORMAT_B4G4R4A4_UNORM] = GEN6_FORMAT_B4G4R4A4_UNORM, + [PIPE_FORMAT_B5G6R5_UNORM] = GEN6_FORMAT_B5G6R5_UNORM, + [PIPE_FORMAT_R10G10B10A2_UNORM] = GEN6_FORMAT_R10G10B10A2_UNORM, + [PIPE_FORMAT_L8_UNORM] = GEN6_FORMAT_L8_UNORM, + [PIPE_FORMAT_A8_UNORM] = GEN6_FORMAT_A8_UNORM, + [PIPE_FORMAT_I8_UNORM] = GEN6_FORMAT_I8_UNORM, + [PIPE_FORMAT_L8A8_UNORM] = GEN6_FORMAT_L8A8_UNORM, + [PIPE_FORMAT_L16_UNORM] = GEN6_FORMAT_L16_UNORM, + [PIPE_FORMAT_UYVY] = GEN6_FORMAT_YCRCB_SWAPUVY, + [PIPE_FORMAT_YUYV] = GEN6_FORMAT_YCRCB_NORMAL, [PIPE_FORMAT_Z16_UNORM] = 0, [PIPE_FORMAT_Z32_UNORM] = 0, [PIPE_FORMAT_Z32_FLOAT] = 0, @@ -366,119 +366,119 @@ ilo_translate_color_format(enum pipe_format format) [PIPE_FORMAT_Z24X8_UNORM] = 0, [PIPE_FORMAT_X8Z24_UNORM] = 0, [PIPE_FORMAT_S8_UINT] = 0, - [PIPE_FORMAT_R64_FLOAT] = BRW_SURFACEFORMAT_R64_FLOAT, - [PIPE_FORMAT_R64G64_FLOAT] = BRW_SURFACEFORMAT_R64G64_FLOAT, - [PIPE_FORMAT_R64G64B64_FLOAT] = BRW_SURFACEFORMAT_R64G64B64_FLOAT, - [PIPE_FORMAT_R64G64B64A64_FLOAT] = BRW_SURFACEFORMAT_R64G64B64A64_FLOAT, - [PIPE_FORMAT_R32_FLOAT] = BRW_SURFACEFORMAT_R32_FLOAT, - [PIPE_FORMAT_R32G32_FLOAT] = BRW_SURFACEFORMAT_R32G32_FLOAT, - [PIPE_FORMAT_R32G32B32_FLOAT] = BRW_SURFACEFORMAT_R32G32B32_FLOAT, - [PIPE_FORMAT_R32G32B32A32_FLOAT] = BRW_SURFACEFORMAT_R32G32B32A32_FLOAT, - [PIPE_FORMAT_R32_UNORM] = BRW_SURFACEFORMAT_R32_UNORM, - [PIPE_FORMAT_R32G32_UNORM] = BRW_SURFACEFORMAT_R32G32_UNORM, - [PIPE_FORMAT_R32G32B32_UNORM] = BRW_SURFACEFORMAT_R32G32B32_UNORM, - [PIPE_FORMAT_R32G32B32A32_UNORM] = BRW_SURFACEFORMAT_R32G32B32A32_UNORM, - [PIPE_FORMAT_R32_USCALED] = BRW_SURFACEFORMAT_R32_USCALED, - [PIPE_FORMAT_R32G32_USCALED] = BRW_SURFACEFORMAT_R32G32_USCALED, - [PIPE_FORMAT_R32G32B32_USCALED] = BRW_SURFACEFORMAT_R32G32B32_USCALED, - [PIPE_FORMAT_R32G32B32A32_USCALED] = BRW_SURFACEFORMAT_R32G32B32A32_USCALED, - [PIPE_FORMAT_R32_SNORM] = BRW_SURFACEFORMAT_R32_SNORM, - [PIPE_FORMAT_R32G32_SNORM] = BRW_SURFACEFORMAT_R32G32_SNORM, - [PIPE_FORMAT_R32G32B32_SNORM] = BRW_SURFACEFORMAT_R32G32B32_SNORM, - [PIPE_FORMAT_R32G32B32A32_SNORM] = BRW_SURFACEFORMAT_R32G32B32A32_SNORM, - [PIPE_FORMAT_R32_SSCALED] = BRW_SURFACEFORMAT_R32_SSCALED, - [PIPE_FORMAT_R32G32_SSCALED] = BRW_SURFACEFORMAT_R32G32_SSCALED, - [PIPE_FORMAT_R32G32B32_SSCALED] = BRW_SURFACEFORMAT_R32G32B32_SSCALED, - [PIPE_FORMAT_R32G32B32A32_SSCALED] = BRW_SURFACEFORMAT_R32G32B32A32_SSCALED, - [PIPE_FORMAT_R16_UNORM] = BRW_SURFACEFORMAT_R16_UNORM, - [PIPE_FORMAT_R16G16_UNORM] = BRW_SURFACEFORMAT_R16G16_UNORM, - [PIPE_FORMAT_R16G16B16_UNORM] = BRW_SURFACEFORMAT_R16G16B16_UNORM, - [PIPE_FORMAT_R16G16B16A16_UNORM] = BRW_SURFACEFORMAT_R16G16B16A16_UNORM, - [PIPE_FORMAT_R16_USCALED] = BRW_SURFACEFORMAT_R16_USCALED, - [PIPE_FORMAT_R16G16_USCALED] = BRW_SURFACEFORMAT_R16G16_USCALED, - [PIPE_FORMAT_R16G16B16_USCALED] = BRW_SURFACEFORMAT_R16G16B16_USCALED, - [PIPE_FORMAT_R16G16B16A16_USCALED] = BRW_SURFACEFORMAT_R16G16B16A16_USCALED, - [PIPE_FORMAT_R16_SNORM] = BRW_SURFACEFORMAT_R16_SNORM, - [PIPE_FORMAT_R16G16_SNORM] = BRW_SURFACEFORMAT_R16G16_SNORM, - [PIPE_FORMAT_R16G16B16_SNORM] = BRW_SURFACEFORMAT_R16G16B16_SNORM, - [PIPE_FORMAT_R16G16B16A16_SNORM] = BRW_SURFACEFORMAT_R16G16B16A16_SNORM, - [PIPE_FORMAT_R16_SSCALED] = BRW_SURFACEFORMAT_R16_SSCALED, - [PIPE_FORMAT_R16G16_SSCALED] = BRW_SURFACEFORMAT_R16G16_SSCALED, - [PIPE_FORMAT_R16G16B16_SSCALED] = BRW_SURFACEFORMAT_R16G16B16_SSCALED, - [PIPE_FORMAT_R16G16B16A16_SSCALED] = BRW_SURFACEFORMAT_R16G16B16A16_SSCALED, - [PIPE_FORMAT_R8_UNORM] = BRW_SURFACEFORMAT_R8_UNORM, - [PIPE_FORMAT_R8G8_UNORM] = BRW_SURFACEFORMAT_R8G8_UNORM, - [PIPE_FORMAT_R8G8B8_UNORM] = BRW_SURFACEFORMAT_R8G8B8_UNORM, - [PIPE_FORMAT_R8G8B8A8_UNORM] = BRW_SURFACEFORMAT_R8G8B8A8_UNORM, + [PIPE_FORMAT_R64_FLOAT] = GEN6_FORMAT_R64_FLOAT, + [PIPE_FORMAT_R64G64_FLOAT] = GEN6_FORMAT_R64G64_FLOAT, + [PIPE_FORMAT_R64G64B64_FLOAT] = GEN6_FORMAT_R64G64B64_FLOAT, + [PIPE_FORMAT_R64G64B64A64_FLOAT] = GEN6_FORMAT_R64G64B64A64_FLOAT, + [PIPE_FORMAT_R32_FLOAT] = GEN6_FORMAT_R32_FLOAT, + [PIPE_FORMAT_R32G32_FLOAT] = GEN6_FORMAT_R32G32_FLOAT, + [PIPE_FORMAT_R32G32B32_FLOAT] = GEN6_FORMAT_R32G32B32_FLOAT, + [PIPE_FORMAT_R32G32B32A32_FLOAT] = GEN6_FORMAT_R32G32B32A32_FLOAT, + [PIPE_FORMAT_R32_UNORM] = GEN6_FORMAT_R32_UNORM, + [PIPE_FORMAT_R32G32_UNORM] = GEN6_FORMAT_R32G32_UNORM, + [PIPE_FORMAT_R32G32B32_UNORM] = GEN6_FORMAT_R32G32B32_UNORM, + [PIPE_FORMAT_R32G32B32A32_UNORM] = GEN6_FORMAT_R32G32B32A32_UNORM, + [PIPE_FORMAT_R32_USCALED] = GEN6_FORMAT_R32_USCALED, + [PIPE_FORMAT_R32G32_USCALED] = GEN6_FORMAT_R32G32_USCALED, + [PIPE_FORMAT_R32G32B32_USCALED] = GEN6_FORMAT_R32G32B32_USCALED, + [PIPE_FORMAT_R32G32B32A32_USCALED] = GEN6_FORMAT_R32G32B32A32_USCALED, + [PIPE_FORMAT_R32_SNORM] = GEN6_FORMAT_R32_SNORM, + [PIPE_FORMAT_R32G32_SNORM] = GEN6_FORMAT_R32G32_SNORM, + [PIPE_FORMAT_R32G32B32_SNORM] = GEN6_FORMAT_R32G32B32_SNORM, + [PIPE_FORMAT_R32G32B32A32_SNORM] = GEN6_FORMAT_R32G32B32A32_SNORM, + [PIPE_FORMAT_R32_SSCALED] = GEN6_FORMAT_R32_SSCALED, + [PIPE_FORMAT_R32G32_SSCALED] = GEN6_FORMAT_R32G32_SSCALED, + [PIPE_FORMAT_R32G32B32_SSCALED] = GEN6_FORMAT_R32G32B32_SSCALED, + [PIPE_FORMAT_R32G32B32A32_SSCALED] = GEN6_FORMAT_R32G32B32A32_SSCALED, + [PIPE_FORMAT_R16_UNORM] = GEN6_FORMAT_R16_UNORM, + [PIPE_FORMAT_R16G16_UNORM] = GEN6_FORMAT_R16G16_UNORM, + [PIPE_FORMAT_R16G16B16_UNORM] = GEN6_FORMAT_R16G16B16_UNORM, + [PIPE_FORMAT_R16G16B16A16_UNORM] = GEN6_FORMAT_R16G16B16A16_UNORM, + [PIPE_FORMAT_R16_USCALED] = GEN6_FORMAT_R16_USCALED, + [PIPE_FORMAT_R16G16_USCALED] = GEN6_FORMAT_R16G16_USCALED, + [PIPE_FORMAT_R16G16B16_USCALED] = GEN6_FORMAT_R16G16B16_USCALED, + [PIPE_FORMAT_R16G16B16A16_USCALED] = GEN6_FORMAT_R16G16B16A16_USCALED, + [PIPE_FORMAT_R16_SNORM] = GEN6_FORMAT_R16_SNORM, + [PIPE_FORMAT_R16G16_SNORM] = GEN6_FORMAT_R16G16_SNORM, + [PIPE_FORMAT_R16G16B16_SNORM] = GEN6_FORMAT_R16G16B16_SNORM, + [PIPE_FORMAT_R16G16B16A16_SNORM] = GEN6_FORMAT_R16G16B16A16_SNORM, + [PIPE_FORMAT_R16_SSCALED] = GEN6_FORMAT_R16_SSCALED, + [PIPE_FORMAT_R16G16_SSCALED] = GEN6_FORMAT_R16G16_SSCALED, + [PIPE_FORMAT_R16G16B16_SSCALED] = GEN6_FORMAT_R16G16B16_SSCALED, + [PIPE_FORMAT_R16G16B16A16_SSCALED] = GEN6_FORMAT_R16G16B16A16_SSCALED, + [PIPE_FORMAT_R8_UNORM] = GEN6_FORMAT_R8_UNORM, + [PIPE_FORMAT_R8G8_UNORM] = GEN6_FORMAT_R8G8_UNORM, + [PIPE_FORMAT_R8G8B8_UNORM] = GEN6_FORMAT_R8G8B8_UNORM, + [PIPE_FORMAT_R8G8B8A8_UNORM] = GEN6_FORMAT_R8G8B8A8_UNORM, [PIPE_FORMAT_X8B8G8R8_UNORM] = 0, - [PIPE_FORMAT_R8_USCALED] = BRW_SURFACEFORMAT_R8_USCALED, - [PIPE_FORMAT_R8G8_USCALED] = BRW_SURFACEFORMAT_R8G8_USCALED, - [PIPE_FORMAT_R8G8B8_USCALED] = BRW_SURFACEFORMAT_R8G8B8_USCALED, - [PIPE_FORMAT_R8G8B8A8_USCALED] = BRW_SURFACEFORMAT_R8G8B8A8_USCALED, - [PIPE_FORMAT_R8_SNORM] = BRW_SURFACEFORMAT_R8_SNORM, - [PIPE_FORMAT_R8G8_SNORM] = BRW_SURFACEFORMAT_R8G8_SNORM, - [PIPE_FORMAT_R8G8B8_SNORM] = BRW_SURFACEFORMAT_R8G8B8_SNORM, - [PIPE_FORMAT_R8G8B8A8_SNORM] = BRW_SURFACEFORMAT_R8G8B8A8_SNORM, - [PIPE_FORMAT_R8_SSCALED] = BRW_SURFACEFORMAT_R8_SSCALED, - [PIPE_FORMAT_R8G8_SSCALED] = BRW_SURFACEFORMAT_R8G8_SSCALED, - [PIPE_FORMAT_R8G8B8_SSCALED] = BRW_SURFACEFORMAT_R8G8B8_SSCALED, - [PIPE_FORMAT_R8G8B8A8_SSCALED] = BRW_SURFACEFORMAT_R8G8B8A8_SSCALED, - [PIPE_FORMAT_R32_FIXED] = BRW_SURFACEFORMAT_R32_SFIXED, - [PIPE_FORMAT_R32G32_FIXED] = BRW_SURFACEFORMAT_R32G32_SFIXED, - [PIPE_FORMAT_R32G32B32_FIXED] = BRW_SURFACEFORMAT_R32G32B32_SFIXED, - [PIPE_FORMAT_R32G32B32A32_FIXED] = BRW_SURFACEFORMAT_R32G32B32A32_SFIXED, - [PIPE_FORMAT_R16_FLOAT] = BRW_SURFACEFORMAT_R16_FLOAT, - [PIPE_FORMAT_R16G16_FLOAT] = BRW_SURFACEFORMAT_R16G16_FLOAT, - [PIPE_FORMAT_R16G16B16_FLOAT] = BRW_SURFACEFORMAT_R16G16B16_FLOAT, - [PIPE_FORMAT_R16G16B16A16_FLOAT] = BRW_SURFACEFORMAT_R16G16B16A16_FLOAT, - [PIPE_FORMAT_L8_SRGB] = BRW_SURFACEFORMAT_L8_UNORM_SRGB, - [PIPE_FORMAT_L8A8_SRGB] = BRW_SURFACEFORMAT_L8A8_UNORM_SRGB, - [PIPE_FORMAT_R8G8B8_SRGB] = BRW_SURFACEFORMAT_R8G8B8_UNORM_SRGB, + [PIPE_FORMAT_R8_USCALED] = GEN6_FORMAT_R8_USCALED, + [PIPE_FORMAT_R8G8_USCALED] = GEN6_FORMAT_R8G8_USCALED, + [PIPE_FORMAT_R8G8B8_USCALED] = GEN6_FORMAT_R8G8B8_USCALED, + [PIPE_FORMAT_R8G8B8A8_USCALED] = GEN6_FORMAT_R8G8B8A8_USCALED, + [PIPE_FORMAT_R8_SNORM] = GEN6_FORMAT_R8_SNORM, + [PIPE_FORMAT_R8G8_SNORM] = GEN6_FORMAT_R8G8_SNORM, + [PIPE_FORMAT_R8G8B8_SNORM] = GEN6_FORMAT_R8G8B8_SNORM, + [PIPE_FORMAT_R8G8B8A8_SNORM] = GEN6_FORMAT_R8G8B8A8_SNORM, + [PIPE_FORMAT_R8_SSCALED] = GEN6_FORMAT_R8_SSCALED, + [PIPE_FORMAT_R8G8_SSCALED] = GEN6_FORMAT_R8G8_SSCALED, + [PIPE_FORMAT_R8G8B8_SSCALED] = GEN6_FORMAT_R8G8B8_SSCALED, + [PIPE_FORMAT_R8G8B8A8_SSCALED] = GEN6_FORMAT_R8G8B8A8_SSCALED, + [PIPE_FORMAT_R32_FIXED] = GEN6_FORMAT_R32_SFIXED, + [PIPE_FORMAT_R32G32_FIXED] = GEN6_FORMAT_R32G32_SFIXED, + [PIPE_FORMAT_R32G32B32_FIXED] = GEN6_FORMAT_R32G32B32_SFIXED, + [PIPE_FORMAT_R32G32B32A32_FIXED] = GEN6_FORMAT_R32G32B32A32_SFIXED, + [PIPE_FORMAT_R16_FLOAT] = GEN6_FORMAT_R16_FLOAT, + [PIPE_FORMAT_R16G16_FLOAT] = GEN6_FORMAT_R16G16_FLOAT, + [PIPE_FORMAT_R16G16B16_FLOAT] = GEN6_FORMAT_R16G16B16_FLOAT, + [PIPE_FORMAT_R16G16B16A16_FLOAT] = GEN6_FORMAT_R16G16B16A16_FLOAT, + [PIPE_FORMAT_L8_SRGB] = GEN6_FORMAT_L8_UNORM_SRGB, + [PIPE_FORMAT_L8A8_SRGB] = GEN6_FORMAT_L8A8_UNORM_SRGB, + [PIPE_FORMAT_R8G8B8_SRGB] = GEN6_FORMAT_R8G8B8_UNORM_SRGB, [PIPE_FORMAT_A8B8G8R8_SRGB] = 0, [PIPE_FORMAT_X8B8G8R8_SRGB] = 0, - [PIPE_FORMAT_B8G8R8A8_SRGB] = BRW_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB, + [PIPE_FORMAT_B8G8R8A8_SRGB] = GEN6_FORMAT_B8G8R8A8_UNORM_SRGB, [PIPE_FORMAT_B8G8R8X8_SRGB] = 0, [PIPE_FORMAT_A8R8G8B8_SRGB] = 0, [PIPE_FORMAT_X8R8G8B8_SRGB] = 0, [PIPE_FORMAT_R8G8B8A8_SRGB] = 0, - [PIPE_FORMAT_DXT1_RGB] = BRW_SURFACEFORMAT_DXT1_RGB, - [PIPE_FORMAT_DXT1_RGBA] = BRW_SURFACEFORMAT_BC1_UNORM, - [PIPE_FORMAT_DXT3_RGBA] = BRW_SURFACEFORMAT_BC2_UNORM, - [PIPE_FORMAT_DXT5_RGBA] = BRW_SURFACEFORMAT_BC3_UNORM, - [PIPE_FORMAT_DXT1_SRGB] = BRW_SURFACEFORMAT_DXT1_RGB_SRGB, - [PIPE_FORMAT_DXT1_SRGBA] = BRW_SURFACEFORMAT_BC1_UNORM_SRGB, - [PIPE_FORMAT_DXT3_SRGBA] = BRW_SURFACEFORMAT_BC2_UNORM_SRGB, - [PIPE_FORMAT_DXT5_SRGBA] = BRW_SURFACEFORMAT_BC3_UNORM_SRGB, - [PIPE_FORMAT_RGTC1_UNORM] = BRW_SURFACEFORMAT_BC4_UNORM, - [PIPE_FORMAT_RGTC1_SNORM] = BRW_SURFACEFORMAT_BC4_SNORM, - [PIPE_FORMAT_RGTC2_UNORM] = BRW_SURFACEFORMAT_BC5_UNORM, - [PIPE_FORMAT_RGTC2_SNORM] = BRW_SURFACEFORMAT_BC5_SNORM, + [PIPE_FORMAT_DXT1_RGB] = GEN6_FORMAT_DXT1_RGB, + [PIPE_FORMAT_DXT1_RGBA] = GEN6_FORMAT_BC1_UNORM, + [PIPE_FORMAT_DXT3_RGBA] = GEN6_FORMAT_BC2_UNORM, + [PIPE_FORMAT_DXT5_RGBA] = GEN6_FORMAT_BC3_UNORM, + [PIPE_FORMAT_DXT1_SRGB] = GEN6_FORMAT_DXT1_RGB_SRGB, + [PIPE_FORMAT_DXT1_SRGBA] = GEN6_FORMAT_BC1_UNORM_SRGB, + [PIPE_FORMAT_DXT3_SRGBA] = GEN6_FORMAT_BC2_UNORM_SRGB, + [PIPE_FORMAT_DXT5_SRGBA] = GEN6_FORMAT_BC3_UNORM_SRGB, + [PIPE_FORMAT_RGTC1_UNORM] = GEN6_FORMAT_BC4_UNORM, + [PIPE_FORMAT_RGTC1_SNORM] = GEN6_FORMAT_BC4_SNORM, + [PIPE_FORMAT_RGTC2_UNORM] = GEN6_FORMAT_BC5_UNORM, + [PIPE_FORMAT_RGTC2_SNORM] = GEN6_FORMAT_BC5_SNORM, [PIPE_FORMAT_R8G8_B8G8_UNORM] = 0, [PIPE_FORMAT_G8R8_G8B8_UNORM] = 0, [PIPE_FORMAT_R8SG8SB8UX8U_NORM] = 0, [PIPE_FORMAT_R5SG5SB6U_NORM] = 0, [PIPE_FORMAT_A8B8G8R8_UNORM] = 0, - [PIPE_FORMAT_B5G5R5X1_UNORM] = BRW_SURFACEFORMAT_B5G5R5X1_UNORM, - [PIPE_FORMAT_R10G10B10A2_USCALED] = BRW_SURFACEFORMAT_R10G10B10A2_USCALED, - [PIPE_FORMAT_R11G11B10_FLOAT] = BRW_SURFACEFORMAT_R11G11B10_FLOAT, - [PIPE_FORMAT_R9G9B9E5_FLOAT] = BRW_SURFACEFORMAT_R9G9B9E5_SHAREDEXP, + [PIPE_FORMAT_B5G5R5X1_UNORM] = GEN6_FORMAT_B5G5R5X1_UNORM, + [PIPE_FORMAT_R10G10B10A2_USCALED] = GEN6_FORMAT_R10G10B10A2_USCALED, + [PIPE_FORMAT_R11G11B10_FLOAT] = GEN6_FORMAT_R11G11B10_FLOAT, + [PIPE_FORMAT_R9G9B9E5_FLOAT] = GEN6_FORMAT_R9G9B9E5_SHAREDEXP, [PIPE_FORMAT_Z32_FLOAT_S8X24_UINT] = 0, [PIPE_FORMAT_R1_UNORM] = 0, - [PIPE_FORMAT_R10G10B10X2_USCALED] = BRW_SURFACEFORMAT_R10G10B10X2_USCALED, + [PIPE_FORMAT_R10G10B10X2_USCALED] = GEN6_FORMAT_R10G10B10X2_USCALED, [PIPE_FORMAT_R10G10B10X2_SNORM] = 0, [PIPE_FORMAT_L4A4_UNORM] = 0, - [PIPE_FORMAT_B10G10R10A2_UNORM] = BRW_SURFACEFORMAT_B10G10R10A2_UNORM, + [PIPE_FORMAT_B10G10R10A2_UNORM] = GEN6_FORMAT_B10G10R10A2_UNORM, [PIPE_FORMAT_R10SG10SB10SA2U_NORM] = 0, [PIPE_FORMAT_R8G8Bx_SNORM] = 0, - [PIPE_FORMAT_R8G8B8X8_UNORM] = BRW_SURFACEFORMAT_R8G8B8X8_UNORM, + [PIPE_FORMAT_R8G8B8X8_UNORM] = GEN6_FORMAT_R8G8B8X8_UNORM, [PIPE_FORMAT_B4G4R4X4_UNORM] = 0, [PIPE_FORMAT_X24S8_UINT] = 0, [PIPE_FORMAT_S8X24_UINT] = 0, [PIPE_FORMAT_X32_S8X24_UINT] = 0, [PIPE_FORMAT_B2G3R3_UNORM] = 0, - [PIPE_FORMAT_L16A16_UNORM] = BRW_SURFACEFORMAT_L16A16_UNORM, - [PIPE_FORMAT_A16_UNORM] = BRW_SURFACEFORMAT_A16_UNORM, - [PIPE_FORMAT_I16_UNORM] = BRW_SURFACEFORMAT_I16_UNORM, + [PIPE_FORMAT_L16A16_UNORM] = GEN6_FORMAT_L16A16_UNORM, + [PIPE_FORMAT_A16_UNORM] = GEN6_FORMAT_A16_UNORM, + [PIPE_FORMAT_I16_UNORM] = GEN6_FORMAT_I16_UNORM, [PIPE_FORMAT_LATC1_UNORM] = 0, [PIPE_FORMAT_LATC1_SNORM] = 0, [PIPE_FORMAT_LATC2_UNORM] = 0, @@ -491,14 +491,14 @@ ilo_translate_color_format(enum pipe_format format) [PIPE_FORMAT_L16_SNORM] = 0, [PIPE_FORMAT_L16A16_SNORM] = 0, [PIPE_FORMAT_I16_SNORM] = 0, - [PIPE_FORMAT_A16_FLOAT] = BRW_SURFACEFORMAT_A16_FLOAT, - [PIPE_FORMAT_L16_FLOAT] = BRW_SURFACEFORMAT_L16_FLOAT, - [PIPE_FORMAT_L16A16_FLOAT] = BRW_SURFACEFORMAT_L16A16_FLOAT, - [PIPE_FORMAT_I16_FLOAT] = BRW_SURFACEFORMAT_I16_FLOAT, - [PIPE_FORMAT_A32_FLOAT] = BRW_SURFACEFORMAT_A32_FLOAT, - [PIPE_FORMAT_L32_FLOAT] = BRW_SURFACEFORMAT_L32_FLOAT, - [PIPE_FORMAT_L32A32_FLOAT] = BRW_SURFACEFORMAT_L32A32_FLOAT, - [PIPE_FORMAT_I32_FLOAT] = BRW_SURFACEFORMAT_I32_FLOAT, + [PIPE_FORMAT_A16_FLOAT] = GEN6_FORMAT_A16_FLOAT, + [PIPE_FORMAT_L16_FLOAT] = GEN6_FORMAT_L16_FLOAT, + [PIPE_FORMAT_L16A16_FLOAT] = GEN6_FORMAT_L16A16_FLOAT, + [PIPE_FORMAT_I16_FLOAT] = GEN6_FORMAT_I16_FLOAT, + [PIPE_FORMAT_A32_FLOAT] = GEN6_FORMAT_A32_FLOAT, + [PIPE_FORMAT_L32_FLOAT] = GEN6_FORMAT_L32_FLOAT, + [PIPE_FORMAT_L32A32_FLOAT] = GEN6_FORMAT_L32A32_FLOAT, + [PIPE_FORMAT_I32_FLOAT] = GEN6_FORMAT_I32_FLOAT, [PIPE_FORMAT_YV12] = 0, [PIPE_FORMAT_YV16] = 0, [PIPE_FORMAT_IYUV] = 0, @@ -508,43 +508,43 @@ ilo_translate_color_format(enum pipe_format format) [PIPE_FORMAT_R4A4_UNORM] = 0, [PIPE_FORMAT_R8A8_UNORM] = 0, [PIPE_FORMAT_A8R8_UNORM] = 0, - [PIPE_FORMAT_R10G10B10A2_SSCALED] = BRW_SURFACEFORMAT_R10G10B10A2_SSCALED, - [PIPE_FORMAT_R10G10B10A2_SNORM] = BRW_SURFACEFORMAT_R10G10B10A2_SNORM, - [PIPE_FORMAT_B10G10R10A2_USCALED] = BRW_SURFACEFORMAT_B10G10R10A2_USCALED, - [PIPE_FORMAT_B10G10R10A2_SSCALED] = BRW_SURFACEFORMAT_B10G10R10A2_SSCALED, - [PIPE_FORMAT_B10G10R10A2_SNORM] = BRW_SURFACEFORMAT_B10G10R10A2_SNORM, - [PIPE_FORMAT_R8_UINT] = BRW_SURFACEFORMAT_R8_UINT, - [PIPE_FORMAT_R8G8_UINT] = BRW_SURFACEFORMAT_R8G8_UINT, - [PIPE_FORMAT_R8G8B8_UINT] = BRW_SURFACEFORMAT_R8G8B8_UINT, - [PIPE_FORMAT_R8G8B8A8_UINT] = BRW_SURFACEFORMAT_R8G8B8A8_UINT, - [PIPE_FORMAT_R8_SINT] = BRW_SURFACEFORMAT_R8_SINT, - [PIPE_FORMAT_R8G8_SINT] = BRW_SURFACEFORMAT_R8G8_SINT, - [PIPE_FORMAT_R8G8B8_SINT] = BRW_SURFACEFORMAT_R8G8B8_SINT, - [PIPE_FORMAT_R8G8B8A8_SINT] = BRW_SURFACEFORMAT_R8G8B8A8_SINT, - [PIPE_FORMAT_R16_UINT] = BRW_SURFACEFORMAT_R16_UINT, - [PIPE_FORMAT_R16G16_UINT] = BRW_SURFACEFORMAT_R16G16_UINT, - [PIPE_FORMAT_R16G16B16_UINT] = BRW_SURFACEFORMAT_R16G16B16_UINT, - [PIPE_FORMAT_R16G16B16A16_UINT] = BRW_SURFACEFORMAT_R16G16B16A16_UINT, - [PIPE_FORMAT_R16_SINT] = BRW_SURFACEFORMAT_R16_SINT, - [PIPE_FORMAT_R16G16_SINT] = BRW_SURFACEFORMAT_R16G16_SINT, - [PIPE_FORMAT_R16G16B16_SINT] = BRW_SURFACEFORMAT_R16G16B16_SINT, - [PIPE_FORMAT_R16G16B16A16_SINT] = BRW_SURFACEFORMAT_R16G16B16A16_SINT, - [PIPE_FORMAT_R32_UINT] = BRW_SURFACEFORMAT_R32_UINT, - [PIPE_FORMAT_R32G32_UINT] = BRW_SURFACEFORMAT_R32G32_UINT, - [PIPE_FORMAT_R32G32B32_UINT] = BRW_SURFACEFORMAT_R32G32B32_UINT, - [PIPE_FORMAT_R32G32B32A32_UINT] = BRW_SURFACEFORMAT_R32G32B32A32_UINT, - [PIPE_FORMAT_R32_SINT] = BRW_SURFACEFORMAT_R32_SINT, - [PIPE_FORMAT_R32G32_SINT] = BRW_SURFACEFORMAT_R32G32_SINT, - [PIPE_FORMAT_R32G32B32_SINT] = BRW_SURFACEFORMAT_R32G32B32_SINT, - [PIPE_FORMAT_R32G32B32A32_SINT] = BRW_SURFACEFORMAT_R32G32B32A32_SINT, + [PIPE_FORMAT_R10G10B10A2_SSCALED] = GEN6_FORMAT_R10G10B10A2_SSCALED, + [PIPE_FORMAT_R10G10B10A2_SNORM] = GEN6_FORMAT_R10G10B10A2_SNORM, + [PIPE_FORMAT_B10G10R10A2_USCALED] = GEN6_FORMAT_B10G10R10A2_USCALED, + [PIPE_FORMAT_B10G10R10A2_SSCALED] = GEN6_FORMAT_B10G10R10A2_SSCALED, + [PIPE_FORMAT_B10G10R10A2_SNORM] = GEN6_FORMAT_B10G10R10A2_SNORM, + [PIPE_FORMAT_R8_UINT] = GEN6_FORMAT_R8_UINT, + [PIPE_FORMAT_R8G8_UINT] = GEN6_FORMAT_R8G8_UINT, + [PIPE_FORMAT_R8G8B8_UINT] = GEN6_FORMAT_R8G8B8_UINT, + [PIPE_FORMAT_R8G8B8A8_UINT] = GEN6_FORMAT_R8G8B8A8_UINT, + [PIPE_FORMAT_R8_SINT] = GEN6_FORMAT_R8_SINT, + [PIPE_FORMAT_R8G8_SINT] = GEN6_FORMAT_R8G8_SINT, + [PIPE_FORMAT_R8G8B8_SINT] = GEN6_FORMAT_R8G8B8_SINT, + [PIPE_FORMAT_R8G8B8A8_SINT] = GEN6_FORMAT_R8G8B8A8_SINT, + [PIPE_FORMAT_R16_UINT] = GEN6_FORMAT_R16_UINT, + [PIPE_FORMAT_R16G16_UINT] = GEN6_FORMAT_R16G16_UINT, + [PIPE_FORMAT_R16G16B16_UINT] = GEN6_FORMAT_R16G16B16_UINT, + [PIPE_FORMAT_R16G16B16A16_UINT] = GEN6_FORMAT_R16G16B16A16_UINT, + [PIPE_FORMAT_R16_SINT] = GEN6_FORMAT_R16_SINT, + [PIPE_FORMAT_R16G16_SINT] = GEN6_FORMAT_R16G16_SINT, + [PIPE_FORMAT_R16G16B16_SINT] = GEN6_FORMAT_R16G16B16_SINT, + [PIPE_FORMAT_R16G16B16A16_SINT] = GEN6_FORMAT_R16G16B16A16_SINT, + [PIPE_FORMAT_R32_UINT] = GEN6_FORMAT_R32_UINT, + [PIPE_FORMAT_R32G32_UINT] = GEN6_FORMAT_R32G32_UINT, + [PIPE_FORMAT_R32G32B32_UINT] = GEN6_FORMAT_R32G32B32_UINT, + [PIPE_FORMAT_R32G32B32A32_UINT] = GEN6_FORMAT_R32G32B32A32_UINT, + [PIPE_FORMAT_R32_SINT] = GEN6_FORMAT_R32_SINT, + [PIPE_FORMAT_R32G32_SINT] = GEN6_FORMAT_R32G32_SINT, + [PIPE_FORMAT_R32G32B32_SINT] = GEN6_FORMAT_R32G32B32_SINT, + [PIPE_FORMAT_R32G32B32A32_SINT] = GEN6_FORMAT_R32G32B32A32_SINT, [PIPE_FORMAT_A8_UINT] = 0, - [PIPE_FORMAT_I8_UINT] = BRW_SURFACEFORMAT_I8_UINT, - [PIPE_FORMAT_L8_UINT] = BRW_SURFACEFORMAT_L8_UINT, - [PIPE_FORMAT_L8A8_UINT] = BRW_SURFACEFORMAT_L8A8_UINT, + [PIPE_FORMAT_I8_UINT] = GEN6_FORMAT_I8_UINT, + [PIPE_FORMAT_L8_UINT] = GEN6_FORMAT_L8_UINT, + [PIPE_FORMAT_L8A8_UINT] = GEN6_FORMAT_L8A8_UINT, [PIPE_FORMAT_A8_SINT] = 0, - [PIPE_FORMAT_I8_SINT] = BRW_SURFACEFORMAT_I8_SINT, - [PIPE_FORMAT_L8_SINT] = BRW_SURFACEFORMAT_L8_SINT, - [PIPE_FORMAT_L8A8_SINT] = BRW_SURFACEFORMAT_L8A8_SINT, + [PIPE_FORMAT_I8_SINT] = GEN6_FORMAT_I8_SINT, + [PIPE_FORMAT_L8_SINT] = GEN6_FORMAT_L8_SINT, + [PIPE_FORMAT_L8A8_SINT] = GEN6_FORMAT_L8A8_SINT, [PIPE_FORMAT_A16_UINT] = 0, [PIPE_FORMAT_I16_UINT] = 0, [PIPE_FORMAT_L16_UINT] = 0, @@ -561,21 +561,21 @@ ilo_translate_color_format(enum pipe_format format) [PIPE_FORMAT_I32_SINT] = 0, [PIPE_FORMAT_L32_SINT] = 0, [PIPE_FORMAT_L32A32_SINT] = 0, - [PIPE_FORMAT_B10G10R10A2_UINT] = BRW_SURFACEFORMAT_B10G10R10A2_UINT, - [PIPE_FORMAT_ETC1_RGB8] = BRW_SURFACEFORMAT_ETC1_RGB8, + [PIPE_FORMAT_B10G10R10A2_UINT] = GEN6_FORMAT_B10G10R10A2_UINT, + [PIPE_FORMAT_ETC1_RGB8] = GEN6_FORMAT_ETC1_RGB8, [PIPE_FORMAT_R8G8_R8B8_UNORM] = 0, [PIPE_FORMAT_G8R8_B8R8_UNORM] = 0, [PIPE_FORMAT_R8G8B8X8_SNORM] = 0, [PIPE_FORMAT_R8G8B8X8_SRGB] = 0, [PIPE_FORMAT_R8G8B8X8_UINT] = 0, [PIPE_FORMAT_R8G8B8X8_SINT] = 0, - [PIPE_FORMAT_B10G10R10X2_UNORM] = BRW_SURFACEFORMAT_B10G10R10X2_UNORM, - [PIPE_FORMAT_R16G16B16X16_UNORM] = BRW_SURFACEFORMAT_R16G16B16X16_UNORM, + [PIPE_FORMAT_B10G10R10X2_UNORM] = GEN6_FORMAT_B10G10R10X2_UNORM, + [PIPE_FORMAT_R16G16B16X16_UNORM] = GEN6_FORMAT_R16G16B16X16_UNORM, [PIPE_FORMAT_R16G16B16X16_SNORM] = 0, - [PIPE_FORMAT_R16G16B16X16_FLOAT] = BRW_SURFACEFORMAT_R16G16B16X16_FLOAT, + [PIPE_FORMAT_R16G16B16X16_FLOAT] = GEN6_FORMAT_R16G16B16X16_FLOAT, [PIPE_FORMAT_R16G16B16X16_UINT] = 0, [PIPE_FORMAT_R16G16B16X16_SINT] = 0, - [PIPE_FORMAT_R32G32B32X32_FLOAT] = BRW_SURFACEFORMAT_R32G32B32X32_FLOAT, + [PIPE_FORMAT_R32G32B32X32_FLOAT] = GEN6_FORMAT_R32G32B32X32_FLOAT, [PIPE_FORMAT_R32G32B32X32_UINT] = 0, [PIPE_FORMAT_R32G32B32X32_SINT] = 0, [PIPE_FORMAT_R8A8_SNORM] = 0, @@ -589,11 +589,11 @@ ilo_translate_color_format(enum pipe_format format) [PIPE_FORMAT_R16A16_SINT] = 0, [PIPE_FORMAT_R32A32_UINT] = 0, [PIPE_FORMAT_R32A32_SINT] = 0, - [PIPE_FORMAT_R10G10B10A2_UINT] = BRW_SURFACEFORMAT_R10G10B10A2_UINT, + [PIPE_FORMAT_R10G10B10A2_UINT] = GEN6_FORMAT_R10G10B10A2_UINT, }; int sfmt = format_mapping[format]; - /* BRW_SURFACEFORMAT_R32G32B32A32_FLOAT happens to be 0 */ + /* GEN6_FORMAT_R32G32B32A32_FLOAT happens to be 0 */ if (!sfmt && format != PIPE_FORMAT_R32G32B32A32_FLOAT) sfmt = -1; diff --git a/src/gallium/drivers/ilo/ilo_format.h b/src/gallium/drivers/ilo/ilo_format.h index 1be3577774d..2ea7885694e 100644 --- a/src/gallium/drivers/ilo/ilo_format.h +++ b/src/gallium/drivers/ilo/ilo_format.h @@ -59,7 +59,7 @@ ilo_translate_format(enum pipe_format format, unsigned bind) */ switch (format) { case PIPE_FORMAT_B8G8R8X8_UNORM: - return BRW_SURFACEFORMAT_B8G8R8A8_UNORM; + return GEN6_FORMAT_B8G8R8A8_UNORM; default: return ilo_translate_color_format(format); } @@ -76,16 +76,16 @@ ilo_translate_format(enum pipe_format format, unsigned bind) */ switch (format) { case PIPE_FORMAT_Z16_UNORM: - return BRW_SURFACEFORMAT_I16_UNORM; + return GEN6_FORMAT_I16_UNORM; case PIPE_FORMAT_Z32_FLOAT: - return BRW_SURFACEFORMAT_I32_FLOAT; + return GEN6_FORMAT_I32_FLOAT; case PIPE_FORMAT_Z24X8_UNORM: case PIPE_FORMAT_Z24_UNORM_S8_UINT: - return BRW_SURFACEFORMAT_I24X8_UNORM; + return GEN6_FORMAT_I24X8_UNORM; case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: - return BRW_SURFACEFORMAT_I32X32_FLOAT; + return GEN6_FORMAT_I32X32_FLOAT; case PIPE_FORMAT_ETC1_RGB8: - return BRW_SURFACEFORMAT_R8G8B8X8_UNORM; + return GEN6_FORMAT_R8G8B8X8_UNORM; default: return ilo_translate_color_format(format); } @@ -100,15 +100,15 @@ ilo_translate_format(enum pipe_format format, unsigned bind) */ switch (format) { case PIPE_FORMAT_R16G16B16_FLOAT: - return BRW_SURFACEFORMAT_R16G16B16A16_FLOAT; + return GEN6_FORMAT_R16G16B16A16_FLOAT; case PIPE_FORMAT_R16G16B16_UINT: - return BRW_SURFACEFORMAT_R16G16B16A16_UINT; + return GEN6_FORMAT_R16G16B16A16_UINT; case PIPE_FORMAT_R16G16B16_SINT: - return BRW_SURFACEFORMAT_R16G16B16A16_SINT; + return GEN6_FORMAT_R16G16B16A16_SINT; case PIPE_FORMAT_R8G8B8_UINT: - return BRW_SURFACEFORMAT_R8G8B8A8_UINT; + return GEN6_FORMAT_R8G8B8A8_UINT; case PIPE_FORMAT_R8G8B8_SINT: - return BRW_SURFACEFORMAT_R8G8B8A8_SINT; + return GEN6_FORMAT_R8G8B8A8_SINT; default: return ilo_translate_color_format(format); } diff --git a/src/gallium/drivers/ilo/ilo_gpe_gen6.c b/src/gallium/drivers/ilo/ilo_gpe_gen6.c index 0e2cb0ebd54..9f416ed67f1 100644 --- a/src/gallium/drivers/ilo/ilo_gpe_gen6.c +++ b/src/gallium/drivers/ilo/ilo_gpe_gen6.c @@ -44,25 +44,25 @@ static int gen6_translate_pipe_logicop(unsigned logicop) { switch (logicop) { - case PIPE_LOGICOP_CLEAR: return BRW_LOGICOPFUNCTION_CLEAR; - case PIPE_LOGICOP_NOR: return BRW_LOGICOPFUNCTION_NOR; - case PIPE_LOGICOP_AND_INVERTED: return BRW_LOGICOPFUNCTION_AND_INVERTED; - case PIPE_LOGICOP_COPY_INVERTED: return BRW_LOGICOPFUNCTION_COPY_INVERTED; - case PIPE_LOGICOP_AND_REVERSE: return BRW_LOGICOPFUNCTION_AND_REVERSE; - case PIPE_LOGICOP_INVERT: return BRW_LOGICOPFUNCTION_INVERT; - case PIPE_LOGICOP_XOR: return BRW_LOGICOPFUNCTION_XOR; - case PIPE_LOGICOP_NAND: return BRW_LOGICOPFUNCTION_NAND; - case PIPE_LOGICOP_AND: return BRW_LOGICOPFUNCTION_AND; - case PIPE_LOGICOP_EQUIV: return BRW_LOGICOPFUNCTION_EQUIV; - case PIPE_LOGICOP_NOOP: return BRW_LOGICOPFUNCTION_NOOP; - case PIPE_LOGICOP_OR_INVERTED: return BRW_LOGICOPFUNCTION_OR_INVERTED; - case PIPE_LOGICOP_COPY: return BRW_LOGICOPFUNCTION_COPY; - case PIPE_LOGICOP_OR_REVERSE: return BRW_LOGICOPFUNCTION_OR_REVERSE; - case PIPE_LOGICOP_OR: return BRW_LOGICOPFUNCTION_OR; - case PIPE_LOGICOP_SET: return BRW_LOGICOPFUNCTION_SET; + case PIPE_LOGICOP_CLEAR: return GEN6_LOGICOP_CLEAR; + case PIPE_LOGICOP_NOR: return GEN6_LOGICOP_NOR; + case PIPE_LOGICOP_AND_INVERTED: return GEN6_LOGICOP_AND_INVERTED; + case PIPE_LOGICOP_COPY_INVERTED: return GEN6_LOGICOP_COPY_INVERTED; + case PIPE_LOGICOP_AND_REVERSE: return GEN6_LOGICOP_AND_REVERSE; + case PIPE_LOGICOP_INVERT: return GEN6_LOGICOP_INVERT; + case PIPE_LOGICOP_XOR: return GEN6_LOGICOP_XOR; + case PIPE_LOGICOP_NAND: return GEN6_LOGICOP_NAND; + case PIPE_LOGICOP_AND: return GEN6_LOGICOP_AND; + case PIPE_LOGICOP_EQUIV: return GEN6_LOGICOP_EQUIV; + case PIPE_LOGICOP_NOOP: return GEN6_LOGICOP_NOOP; + case PIPE_LOGICOP_OR_INVERTED: return GEN6_LOGICOP_OR_INVERTED; + case PIPE_LOGICOP_COPY: return GEN6_LOGICOP_COPY; + case PIPE_LOGICOP_OR_REVERSE: return GEN6_LOGICOP_OR_REVERSE; + case PIPE_LOGICOP_OR: return GEN6_LOGICOP_OR; + case PIPE_LOGICOP_SET: return GEN6_LOGICOP_SET; default: assert(!"unknown logicop function"); - return BRW_LOGICOPFUNCTION_CLEAR; + return GEN6_LOGICOP_CLEAR; } } @@ -73,14 +73,14 @@ static int gen6_translate_pipe_blend(unsigned blend) { switch (blend) { - case PIPE_BLEND_ADD: return BRW_BLENDFUNCTION_ADD; - case PIPE_BLEND_SUBTRACT: return BRW_BLENDFUNCTION_SUBTRACT; - case PIPE_BLEND_REVERSE_SUBTRACT: return BRW_BLENDFUNCTION_REVERSE_SUBTRACT; - case PIPE_BLEND_MIN: return BRW_BLENDFUNCTION_MIN; - case PIPE_BLEND_MAX: return BRW_BLENDFUNCTION_MAX; + case PIPE_BLEND_ADD: return GEN6_BLENDFUNCTION_ADD; + case PIPE_BLEND_SUBTRACT: return GEN6_BLENDFUNCTION_SUBTRACT; + case PIPE_BLEND_REVERSE_SUBTRACT: return GEN6_BLENDFUNCTION_REVERSE_SUBTRACT; + case PIPE_BLEND_MIN: return GEN6_BLENDFUNCTION_MIN; + case PIPE_BLEND_MAX: return GEN6_BLENDFUNCTION_MAX; default: assert(!"unknown blend function"); - return BRW_BLENDFUNCTION_ADD; + return GEN6_BLENDFUNCTION_ADD; }; } @@ -91,28 +91,28 @@ static int gen6_translate_pipe_blendfactor(unsigned blendfactor) { switch (blendfactor) { - case PIPE_BLENDFACTOR_ONE: return BRW_BLENDFACTOR_ONE; - case PIPE_BLENDFACTOR_SRC_COLOR: return BRW_BLENDFACTOR_SRC_COLOR; - case PIPE_BLENDFACTOR_SRC_ALPHA: return BRW_BLENDFACTOR_SRC_ALPHA; - case PIPE_BLENDFACTOR_DST_ALPHA: return BRW_BLENDFACTOR_DST_ALPHA; - case PIPE_BLENDFACTOR_DST_COLOR: return BRW_BLENDFACTOR_DST_COLOR; - case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE: return BRW_BLENDFACTOR_SRC_ALPHA_SATURATE; - case PIPE_BLENDFACTOR_CONST_COLOR: return BRW_BLENDFACTOR_CONST_COLOR; - case PIPE_BLENDFACTOR_CONST_ALPHA: return BRW_BLENDFACTOR_CONST_ALPHA; - case PIPE_BLENDFACTOR_SRC1_COLOR: return BRW_BLENDFACTOR_SRC1_COLOR; - case PIPE_BLENDFACTOR_SRC1_ALPHA: return BRW_BLENDFACTOR_SRC1_ALPHA; - case PIPE_BLENDFACTOR_ZERO: return BRW_BLENDFACTOR_ZERO; - case PIPE_BLENDFACTOR_INV_SRC_COLOR: return BRW_BLENDFACTOR_INV_SRC_COLOR; - case PIPE_BLENDFACTOR_INV_SRC_ALPHA: return BRW_BLENDFACTOR_INV_SRC_ALPHA; - case PIPE_BLENDFACTOR_INV_DST_ALPHA: return BRW_BLENDFACTOR_INV_DST_ALPHA; - case PIPE_BLENDFACTOR_INV_DST_COLOR: return BRW_BLENDFACTOR_INV_DST_COLOR; - case PIPE_BLENDFACTOR_INV_CONST_COLOR: return BRW_BLENDFACTOR_INV_CONST_COLOR; - case PIPE_BLENDFACTOR_INV_CONST_ALPHA: return BRW_BLENDFACTOR_INV_CONST_ALPHA; - case PIPE_BLENDFACTOR_INV_SRC1_COLOR: return BRW_BLENDFACTOR_INV_SRC1_COLOR; - case PIPE_BLENDFACTOR_INV_SRC1_ALPHA: return BRW_BLENDFACTOR_INV_SRC1_ALPHA; + case PIPE_BLENDFACTOR_ONE: return GEN6_BLENDFACTOR_ONE; + case PIPE_BLENDFACTOR_SRC_COLOR: return GEN6_BLENDFACTOR_SRC_COLOR; + case PIPE_BLENDFACTOR_SRC_ALPHA: return GEN6_BLENDFACTOR_SRC_ALPHA; + case PIPE_BLENDFACTOR_DST_ALPHA: return GEN6_BLENDFACTOR_DST_ALPHA; + case PIPE_BLENDFACTOR_DST_COLOR: return GEN6_BLENDFACTOR_DST_COLOR; + case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE: return GEN6_BLENDFACTOR_SRC_ALPHA_SATURATE; + case PIPE_BLENDFACTOR_CONST_COLOR: return GEN6_BLENDFACTOR_CONST_COLOR; + case PIPE_BLENDFACTOR_CONST_ALPHA: return GEN6_BLENDFACTOR_CONST_ALPHA; + case PIPE_BLENDFACTOR_SRC1_COLOR: return GEN6_BLENDFACTOR_SRC1_COLOR; + case PIPE_BLENDFACTOR_SRC1_ALPHA: return GEN6_BLENDFACTOR_SRC1_ALPHA; + case PIPE_BLENDFACTOR_ZERO: return GEN6_BLENDFACTOR_ZERO; + case PIPE_BLENDFACTOR_INV_SRC_COLOR: return GEN6_BLENDFACTOR_INV_SRC_COLOR; + case PIPE_BLENDFACTOR_INV_SRC_ALPHA: return GEN6_BLENDFACTOR_INV_SRC_ALPHA; + case PIPE_BLENDFACTOR_INV_DST_ALPHA: return GEN6_BLENDFACTOR_INV_DST_ALPHA; + case PIPE_BLENDFACTOR_INV_DST_COLOR: return GEN6_BLENDFACTOR_INV_DST_COLOR; + case PIPE_BLENDFACTOR_INV_CONST_COLOR: return GEN6_BLENDFACTOR_INV_CONST_COLOR; + case PIPE_BLENDFACTOR_INV_CONST_ALPHA: return GEN6_BLENDFACTOR_INV_CONST_ALPHA; + case PIPE_BLENDFACTOR_INV_SRC1_COLOR: return GEN6_BLENDFACTOR_INV_SRC1_COLOR; + case PIPE_BLENDFACTOR_INV_SRC1_ALPHA: return GEN6_BLENDFACTOR_INV_SRC1_ALPHA; default: assert(!"unknown blend factor"); - return BRW_BLENDFACTOR_ONE; + return GEN6_BLENDFACTOR_ONE; }; } @@ -123,17 +123,17 @@ static int gen6_translate_pipe_stencil_op(unsigned stencil_op) { switch (stencil_op) { - case PIPE_STENCIL_OP_KEEP: return BRW_STENCILOP_KEEP; - case PIPE_STENCIL_OP_ZERO: return BRW_STENCILOP_ZERO; - case PIPE_STENCIL_OP_REPLACE: return BRW_STENCILOP_REPLACE; - case PIPE_STENCIL_OP_INCR: return BRW_STENCILOP_INCRSAT; - case PIPE_STENCIL_OP_DECR: return BRW_STENCILOP_DECRSAT; - case PIPE_STENCIL_OP_INCR_WRAP: return BRW_STENCILOP_INCR; - case PIPE_STENCIL_OP_DECR_WRAP: return BRW_STENCILOP_DECR; - case PIPE_STENCIL_OP_INVERT: return BRW_STENCILOP_INVERT; + case PIPE_STENCIL_OP_KEEP: return GEN6_STENCILOP_KEEP; + case PIPE_STENCIL_OP_ZERO: return GEN6_STENCILOP_ZERO; + case PIPE_STENCIL_OP_REPLACE: return GEN6_STENCILOP_REPLACE; + case PIPE_STENCIL_OP_INCR: return GEN6_STENCILOP_INCRSAT; + case PIPE_STENCIL_OP_DECR: return GEN6_STENCILOP_DECRSAT; + case PIPE_STENCIL_OP_INCR_WRAP: return GEN6_STENCILOP_INCR; + case PIPE_STENCIL_OP_DECR_WRAP: return GEN6_STENCILOP_DECR; + case PIPE_STENCIL_OP_INVERT: return GEN6_STENCILOP_INVERT; default: assert(!"unknown stencil op"); - return BRW_STENCILOP_KEEP; + return GEN6_STENCILOP_KEEP; } } @@ -144,12 +144,12 @@ static int gen6_translate_tex_mipfilter(unsigned filter) { switch (filter) { - case PIPE_TEX_MIPFILTER_NEAREST: return BRW_MIPFILTER_NEAREST; - case PIPE_TEX_MIPFILTER_LINEAR: return BRW_MIPFILTER_LINEAR; - case PIPE_TEX_MIPFILTER_NONE: return BRW_MIPFILTER_NONE; + case PIPE_TEX_MIPFILTER_NEAREST: return GEN6_MIPFILTER_NEAREST; + case PIPE_TEX_MIPFILTER_LINEAR: return GEN6_MIPFILTER_LINEAR; + case PIPE_TEX_MIPFILTER_NONE: return GEN6_MIPFILTER_NONE; default: assert(!"unknown mipfilter"); - return BRW_MIPFILTER_NONE; + return GEN6_MIPFILTER_NONE; } } @@ -160,11 +160,11 @@ static int gen6_translate_tex_filter(unsigned filter) { switch (filter) { - case PIPE_TEX_FILTER_NEAREST: return BRW_MAPFILTER_NEAREST; - case PIPE_TEX_FILTER_LINEAR: return BRW_MAPFILTER_LINEAR; + case PIPE_TEX_FILTER_NEAREST: return GEN6_MAPFILTER_NEAREST; + case PIPE_TEX_FILTER_LINEAR: return GEN6_MAPFILTER_LINEAR; default: assert(!"unknown sampler filter"); - return BRW_MAPFILTER_NEAREST; + return GEN6_MAPFILTER_NEAREST; } } @@ -182,17 +182,17 @@ gen6_translate_tex_wrap(unsigned wrap, bool clamp_to_edge) } switch (wrap) { - case PIPE_TEX_WRAP_REPEAT: return BRW_TEXCOORDMODE_WRAP; - case PIPE_TEX_WRAP_CLAMP_TO_EDGE: return BRW_TEXCOORDMODE_CLAMP; - case PIPE_TEX_WRAP_CLAMP_TO_BORDER: return BRW_TEXCOORDMODE_CLAMP_BORDER; - case PIPE_TEX_WRAP_MIRROR_REPEAT: return BRW_TEXCOORDMODE_MIRROR; + case PIPE_TEX_WRAP_REPEAT: return GEN6_TEXCOORDMODE_WRAP; + case PIPE_TEX_WRAP_CLAMP_TO_EDGE: return GEN6_TEXCOORDMODE_CLAMP; + case PIPE_TEX_WRAP_CLAMP_TO_BORDER: return GEN6_TEXCOORDMODE_CLAMP_BORDER; + case PIPE_TEX_WRAP_MIRROR_REPEAT: return GEN6_TEXCOORDMODE_MIRROR; case PIPE_TEX_WRAP_CLAMP: case PIPE_TEX_WRAP_MIRROR_CLAMP: case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE: case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER: default: assert(!"unknown sampler wrap mode"); - return BRW_TEXCOORDMODE_WRAP; + return GEN6_TEXCOORDMODE_WRAP; } } @@ -207,21 +207,21 @@ gen6_translate_shadow_func(unsigned func) * For PIPE_FUNC_x, the reference value is on the left-hand side of the * comparison, and 1.0 is returned when the comparison is true. * - * For BRW_PREFILTER_x, the reference value is on the right-hand side of + * For GEN6_COMPAREFUNCTION_x, the reference value is on the right-hand side of * the comparison, and 0.0 is returned when the comparison is true. */ switch (func) { - case PIPE_FUNC_NEVER: return BRW_PREFILTER_ALWAYS; - case PIPE_FUNC_LESS: return BRW_PREFILTER_LEQUAL; - case PIPE_FUNC_EQUAL: return BRW_PREFILTER_NOTEQUAL; - case PIPE_FUNC_LEQUAL: return BRW_PREFILTER_LESS; - case PIPE_FUNC_GREATER: return BRW_PREFILTER_GEQUAL; - case PIPE_FUNC_NOTEQUAL: return BRW_PREFILTER_EQUAL; - case PIPE_FUNC_GEQUAL: return BRW_PREFILTER_GREATER; - case PIPE_FUNC_ALWAYS: return BRW_PREFILTER_NEVER; + case PIPE_FUNC_NEVER: return GEN6_COMPAREFUNCTION_ALWAYS; + case PIPE_FUNC_LESS: return GEN6_COMPAREFUNCTION_LEQUAL; + case PIPE_FUNC_EQUAL: return GEN6_COMPAREFUNCTION_NOTEQUAL; + case PIPE_FUNC_LEQUAL: return GEN6_COMPAREFUNCTION_LESS; + case PIPE_FUNC_GREATER: return GEN6_COMPAREFUNCTION_GEQUAL; + case PIPE_FUNC_NOTEQUAL: return GEN6_COMPAREFUNCTION_EQUAL; + case PIPE_FUNC_GEQUAL: return GEN6_COMPAREFUNCTION_GREATER; + case PIPE_FUNC_ALWAYS: return GEN6_COMPAREFUNCTION_NEVER; default: assert(!"unknown shadow compare function"); - return BRW_PREFILTER_NEVER; + return GEN6_COMPAREFUNCTION_NEVER; } } @@ -233,17 +233,17 @@ static int gen6_translate_dsa_func(unsigned func) { switch (func) { - case PIPE_FUNC_NEVER: return BRW_COMPAREFUNCTION_NEVER; - case PIPE_FUNC_LESS: return BRW_COMPAREFUNCTION_LESS; - case PIPE_FUNC_EQUAL: return BRW_COMPAREFUNCTION_EQUAL; - case PIPE_FUNC_LEQUAL: return BRW_COMPAREFUNCTION_LEQUAL; - case PIPE_FUNC_GREATER: return BRW_COMPAREFUNCTION_GREATER; - case PIPE_FUNC_NOTEQUAL: return BRW_COMPAREFUNCTION_NOTEQUAL; - case PIPE_FUNC_GEQUAL: return BRW_COMPAREFUNCTION_GEQUAL; - case PIPE_FUNC_ALWAYS: return BRW_COMPAREFUNCTION_ALWAYS; + case PIPE_FUNC_NEVER: return GEN6_COMPAREFUNCTION_NEVER; + case PIPE_FUNC_LESS: return GEN6_COMPAREFUNCTION_LESS; + case PIPE_FUNC_EQUAL: return GEN6_COMPAREFUNCTION_EQUAL; + case PIPE_FUNC_LEQUAL: return GEN6_COMPAREFUNCTION_LEQUAL; + case PIPE_FUNC_GREATER: return GEN6_COMPAREFUNCTION_GREATER; + case PIPE_FUNC_NOTEQUAL: return GEN6_COMPAREFUNCTION_NOTEQUAL; + case PIPE_FUNC_GEQUAL: return GEN6_COMPAREFUNCTION_GEQUAL; + case PIPE_FUNC_ALWAYS: return GEN6_COMPAREFUNCTION_ALWAYS; default: assert(!"unknown depth/stencil/alpha test function"); - return BRW_COMPAREFUNCTION_NEVER; + return GEN6_COMPAREFUNCTION_NEVER; } } @@ -254,37 +254,37 @@ ve_init_cso(const struct ilo_dev_info *dev, struct ilo_ve_cso *cso) { int comp[4] = { - BRW_VE1_COMPONENT_STORE_SRC, - BRW_VE1_COMPONENT_STORE_SRC, - BRW_VE1_COMPONENT_STORE_SRC, - BRW_VE1_COMPONENT_STORE_SRC, + GEN6_VFCOMP_STORE_SRC, + GEN6_VFCOMP_STORE_SRC, + GEN6_VFCOMP_STORE_SRC, + GEN6_VFCOMP_STORE_SRC, }; int format; ILO_GPE_VALID_GEN(dev, 6, 7.5); switch (util_format_get_nr_components(state->src_format)) { - case 1: comp[1] = BRW_VE1_COMPONENT_STORE_0; - case 2: comp[2] = BRW_VE1_COMPONENT_STORE_0; + case 1: comp[1] = GEN6_VFCOMP_STORE_0; + case 2: comp[2] = GEN6_VFCOMP_STORE_0; case 3: comp[3] = (util_format_is_pure_integer(state->src_format)) ? - BRW_VE1_COMPONENT_STORE_1_INT : - BRW_VE1_COMPONENT_STORE_1_FLT; + GEN6_VFCOMP_STORE_1_INT : + GEN6_VFCOMP_STORE_1_FP; } format = ilo_translate_vertex_format(state->src_format); STATIC_ASSERT(Elements(cso->payload) >= 2); cso->payload[0] = - vb_index << GEN6_VE0_INDEX_SHIFT | - GEN6_VE0_VALID | - format << BRW_VE0_FORMAT_SHIFT | - state->src_offset << BRW_VE0_SRC_OFFSET_SHIFT; + vb_index << GEN6_VE_STATE_DW0_VB_INDEX__SHIFT | + GEN6_VE_STATE_DW0_VALID | + format << GEN6_VE_STATE_DW0_FORMAT__SHIFT | + state->src_offset << GEN6_VE_STATE_DW0_VB_OFFSET__SHIFT; cso->payload[1] = - comp[0] << BRW_VE1_COMPONENT_0_SHIFT | - comp[1] << BRW_VE1_COMPONENT_1_SHIFT | - comp[2] << BRW_VE1_COMPONENT_2_SHIFT | - comp[3] << BRW_VE1_COMPONENT_3_SHIFT; + comp[0] << GEN6_VE_STATE_DW1_COMP0__SHIFT | + comp[1] << GEN6_VE_STATE_DW1_COMP1__SHIFT | + comp[2] << GEN6_VE_STATE_DW1_COMP2__SHIFT | + comp[3] << GEN6_VE_STATE_DW1_COMP3__SHIFT; } void @@ -384,19 +384,19 @@ ilo_gpe_init_vs_cso(const struct ilo_dev_info *dev, break; } - dw2 = (true) ? 0 : GEN6_VS_FLOATING_POINT_MODE_ALT; + dw2 = (true) ? 0 : GEN6_THREADDISP_FP_MODE_ALT; - dw4 = start_grf << GEN6_VS_DISPATCH_START_GRF_SHIFT | - vue_read_len << GEN6_VS_URB_READ_LENGTH_SHIFT | - 0 << GEN6_VS_URB_ENTRY_READ_OFFSET_SHIFT; + dw4 = start_grf << GEN6_VS_DW4_URB_GRF_START__SHIFT | + vue_read_len << GEN6_VS_DW4_URB_READ_LEN__SHIFT | + 0 << GEN6_VS_DW4_URB_READ_OFFSET__SHIFT; - dw5 = GEN6_VS_STATISTICS_ENABLE | - GEN6_VS_ENABLE; + dw5 = GEN6_VS_DW5_STATISTICS | + GEN6_VS_DW5_VS_ENABLE; if (dev->gen >= ILO_GEN(7.5)) - dw5 |= (max_threads - 1) << HSW_VS_MAX_THREADS_SHIFT; + dw5 |= (max_threads - 1) << GEN75_VS_DW5_MAX_THREADS__SHIFT; else - dw5 |= (max_threads - 1) << GEN6_VS_MAX_THREADS_SHIFT; + dw5 |= (max_threads - 1) << GEN6_VS_DW5_MAX_THREADS__SHIFT; STATIC_ASSERT(Elements(cso->payload) >= 3); cso->payload[0] = dw2; @@ -466,16 +466,16 @@ ilo_gpe_init_gs_cso_gen6(const struct ilo_dev_info *dev, max_threads = 21; } - dw2 = GEN6_GS_SPF_MODE; + dw2 = GEN6_THREADDISP_SPF; - dw4 = vue_read_len << GEN6_GS_URB_READ_LENGTH_SHIFT | - 0 << GEN6_GS_URB_ENTRY_READ_OFFSET_SHIFT | - start_grf << GEN6_GS_DISPATCH_START_GRF_SHIFT; + dw4 = vue_read_len << GEN6_GS_DW4_URB_READ_LEN__SHIFT | + 0 << GEN6_GS_DW4_URB_READ_OFFSET__SHIFT | + start_grf << GEN6_GS_DW4_URB_GRF_START__SHIFT; - dw5 = (max_threads - 1) << GEN6_GS_MAX_THREADS_SHIFT | - GEN6_GS_STATISTICS_ENABLE | - GEN6_GS_SO_STATISTICS_ENABLE | - GEN6_GS_RENDERING_ENABLE; + dw5 = (max_threads - 1) << GEN6_GS_DW5_MAX_THREADS__SHIFT | + GEN6_GS_DW5_STATISTICS | + GEN6_GS_DW5_SO_STATISTICS | + GEN6_GS_DW5_RENDER_ENABLE; /* * we cannot make use of GEN6_GS_REORDER because it will reorder @@ -483,19 +483,19 @@ ilo_gpe_init_gs_cso_gen6(const struct ilo_dev_info *dev, * (2N+1, 2N+3, 2N+2)), instead of GL rules (triangle 2N+1 uses vertices * (2N+2, 2N+1, 2N+3)). */ - dw6 = GEN6_GS_ENABLE; + dw6 = GEN6_GS_DW6_GS_ENABLE; if (ilo_shader_get_kernel_param(gs, ILO_KERNEL_GS_DISCARD_ADJACENCY)) - dw6 |= GEN6_GS_DISCARD_ADJACENCY; + dw6 |= GEN6_GS_DW6_DISCARD_ADJACENCY; if (ilo_shader_get_kernel_param(gs, ILO_KERNEL_VS_GEN6_SO)) { const uint32_t svbi_post_inc = ilo_shader_get_kernel_param(gs, ILO_KERNEL_GS_GEN6_SVBI_POST_INC); - dw6 |= GEN6_GS_SVBI_PAYLOAD_ENABLE; + dw6 |= GEN6_GS_DW6_SVBI_PAYLOAD_ENABLE; if (svbi_post_inc) { - dw6 |= GEN6_GS_SVBI_POSTINCREMENT_ENABLE | - svbi_post_inc << GEN6_GS_SVBI_POSTINCREMENT_VALUE_SHIFT; + dw6 |= GEN6_GS_DW6_SVBI_POST_INC_ENABLE | + svbi_post_inc << GEN6_GS_DW6_SVBI_POST_INC_VAL__SHIFT; } } @@ -515,7 +515,7 @@ ilo_gpe_init_rasterizer_clip(const struct ilo_dev_info *dev, ILO_GPE_VALID_GEN(dev, 6, 7.5); - dw1 = GEN6_CLIP_STATISTICS_ENABLE; + dw1 = GEN6_CLIP_DW1_STATISTICS; if (dev->gen >= ILO_GEN(7)) { /* @@ -528,53 +528,53 @@ ilo_gpe_init_rasterizer_clip(const struct ilo_dev_info *dev, * What does this mean? */ dw1 |= 0 << 19 | - GEN7_CLIP_EARLY_CULL; + GEN7_CLIP_DW1_EARLY_CULL_ENABLE; if (state->front_ccw) - dw1 |= GEN7_CLIP_WINDING_CCW; + dw1 |= GEN7_CLIP_DW1_FRONTWINDING_CCW; switch (state->cull_face) { case PIPE_FACE_NONE: - dw1 |= GEN7_CLIP_CULLMODE_NONE; + dw1 |= GEN7_CLIP_DW1_CULLMODE_NONE; break; case PIPE_FACE_FRONT: - dw1 |= GEN7_CLIP_CULLMODE_FRONT; + dw1 |= GEN7_CLIP_DW1_CULLMODE_FRONT; break; case PIPE_FACE_BACK: - dw1 |= GEN7_CLIP_CULLMODE_BACK; + dw1 |= GEN7_CLIP_DW1_CULLMODE_BACK; break; case PIPE_FACE_FRONT_AND_BACK: - dw1 |= GEN7_CLIP_CULLMODE_BOTH; + dw1 |= GEN7_CLIP_DW1_CULLMODE_BOTH; break; } } - dw2 = GEN6_CLIP_ENABLE | - GEN6_CLIP_XY_TEST | - state->clip_plane_enable << GEN6_USER_CLIP_CLIP_DISTANCES_SHIFT | - GEN6_CLIP_MODE_NORMAL; + dw2 = GEN6_CLIP_DW2_CLIP_ENABLE | + GEN6_CLIP_DW2_XY_TEST_ENABLE | + state->clip_plane_enable << GEN6_CLIP_DW2_UCP_CLIP_ENABLES__SHIFT | + GEN6_CLIP_DW2_CLIPMODE_NORMAL; if (state->clip_halfz) - dw2 |= GEN6_CLIP_API_D3D; + dw2 |= GEN6_CLIP_DW2_APIMODE_D3D; else - dw2 |= GEN6_CLIP_API_OGL; + dw2 |= GEN6_CLIP_DW2_APIMODE_OGL; if (state->depth_clip) - dw2 |= GEN6_CLIP_Z_TEST; + dw2 |= GEN6_CLIP_DW2_Z_TEST_ENABLE; if (state->flatshade_first) { - dw2 |= 0 << GEN6_CLIP_TRI_PROVOKE_SHIFT | - 0 << GEN6_CLIP_LINE_PROVOKE_SHIFT | - 1 << GEN6_CLIP_TRIFAN_PROVOKE_SHIFT; + dw2 |= 0 << GEN6_CLIP_DW2_TRI_PROVOKE__SHIFT | + 0 << GEN6_CLIP_DW2_LINE_PROVOKE__SHIFT | + 1 << GEN6_CLIP_DW2_TRIFAN_PROVOKE__SHIFT; } else { - dw2 |= 2 << GEN6_CLIP_TRI_PROVOKE_SHIFT | - 1 << GEN6_CLIP_LINE_PROVOKE_SHIFT | - 2 << GEN6_CLIP_TRIFAN_PROVOKE_SHIFT; + dw2 |= 2 << GEN6_CLIP_DW2_TRI_PROVOKE__SHIFT | + 1 << GEN6_CLIP_DW2_LINE_PROVOKE__SHIFT | + 2 << GEN6_CLIP_DW2_TRIFAN_PROVOKE__SHIFT; } - dw3 = 0x1 << GEN6_CLIP_MIN_POINT_WIDTH_SHIFT | - 0x7ff << GEN6_CLIP_MAX_POINT_WIDTH_SHIFT; + dw3 = 0x1 << GEN6_CLIP_DW3_MIN_POINT_WIDTH__SHIFT | + 0x7ff << GEN6_CLIP_DW3_MAX_POINT_WIDTH__SHIFT; clip->payload[0] = dw1; clip->payload[1] = dw2; @@ -622,8 +622,8 @@ ilo_gpe_init_rasterizer_sf(const struct ilo_dev_info *dev, * should be cleared if clipping is disabled or Statistics Enable in * CLIP_STATE is clear." */ - dw1 = GEN6_SF_STATISTICS_ENABLE | - GEN6_SF_VIEWPORT_TRANSFORM_ENABLE; + dw1 = GEN7_SF_DW1_STATISTICS | + GEN7_SF_DW1_VIEWPORT_ENABLE; /* XXX GEN6 path seems to work fine for GEN7 */ if (false && dev->gen >= ILO_GEN(7)) { @@ -638,11 +638,11 @@ ilo_gpe_init_rasterizer_sf(const struct ilo_dev_info *dev, */ if (state->offset_tri || state->offset_line || state->offset_point) { /* XXX need to scale offset_const according to the depth format */ - dw1 |= GEN6_SF_LEGACY_GLOBAL_DEPTH_BIAS; + dw1 |= GEN7_SF_DW1_LEGACY_DEPTH_OFFSET; - dw1 |= GEN6_SF_GLOBAL_DEPTH_OFFSET_SOLID | - GEN6_SF_GLOBAL_DEPTH_OFFSET_WIREFRAME | - GEN6_SF_GLOBAL_DEPTH_OFFSET_POINT; + dw1 |= GEN7_SF_DW1_DEPTH_OFFSET_SOLID | + GEN7_SF_DW1_DEPTH_OFFSET_WIREFRAME | + GEN7_SF_DW1_DEPTH_OFFSET_POINT; } else { offset_const = 0.0f; @@ -652,39 +652,39 @@ ilo_gpe_init_rasterizer_sf(const struct ilo_dev_info *dev, } else { if (state->offset_tri) - dw1 |= GEN6_SF_GLOBAL_DEPTH_OFFSET_SOLID; + dw1 |= GEN7_SF_DW1_DEPTH_OFFSET_SOLID; if (state->offset_line) - dw1 |= GEN6_SF_GLOBAL_DEPTH_OFFSET_WIREFRAME; + dw1 |= GEN7_SF_DW1_DEPTH_OFFSET_WIREFRAME; if (state->offset_point) - dw1 |= GEN6_SF_GLOBAL_DEPTH_OFFSET_POINT; + dw1 |= GEN7_SF_DW1_DEPTH_OFFSET_POINT; } switch (state->fill_front) { case PIPE_POLYGON_MODE_FILL: - dw1 |= GEN6_SF_FRONT_SOLID; + dw1 |= GEN7_SF_DW1_FRONTFACE_SOLID; break; case PIPE_POLYGON_MODE_LINE: - dw1 |= GEN6_SF_FRONT_WIREFRAME; + dw1 |= GEN7_SF_DW1_FRONTFACE_WIREFRAME; break; case PIPE_POLYGON_MODE_POINT: - dw1 |= GEN6_SF_FRONT_POINT; + dw1 |= GEN7_SF_DW1_FRONTFACE_POINT; break; } switch (state->fill_back) { case PIPE_POLYGON_MODE_FILL: - dw1 |= GEN6_SF_BACK_SOLID; + dw1 |= GEN7_SF_DW1_BACKFACE_SOLID; break; case PIPE_POLYGON_MODE_LINE: - dw1 |= GEN6_SF_BACK_WIREFRAME; + dw1 |= GEN7_SF_DW1_BACKFACE_WIREFRAME; break; case PIPE_POLYGON_MODE_POINT: - dw1 |= GEN6_SF_BACK_POINT; + dw1 |= GEN7_SF_DW1_BACKFACE_POINT; break; } if (state->front_ccw) - dw1 |= GEN6_SF_WINDING_CCW; + dw1 |= GEN7_SF_DW1_FRONTWINDING_CCW; dw2 = 0; @@ -702,22 +702,22 @@ ilo_gpe_init_rasterizer_sf(const struct ilo_dev_info *dev, * * TODO We do not check those yet. */ - dw2 |= GEN6_SF_LINE_AA_ENABLE | - GEN6_SF_LINE_END_CAP_WIDTH_1_0; + dw2 |= GEN7_SF_DW2_AA_LINE_ENABLE | + GEN7_SF_DW2_AA_LINE_CAP_1_0; } switch (state->cull_face) { case PIPE_FACE_NONE: - dw2 |= GEN6_SF_CULL_NONE; + dw2 |= GEN7_SF_DW2_CULLMODE_NONE; break; case PIPE_FACE_FRONT: - dw2 |= GEN6_SF_CULL_FRONT; + dw2 |= GEN7_SF_DW2_CULLMODE_FRONT; break; case PIPE_FACE_BACK: - dw2 |= GEN6_SF_CULL_BACK; + dw2 |= GEN7_SF_DW2_CULLMODE_BACK; break; case PIPE_FACE_FRONT_AND_BACK: - dw2 |= GEN6_SF_CULL_BOTH; + dw2 |= GEN7_SF_DW2_CULLMODE_BOTH; break; } @@ -738,33 +738,33 @@ ilo_gpe_init_rasterizer_sf(const struct ilo_dev_info *dev, line_width = 0; } - dw2 |= line_width << GEN6_SF_LINE_WIDTH_SHIFT; + dw2 |= line_width << GEN7_SF_DW2_LINE_WIDTH__SHIFT; if (dev->gen >= ILO_GEN(7.5) && state->line_stipple_enable) - dw2 |= HSW_SF_LINE_STIPPLE_ENABLE; + dw2 |= GEN75_SF_DW2_LINE_STIPPLE_ENABLE; if (state->scissor) - dw2 |= GEN6_SF_SCISSOR_ENABLE; + dw2 |= GEN7_SF_DW2_SCISSOR_ENABLE; - dw3 = GEN6_SF_LINE_AA_MODE_TRUE | - GEN6_SF_VERTEX_SUBPIXEL_8BITS; + dw3 = GEN7_SF_DW3_TRUE_AA_LINE_DISTANCE | + GEN7_SF_DW3_SUBPIXEL_8BITS; if (state->line_last_pixel) dw3 |= 1 << 31; if (state->flatshade_first) { - dw3 |= 0 << GEN6_SF_TRI_PROVOKE_SHIFT | - 0 << GEN6_SF_LINE_PROVOKE_SHIFT | - 1 << GEN6_SF_TRIFAN_PROVOKE_SHIFT; + dw3 |= 0 << GEN7_SF_DW3_TRI_PROVOKE__SHIFT | + 0 << GEN7_SF_DW3_LINE_PROVOKE__SHIFT | + 1 << GEN7_SF_DW3_TRIFAN_PROVOKE__SHIFT; } else { - dw3 |= 2 << GEN6_SF_TRI_PROVOKE_SHIFT | - 1 << GEN6_SF_LINE_PROVOKE_SHIFT | - 2 << GEN6_SF_TRIFAN_PROVOKE_SHIFT; + dw3 |= 2 << GEN7_SF_DW3_TRI_PROVOKE__SHIFT | + 1 << GEN7_SF_DW3_LINE_PROVOKE__SHIFT | + 2 << GEN7_SF_DW3_TRIFAN_PROVOKE__SHIFT; } if (!state->point_size_per_vertex) - dw3 |= GEN6_SF_USE_STATE_POINT_WIDTH; + dw3 |= GEN7_SF_DW3_USE_POINT_WIDTH; /* in U8.3 */ point_width = (int) (state->point_size * 8.0f + 0.5f); @@ -781,7 +781,7 @@ ilo_gpe_init_rasterizer_sf(const struct ilo_dev_info *dev, sf->payload[5] = fui(offset_clamp); if (state->multisample) { - sf->dw_msaa = GEN6_SF_MSRAST_ON_PATTERN; + sf->dw_msaa = GEN7_SF_DW2_MSRASTMODE_ON_PATTERN; /* * From the Sandy Bridge PRM, volume 2 part 1, page 251: @@ -793,7 +793,7 @@ ilo_gpe_init_rasterizer_sf(const struct ilo_dev_info *dev, if (!line_width) { line_width = 128; /* 1.0f */ - sf->dw_msaa |= line_width << GEN6_SF_LINE_WIDTH_SHIFT; + sf->dw_msaa |= line_width << GEN7_SF_DW2_LINE_WIDTH__SHIFT; } } else { @@ -812,23 +812,23 @@ ilo_gpe_init_rasterizer_wm_gen6(const struct ilo_dev_info *dev, /* only the FF unit states are set, as in GEN7 */ - dw5 = GEN6_WM_LINE_AA_WIDTH_2_0; + dw5 = GEN6_WM_DW5_AA_LINE_WIDTH_2_0; /* same value as in 3DSTATE_SF */ if (state->line_smooth) - dw5 |= GEN6_WM_LINE_END_CAP_AA_WIDTH_1_0; + dw5 |= GEN6_WM_DW5_AA_LINE_CAP_1_0; if (state->poly_stipple_enable) - dw5 |= GEN6_WM_POLYGON_STIPPLE_ENABLE; + dw5 |= GEN6_WM_DW5_POLY_STIPPLE_ENABLE; if (state->line_stipple_enable) - dw5 |= GEN6_WM_LINE_STIPPLE_ENABLE; + dw5 |= GEN6_WM_DW5_LINE_STIPPLE_ENABLE; - dw6 = GEN6_WM_POSITION_ZW_PIXEL | - GEN6_WM_MSRAST_OFF_PIXEL | - GEN6_WM_MSDISPMODE_PERSAMPLE; + dw6 = GEN6_WM_DW6_ZW_INTERP_PIXEL | + GEN6_WM_DW6_MSRASTMODE_OFF_PIXEL | + GEN6_WM_DW6_MSDISPMODE_PERSAMPLE; if (state->bottom_edge_rule) - dw6 |= GEN6_WM_POINT_RASTRULE_UPPER_RIGHT; + dw6 |= GEN6_WM_DW6_POINT_RASTRULE_UPPER_RIGHT; /* * assertion that makes sure @@ -837,12 +837,12 @@ ilo_gpe_init_rasterizer_wm_gen6(const struct ilo_dev_info *dev, * * is valid */ - STATIC_ASSERT(GEN6_WM_MSRAST_OFF_PIXEL == 0 && - GEN6_WM_MSDISPMODE_PERSAMPLE == 0); + STATIC_ASSERT(GEN6_WM_DW6_MSRASTMODE_OFF_PIXEL == 0 && + GEN6_WM_DW6_MSDISPMODE_PERSAMPLE == 0); wm->dw_msaa_rast = - (state->multisample) ? GEN6_WM_MSRAST_ON_PATTERN : 0; - wm->dw_msaa_disp = GEN6_WM_MSDISPMODE_PERPIXEL; + (state->multisample) ? GEN6_WM_DW6_MSRASTMODE_ON_PATTERN : 0; + wm->dw_msaa_disp = GEN6_WM_DW6_MSDISPMODE_PERPIXEL; STATIC_ASSERT(Elements(wm->payload) >= 2); wm->payload[0] = dw5; @@ -867,13 +867,13 @@ ilo_gpe_init_fs_cso_gen6(const struct ilo_dev_info *dev, /* see brwCreateContext() */ max_threads = (dev->gt == 2) ? 80 : 40; - dw2 = (true) ? 0 : GEN6_WM_FLOATING_POINT_MODE_ALT; + dw2 = (true) ? 0 : GEN6_THREADDISP_FP_MODE_ALT; - dw4 = start_grf << GEN6_WM_DISPATCH_START_GRF_SHIFT_0 | - 0 << GEN6_WM_DISPATCH_START_GRF_SHIFT_1 | - 0 << GEN6_WM_DISPATCH_START_GRF_SHIFT_2; + dw4 = start_grf << GEN6_WM_DW4_URB_GRF_START0__SHIFT | + 0 << GEN6_WM_DW4_URB_GRF_START1__SHIFT | + 0 << GEN6_WM_DW4_URB_GRF_START2__SHIFT; - dw5 = (max_threads - 1) << GEN6_WM_MAX_THREADS_SHIFT; + dw5 = (max_threads - 1) << GEN6_WM_DW5_MAX_THREADS__SHIFT; /* * From the Sandy Bridge PRM, volume 2 part 1, page 275: @@ -901,7 +901,7 @@ ilo_gpe_init_fs_cso_gen6(const struct ilo_dev_info *dev, * ENABLE this bit due to ClipDistance clipping." */ if (ilo_shader_get_kernel_param(fs, ILO_KERNEL_FS_USE_KILL)) - dw5 |= GEN6_WM_KILL_ENABLE; + dw5 |= GEN6_WM_DW5_PS_KILL; /* * From the Sandy Bridge PRM, volume 2 part 1, page 275: @@ -912,13 +912,13 @@ ilo_gpe_init_fs_cso_gen6(const struct ilo_dev_info *dev, * TODO This is not checked yet. */ if (ilo_shader_get_kernel_param(fs, ILO_KERNEL_FS_OUTPUT_Z)) - dw5 |= GEN6_WM_COMPUTED_DEPTH; + dw5 |= GEN6_WM_DW5_PS_COMPUTE_DEPTH; if (ilo_shader_get_kernel_param(fs, ILO_KERNEL_FS_INPUT_Z)) - dw5 |= GEN6_WM_USES_SOURCE_DEPTH; + dw5 |= GEN6_WM_DW5_PS_USE_DEPTH; if (ilo_shader_get_kernel_param(fs, ILO_KERNEL_FS_INPUT_W)) - dw5 |= GEN6_WM_USES_SOURCE_W; + dw5 |= GEN6_WM_DW5_PS_USE_W; /* * TODO set this bit only when @@ -928,14 +928,14 @@ ilo_gpe_init_fs_cso_gen6(const struct ilo_dev_info *dev, * c) fs or cc kills */ if (true) - dw5 |= GEN6_WM_DISPATCH_ENABLE; + dw5 |= GEN6_WM_DW5_PS_ENABLE; assert(!ilo_shader_get_kernel_param(fs, ILO_KERNEL_FS_DISPATCH_16_OFFSET)); - dw5 |= GEN6_WM_8_DISPATCH_ENABLE; + dw5 |= GEN6_WM_DW5_8_PIXEL_DISPATCH; - dw6 = input_count << GEN6_WM_NUM_SF_OUTPUTS_SHIFT | - GEN6_WM_POSOFFSET_NONE | - interps << GEN6_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT; + dw6 = input_count << GEN6_WM_DW6_SF_ATTR_COUNT__SHIFT | + GEN6_WM_DW6_POSOFFSET_NONE | + interps << GEN6_WM_DW6_BARYCENTRIC_INTERP__SHIFT; STATIC_ASSERT(Elements(cso->payload) >= 4); cso->payload[0] = dw2; @@ -968,8 +968,8 @@ zs_init_info_null(const struct ilo_dev_info *dev, memset(info, 0, sizeof(*info)); - info->surface_type = BRW_SURFACE_NULL; - info->format = BRW_DEPTHFORMAT_D32_FLOAT; + info->surface_type = GEN6_SURFTYPE_NULL; + info->format = GEN6_ZFORMAT_D32_FLOAT; info->width = 1; info->height = 1; info->depth = 1; @@ -992,7 +992,7 @@ zs_init_info(const struct ilo_dev_info *dev, info->surface_type = ilo_gpe_gen6_translate_texture(tex->base.target); - if (info->surface_type == BRW_SURFACE_CUBE) { + if (info->surface_type == GEN6_SURFTYPE_CUBE) { /* * From the Sandy Bridge PRM, volume 2 part 1, page 325-326: * @@ -1005,7 +1005,7 @@ zs_init_info(const struct ilo_dev_info *dev, * As such, we cannot set first_layer and num_layers on cube surfaces. * To work around that, treat it as a 2D surface. */ - info->surface_type = BRW_SURFACE_2D; + info->surface_type = GEN6_SURFTYPE_2D; } if (dev->gen >= ILO_GEN(7)) { @@ -1044,25 +1044,25 @@ zs_init_info(const struct ilo_dev_info *dev, */ switch (format) { case PIPE_FORMAT_Z16_UNORM: - info->format = BRW_DEPTHFORMAT_D16_UNORM; + info->format = GEN6_ZFORMAT_D16_UNORM; break; case PIPE_FORMAT_Z32_FLOAT: - info->format = BRW_DEPTHFORMAT_D32_FLOAT; + info->format = GEN6_ZFORMAT_D32_FLOAT; break; case PIPE_FORMAT_Z24X8_UNORM: case PIPE_FORMAT_Z24_UNORM_S8_UINT: info->format = (separate_stencil) ? - BRW_DEPTHFORMAT_D24_UNORM_X8_UINT : - BRW_DEPTHFORMAT_D24_UNORM_S8_UINT; + GEN6_ZFORMAT_D24_UNORM_X8_UINT : + GEN6_ZFORMAT_D24_UNORM_S8_UINT; break; case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: info->format = (separate_stencil) ? - BRW_DEPTHFORMAT_D32_FLOAT : - BRW_DEPTHFORMAT_D32_FLOAT_S8X24_UINT; + GEN6_ZFORMAT_D32_FLOAT : + GEN6_ZFORMAT_D32_FLOAT_S8X24_UINT; break; case PIPE_FORMAT_S8_UINT: if (separate_stencil) { - info->format = BRW_DEPTHFORMAT_D32_FLOAT; + info->format = GEN6_ZFORMAT_D32_FLOAT; break; } /* fall through */ @@ -1141,7 +1141,7 @@ zs_init_info(const struct ilo_dev_info *dev, /* the size of the layer */ info->width = u_minify(info->width, level); info->height = u_minify(info->height, level); - if (info->surface_type == BRW_SURFACE_3D) + if (info->surface_type == GEN6_SURFTYPE_3D) info->depth = u_minify(info->depth, level); else info->depth = 1; @@ -1194,14 +1194,14 @@ zs_init_info(const struct ilo_dev_info *dev, info->height += info->y_offset; /* we have to treat them as 2D surfaces */ - if (info->surface_type == BRW_SURFACE_CUBE) { + if (info->surface_type == GEN6_SURFTYPE_CUBE) { assert(tex->base.width0 == tex->base.height0); /* we will set slice_offset to point to the single face */ - info->surface_type = BRW_SURFACE_2D; + info->surface_type = GEN6_SURFTYPE_2D; } - else if (info->surface_type == BRW_SURFACE_1D && info->height > 1) { + else if (info->surface_type == GEN6_SURFTYPE_1D && info->height > 1) { assert(tex->base.height0 == 1); - info->surface_type = BRW_SURFACE_2D; + info->surface_type = GEN6_SURFTYPE_2D; } } } @@ -1229,26 +1229,26 @@ ilo_gpe_init_zs_surface(const struct ilo_dev_info *dev, } switch (info.surface_type) { - case BRW_SURFACE_NULL: + case GEN6_SURFTYPE_NULL: break; - case BRW_SURFACE_1D: + case GEN6_SURFTYPE_1D: assert(info.width <= max_2d_size && info.height == 1 && info.depth <= max_array_size); assert(info.first_layer < max_array_size - 1 && info.num_layers <= max_array_size); break; - case BRW_SURFACE_2D: + case GEN6_SURFTYPE_2D: assert(info.width <= max_2d_size && info.height <= max_2d_size && info.depth <= max_array_size); assert(info.first_layer < max_array_size - 1 && info.num_layers <= max_array_size); break; - case BRW_SURFACE_3D: + case GEN6_SURFTYPE_3D: assert(info.width <= 2048 && info.height <= 2048 && info.depth <= 2048); assert(info.first_layer < 2048 && info.num_layers <= max_array_size); assert(info.x_offset == 0 && info.y_offset == 0); break; - case BRW_SURFACE_CUBE: + case GEN6_SURFTYPE_CUBE: assert(info.width <= max_2d_size && info.height <= max_2d_size && info.depth == 1); assert(info.first_layer == 0 && info.num_layers == 1); @@ -1311,7 +1311,7 @@ ilo_gpe_init_zs_surface(const struct ilo_dev_info *dev, dw3 = (info.height - 1) << 19 | (info.width - 1) << 6 | info.lod << 2 | - BRW_SURFACE_MIPMAPLAYOUT_BELOW << 1; + GEN6_DEPTH_DW3_MIPLAYOUT_BELOW; dw4 = (info.depth - 1) << 21 | info.first_layer << 10 | @@ -1343,7 +1343,7 @@ ilo_gpe_init_zs_surface(const struct ilo_dev_info *dev, zs->payload[7] = info.stencil.offset; if (dev->gen >= ILO_GEN(7.5)) - zs->payload[6] |= HSW_STENCIL_ENABLED; + zs->payload[6] |= GEN75_STENCIL_DW1_STENCIL_BUFFER_ENABLE; /* do not increment reference count */ zs->separate_s8_bo = info.stencil.bo; @@ -1472,11 +1472,11 @@ static int gen6_blend_factor_dst_alpha_forced_one(int factor) { switch (factor) { - case BRW_BLENDFACTOR_DST_ALPHA: - return BRW_BLENDFACTOR_ONE; - case BRW_BLENDFACTOR_INV_DST_ALPHA: - case BRW_BLENDFACTOR_SRC_ALPHA_SATURATE: - return BRW_BLENDFACTOR_ZERO; + case GEN6_BLENDFACTOR_DST_ALPHA: + return GEN6_BLENDFACTOR_ONE; + case GEN6_BLENDFACTOR_INV_DST_ALPHA: + case GEN6_BLENDFACTOR_SRC_ALPHA_SATURATE: + return GEN6_BLENDFACTOR_ZERO; default: return factor; } @@ -1547,7 +1547,7 @@ ilo_gpe_init_blend(const struct ilo_dev_info *dev, bool dual_blend; cso->payload[0] = 0; - cso->payload[1] = BRW_RENDERTARGET_CLAMPRANGE_FORMAT << 2 | + cso->payload[1] = GEN6_BLEND_DW1_COLORCLAMP_RTFORMAT | 0x3; if (!(rt->colormask & PIPE_MASK_A)) @@ -1692,7 +1692,7 @@ ilo_gpe_init_dsa(const struct ilo_dev_info *dev, if (depth->enabled) dw[2] |= gen6_translate_dsa_func(depth->func) << 27; else - dw[2] |= BRW_COMPAREFUNCTION_ALWAYS << 27; + dw[2] |= GEN6_COMPAREFUNCTION_ALWAYS << 27; /* dw_alpha will be ORed to BLEND_STATE */ if (alpha->enabled) { @@ -1792,17 +1792,17 @@ ilo_gpe_init_view_surface_null_gen6(const struct ilo_dev_info *dev, STATIC_ASSERT(Elements(surf->payload) >= 6); dw = surf->payload; - dw[0] = BRW_SURFACE_NULL << BRW_SURFACE_TYPE_SHIFT | - BRW_SURFACEFORMAT_B8G8R8A8_UNORM << BRW_SURFACE_FORMAT_SHIFT; + dw[0] = GEN6_SURFTYPE_NULL << GEN6_SURFACE_DW0_TYPE__SHIFT | + GEN6_FORMAT_B8G8R8A8_UNORM << GEN6_SURFACE_DW0_FORMAT__SHIFT; dw[1] = 0; - dw[2] = (height - 1) << BRW_SURFACE_HEIGHT_SHIFT | - (width - 1) << BRW_SURFACE_WIDTH_SHIFT | - level << BRW_SURFACE_LOD_SHIFT; + dw[2] = (height - 1) << GEN6_SURFACE_DW2_HEIGHT__SHIFT | + (width - 1) << GEN6_SURFACE_DW2_WIDTH__SHIFT | + level << GEN6_SURFACE_DW2_MIP_COUNT_LOD__SHIFT; - dw[3] = (depth - 1) << BRW_SURFACE_DEPTH_SHIFT | - BRW_SURFACE_TILED; + dw[3] = (depth - 1) << GEN6_SURFACE_DW3_DEPTH__SHIFT | + GEN6_TILING_X; dw[4] = 0; dw[5] = 0; @@ -1884,18 +1884,18 @@ ilo_gpe_init_view_surface_for_buffer_gen6(const struct ilo_dev_info *dev, STATIC_ASSERT(Elements(surf->payload) >= 6); dw = surf->payload; - dw[0] = BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT | - surface_format << BRW_SURFACE_FORMAT_SHIFT; + dw[0] = GEN6_SURFTYPE_BUFFER << GEN6_SURFACE_DW0_TYPE__SHIFT | + surface_format << GEN6_SURFACE_DW0_FORMAT__SHIFT; if (render_cache_rw) - dw[0] |= BRW_SURFACE_RC_READ_WRITE; + dw[0] |= GEN6_SURFACE_DW0_RENDER_CACHE_RW; dw[1] = offset; - dw[2] = height << BRW_SURFACE_HEIGHT_SHIFT | - width << BRW_SURFACE_WIDTH_SHIFT; + dw[2] = height << GEN6_SURFACE_DW2_HEIGHT__SHIFT | + width << GEN6_SURFACE_DW2_WIDTH__SHIFT; - dw[3] = depth << BRW_SURFACE_DEPTH_SHIFT | - pitch << BRW_SURFACE_PITCH_SHIFT; + dw[3] = depth << GEN6_SURFACE_DW3_DEPTH__SHIFT | + pitch << GEN6_SURFACE_DW3_PITCH__SHIFT; dw[4] = 0; dw[5] = 0; @@ -1923,7 +1923,7 @@ ilo_gpe_init_view_surface_for_texture_gen6(const struct ilo_dev_info *dev, ILO_GPE_VALID_GEN(dev, 6, 6); surface_type = ilo_gpe_gen6_translate_texture(tex->base.target); - assert(surface_type != BRW_SURFACE_BUFFER); + assert(surface_type != GEN6_SURFTYPE_BUFFER); if (format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT && tex->separate_s8) format = PIPE_FORMAT_Z32_FLOAT; @@ -1940,7 +1940,7 @@ ilo_gpe_init_view_surface_for_texture_gen6(const struct ilo_dev_info *dev, tex->base.depth0 : num_layers; pitch = tex->bo_stride; - if (surface_type == BRW_SURFACE_CUBE) { + if (surface_type == GEN6_SURFTYPE_CUBE) { /* * From the Sandy Bridge PRM, volume 4 part 1, page 81: * @@ -1954,7 +1954,7 @@ ilo_gpe_init_view_surface_for_texture_gen6(const struct ilo_dev_info *dev, * restriction. */ if (is_rt) { - surface_type = BRW_SURFACE_2D; + surface_type = GEN6_SURFTYPE_2D; } else { assert(num_layers % 6 == 0); @@ -1965,21 +1965,21 @@ ilo_gpe_init_view_surface_for_texture_gen6(const struct ilo_dev_info *dev, /* sanity check the size */ assert(width >= 1 && height >= 1 && depth >= 1 && pitch >= 1); switch (surface_type) { - case BRW_SURFACE_1D: + case GEN6_SURFTYPE_1D: assert(width <= 8192 && height == 1 && depth <= 512); assert(first_layer < 512 && num_layers <= 512); break; - case BRW_SURFACE_2D: + case GEN6_SURFTYPE_2D: assert(width <= 8192 && height <= 8192 && depth <= 512); assert(first_layer < 512 && num_layers <= 512); break; - case BRW_SURFACE_3D: + case GEN6_SURFTYPE_3D: assert(width <= 2048 && height <= 2048 && depth <= 2048); assert(first_layer < 2048 && num_layers <= 512); if (!is_rt) assert(first_layer == 0); break; - case BRW_SURFACE_CUBE: + case GEN6_SURFTYPE_CUBE: assert(width <= 8192 && height <= 8192 && depth <= 85); assert(width == height); assert(first_layer < 512 && num_layers <= 512); @@ -2069,38 +2069,38 @@ ilo_gpe_init_view_surface_for_texture_gen6(const struct ilo_dev_info *dev, STATIC_ASSERT(Elements(surf->payload) >= 6); dw = surf->payload; - dw[0] = surface_type << BRW_SURFACE_TYPE_SHIFT | - surface_format << BRW_SURFACE_FORMAT_SHIFT | - BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT; + dw[0] = surface_type << GEN6_SURFACE_DW0_TYPE__SHIFT | + surface_format << GEN6_SURFACE_DW0_FORMAT__SHIFT | + GEN6_SURFACE_DW0_MIPLAYOUT_BELOW; - if (surface_type == BRW_SURFACE_CUBE && !is_rt) { + if (surface_type == GEN6_SURFTYPE_CUBE && !is_rt) { dw[0] |= 1 << 9 | - BRW_SURFACE_CUBEFACE_ENABLES; + GEN6_SURFACE_DW0_CUBE_FACE_ENABLES__MASK; } if (is_rt) - dw[0] |= BRW_SURFACE_RC_READ_WRITE; + dw[0] |= GEN6_SURFACE_DW0_RENDER_CACHE_RW; dw[1] = layer_offset; - dw[2] = (height - 1) << BRW_SURFACE_HEIGHT_SHIFT | - (width - 1) << BRW_SURFACE_WIDTH_SHIFT | - lod << BRW_SURFACE_LOD_SHIFT; + dw[2] = (height - 1) << GEN6_SURFACE_DW2_HEIGHT__SHIFT | + (width - 1) << GEN6_SURFACE_DW2_WIDTH__SHIFT | + lod << GEN6_SURFACE_DW2_MIP_COUNT_LOD__SHIFT; - dw[3] = (depth - 1) << BRW_SURFACE_DEPTH_SHIFT | - (pitch - 1) << BRW_SURFACE_PITCH_SHIFT | + dw[3] = (depth - 1) << GEN6_SURFACE_DW3_DEPTH__SHIFT | + (pitch - 1) << GEN6_SURFACE_DW3_PITCH__SHIFT | ilo_gpe_gen6_translate_winsys_tiling(tex->tiling); - dw[4] = first_level << BRW_SURFACE_MIN_LOD_SHIFT | + dw[4] = first_level << GEN6_SURFACE_DW4_MIN_LOD__SHIFT | first_layer << 17 | (num_layers - 1) << 8 | - ((tex->base.nr_samples > 1) ? BRW_SURFACE_MULTISAMPLECOUNT_4 : - BRW_SURFACE_MULTISAMPLECOUNT_1); + ((tex->base.nr_samples > 1) ? GEN6_SURFACE_DW4_MULTISAMPLECOUNT_4 : + GEN6_SURFACE_DW4_MULTISAMPLECOUNT_1); - dw[5] = x_offset << BRW_SURFACE_X_OFFSET_SHIFT | - y_offset << BRW_SURFACE_Y_OFFSET_SHIFT; + dw[5] = x_offset << GEN6_SURFACE_DW5_X_OFFSET__SHIFT | + y_offset << GEN6_SURFACE_DW5_Y_OFFSET__SHIFT; if (tex->valign_4) - dw[5] |= BRW_SURFACE_VERTICAL_ALIGN_ENABLE; + dw[5] |= GEN6_SURFACE_DW5_VALIGN_4; /* do not increment reference count */ surf->bo = tex->bo; @@ -2197,9 +2197,9 @@ ilo_gpe_init_sampler_cso(const struct ilo_dev_info *dev, if (state->max_anisotropy >= 2 && state->max_anisotropy <= 16) max_aniso = state->max_anisotropy / 2 - 1; else if (state->max_anisotropy > 16) - max_aniso = BRW_ANISORATIO_16; + max_aniso = GEN6_ANISORATIO_16; else - max_aniso = BRW_ANISORATIO_2; + max_aniso = GEN6_ANISORATIO_2; /* * @@ -2300,10 +2300,10 @@ ilo_gpe_init_sampler_cso(const struct ilo_dev_info *dev, if (state->seamless_cube_map && (state->min_img_filter != PIPE_TEX_FILTER_NEAREST || state->mag_img_filter != PIPE_TEX_FILTER_NEAREST)) { - wrap_cube = BRW_TEXCOORDMODE_CUBE; + wrap_cube = GEN6_TEXCOORDMODE_CUBE; } else { - wrap_cube = BRW_TEXCOORDMODE_CLAMP; + wrap_cube = GEN6_TEXCOORDMODE_CLAMP; } if (!state->normalized_coords) { @@ -2327,22 +2327,22 @@ ilo_gpe_init_sampler_cso(const struct ilo_dev_info *dev, * - Surface Min LOD must be 0. * - Texture LOD Bias must be 0." */ - assert(wrap_s == BRW_TEXCOORDMODE_CLAMP || - wrap_s == BRW_TEXCOORDMODE_CLAMP_BORDER); - assert(wrap_t == BRW_TEXCOORDMODE_CLAMP || - wrap_t == BRW_TEXCOORDMODE_CLAMP_BORDER); - assert(wrap_r == BRW_TEXCOORDMODE_CLAMP || - wrap_r == BRW_TEXCOORDMODE_CLAMP_BORDER); - - assert(mag_filter == BRW_MAPFILTER_NEAREST || - mag_filter == BRW_MAPFILTER_LINEAR); - assert(min_filter == BRW_MAPFILTER_NEAREST || - min_filter == BRW_MAPFILTER_LINEAR); + assert(wrap_s == GEN6_TEXCOORDMODE_CLAMP || + wrap_s == GEN6_TEXCOORDMODE_CLAMP_BORDER); + assert(wrap_t == GEN6_TEXCOORDMODE_CLAMP || + wrap_t == GEN6_TEXCOORDMODE_CLAMP_BORDER); + assert(wrap_r == GEN6_TEXCOORDMODE_CLAMP || + wrap_r == GEN6_TEXCOORDMODE_CLAMP_BORDER); + + assert(mag_filter == GEN6_MAPFILTER_NEAREST || + mag_filter == GEN6_MAPFILTER_LINEAR); + assert(min_filter == GEN6_MAPFILTER_NEAREST || + min_filter == GEN6_MAPFILTER_LINEAR); /* work around a bug in util_blitter */ - mip_filter = BRW_MIPFILTER_NONE; + mip_filter = GEN6_MIPFILTER_NONE; - assert(mip_filter == BRW_MIPFILTER_NONE); + assert(mip_filter == GEN6_MIPFILTER_NONE); } if (dev->gen >= ILO_GEN(7)) { @@ -2353,8 +2353,8 @@ ilo_gpe_init_sampler_cso(const struct ilo_dev_info *dev, sampler->dw_filter = mag_filter << 17 | min_filter << 14; - sampler->dw_filter_aniso = BRW_MAPFILTER_ANISOTROPIC << 17 | - BRW_MAPFILTER_ANISOTROPIC << 14 | + sampler->dw_filter_aniso = GEN6_MAPFILTER_ANISOTROPIC << 17 | + GEN6_MAPFILTER_ANISOTROPIC << 14 | 1; dw1 = min_lod << 20 | @@ -2366,15 +2366,15 @@ ilo_gpe_init_sampler_cso(const struct ilo_dev_info *dev, dw3 = max_aniso << 19; /* round the coordinates for linear filtering */ - if (min_filter != BRW_MAPFILTER_NEAREST) { - dw3 |= (BRW_ADDRESS_ROUNDING_ENABLE_U_MIN | - BRW_ADDRESS_ROUNDING_ENABLE_V_MIN | - BRW_ADDRESS_ROUNDING_ENABLE_R_MIN) << 13; + if (min_filter != GEN6_MAPFILTER_NEAREST) { + dw3 |= (GEN6_SAMPLER_DW3_U_MIN_ROUND | + GEN6_SAMPLER_DW3_V_MIN_ROUND | + GEN6_SAMPLER_DW3_R_MIN_ROUND); } - if (mag_filter != BRW_MAPFILTER_NEAREST) { - dw3 |= (BRW_ADDRESS_ROUNDING_ENABLE_U_MAG | - BRW_ADDRESS_ROUNDING_ENABLE_V_MAG | - BRW_ADDRESS_ROUNDING_ENABLE_R_MAG) << 13; + if (mag_filter != GEN6_MAPFILTER_NEAREST) { + dw3 |= (GEN6_SAMPLER_DW3_U_MAG_ROUND | + GEN6_SAMPLER_DW3_V_MAG_ROUND | + GEN6_SAMPLER_DW3_R_MAG_ROUND); } if (!state->normalized_coords) @@ -2390,8 +2390,8 @@ ilo_gpe_init_sampler_cso(const struct ilo_dev_info *dev, * mode */ sampler->dw_wrap_1d = wrap_s << 6 | - BRW_TEXCOORDMODE_WRAP << 3 | - BRW_TEXCOORDMODE_WRAP; + GEN6_TEXCOORDMODE_WRAP << 3 | + GEN6_TEXCOORDMODE_WRAP; sampler->dw_wrap_cube = wrap_cube << 6 | wrap_cube << 3 | @@ -2418,8 +2418,8 @@ ilo_gpe_init_sampler_cso(const struct ilo_dev_info *dev, mag_filter << 17 | min_filter << 14; - sampler->dw_filter_aniso = BRW_MAPFILTER_ANISOTROPIC << 17 | - BRW_MAPFILTER_ANISOTROPIC << 14; + sampler->dw_filter_aniso = GEN6_MAPFILTER_ANISOTROPIC << 17 | + GEN6_MAPFILTER_ANISOTROPIC << 14; dw1 = min_lod << 22 | max_lod << 12; @@ -2429,8 +2429,8 @@ ilo_gpe_init_sampler_cso(const struct ilo_dev_info *dev, wrap_r; sampler->dw_wrap_1d = wrap_s << 6 | - BRW_TEXCOORDMODE_WRAP << 3 | - BRW_TEXCOORDMODE_WRAP; + GEN6_TEXCOORDMODE_WRAP << 3 | + GEN6_TEXCOORDMODE_WRAP; sampler->dw_wrap_cube = wrap_cube << 6 | wrap_cube << 3 | @@ -2439,15 +2439,15 @@ ilo_gpe_init_sampler_cso(const struct ilo_dev_info *dev, dw3 = max_aniso << 19; /* round the coordinates for linear filtering */ - if (min_filter != BRW_MAPFILTER_NEAREST) { - dw3 |= (BRW_ADDRESS_ROUNDING_ENABLE_U_MIN | - BRW_ADDRESS_ROUNDING_ENABLE_V_MIN | - BRW_ADDRESS_ROUNDING_ENABLE_R_MIN) << 13; + if (min_filter != GEN6_MAPFILTER_NEAREST) { + dw3 |= (GEN6_SAMPLER_DW3_U_MIN_ROUND | + GEN6_SAMPLER_DW3_V_MIN_ROUND | + GEN6_SAMPLER_DW3_R_MIN_ROUND); } - if (mag_filter != BRW_MAPFILTER_NEAREST) { - dw3 |= (BRW_ADDRESS_ROUNDING_ENABLE_U_MAG | - BRW_ADDRESS_ROUNDING_ENABLE_V_MAG | - BRW_ADDRESS_ROUNDING_ENABLE_R_MAG) << 13; + if (mag_filter != GEN6_MAPFILTER_NEAREST) { + dw3 |= (GEN6_SAMPLER_DW3_U_MAG_ROUND | + GEN6_SAMPLER_DW3_V_MAG_ROUND | + GEN6_SAMPLER_DW3_R_MAG_ROUND); } if (!state->normalized_coords) diff --git a/src/gallium/drivers/ilo/ilo_gpe_gen6.h b/src/gallium/drivers/ilo/ilo_gpe_gen6.h index bbcbced4d66..b1219466a0d 100644 --- a/src/gallium/drivers/ilo/ilo_gpe_gen6.h +++ b/src/gallium/drivers/ilo/ilo_gpe_gen6.h @@ -140,9 +140,9 @@ ilo_gpe_gen6_translate_winsys_tiling(enum intel_tiling_mode tiling) case INTEL_TILING_NONE: return 0; case INTEL_TILING_X: - return BRW_SURFACE_TILED; + return GEN6_TILING_X; case INTEL_TILING_Y: - return BRW_SURFACE_TILED | BRW_SURFACE_TILED_Y; + return GEN6_TILING_Y; default: assert(!"unknown tiling"); return 0; @@ -156,20 +156,20 @@ static inline int ilo_gpe_gen6_translate_pipe_prim(unsigned prim) { static const int prim_mapping[PIPE_PRIM_MAX] = { - [PIPE_PRIM_POINTS] = _3DPRIM_POINTLIST, - [PIPE_PRIM_LINES] = _3DPRIM_LINELIST, - [PIPE_PRIM_LINE_LOOP] = _3DPRIM_LINELOOP, - [PIPE_PRIM_LINE_STRIP] = _3DPRIM_LINESTRIP, - [PIPE_PRIM_TRIANGLES] = _3DPRIM_TRILIST, - [PIPE_PRIM_TRIANGLE_STRIP] = _3DPRIM_TRISTRIP, - [PIPE_PRIM_TRIANGLE_FAN] = _3DPRIM_TRIFAN, - [PIPE_PRIM_QUADS] = _3DPRIM_QUADLIST, - [PIPE_PRIM_QUAD_STRIP] = _3DPRIM_QUADSTRIP, - [PIPE_PRIM_POLYGON] = _3DPRIM_POLYGON, - [PIPE_PRIM_LINES_ADJACENCY] = _3DPRIM_LINELIST_ADJ, - [PIPE_PRIM_LINE_STRIP_ADJACENCY] = _3DPRIM_LINESTRIP_ADJ, - [PIPE_PRIM_TRIANGLES_ADJACENCY] = _3DPRIM_TRILIST_ADJ, - [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = _3DPRIM_TRISTRIP_ADJ, + [PIPE_PRIM_POINTS] = GEN6_3DPRIM_POINTLIST, + [PIPE_PRIM_LINES] = GEN6_3DPRIM_LINELIST, + [PIPE_PRIM_LINE_LOOP] = GEN6_3DPRIM_LINELOOP, + [PIPE_PRIM_LINE_STRIP] = GEN6_3DPRIM_LINESTRIP, + [PIPE_PRIM_TRIANGLES] = GEN6_3DPRIM_TRILIST, + [PIPE_PRIM_TRIANGLE_STRIP] = GEN6_3DPRIM_TRISTRIP, + [PIPE_PRIM_TRIANGLE_FAN] = GEN6_3DPRIM_TRIFAN, + [PIPE_PRIM_QUADS] = GEN6_3DPRIM_QUADLIST, + [PIPE_PRIM_QUAD_STRIP] = GEN6_3DPRIM_QUADSTRIP, + [PIPE_PRIM_POLYGON] = GEN6_3DPRIM_POLYGON, + [PIPE_PRIM_LINES_ADJACENCY] = GEN6_3DPRIM_LINELIST_ADJ, + [PIPE_PRIM_LINE_STRIP_ADJACENCY] = GEN6_3DPRIM_LINESTRIP_ADJ, + [PIPE_PRIM_TRIANGLES_ADJACENCY] = GEN6_3DPRIM_TRILIST_ADJ, + [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = GEN6_3DPRIM_TRISTRIP_ADJ, }; assert(prim_mapping[prim]); @@ -185,22 +185,22 @@ ilo_gpe_gen6_translate_texture(enum pipe_texture_target target) { switch (target) { case PIPE_BUFFER: - return BRW_SURFACE_BUFFER; + return GEN6_SURFTYPE_BUFFER; case PIPE_TEXTURE_1D: case PIPE_TEXTURE_1D_ARRAY: - return BRW_SURFACE_1D; + return GEN6_SURFTYPE_1D; case PIPE_TEXTURE_2D: case PIPE_TEXTURE_RECT: case PIPE_TEXTURE_2D_ARRAY: - return BRW_SURFACE_2D; + return GEN6_SURFTYPE_2D; case PIPE_TEXTURE_3D: - return BRW_SURFACE_3D; + return GEN6_SURFTYPE_3D; case PIPE_TEXTURE_CUBE: case PIPE_TEXTURE_CUBE_ARRAY: - return BRW_SURFACE_CUBE; + return GEN6_SURFTYPE_CUBE; default: assert(!"unknown texture target"); - return BRW_SURFACE_BUFFER; + return GEN6_SURFTYPE_BUFFER; } } @@ -225,7 +225,7 @@ ilo_gpe_gen6_fill_3dstate_sf_raster(const struct ilo_dev_info *dev, } else { payload[0] = 0; - payload[1] = (num_samples > 1) ? GEN6_SF_MSRAST_ON_PATTERN : 0; + payload[1] = (num_samples > 1) ? GEN7_SF_DW2_MSRASTMODE_ON_PATTERN : 0; payload[2] = 0; payload[3] = 0; payload[4] = 0; @@ -238,23 +238,23 @@ ilo_gpe_gen6_fill_3dstate_sf_raster(const struct ilo_dev_info *dev, /* separate stencil */ switch (depth_format) { case PIPE_FORMAT_Z16_UNORM: - format = BRW_DEPTHFORMAT_D16_UNORM; + format = GEN6_ZFORMAT_D16_UNORM; break; case PIPE_FORMAT_Z32_FLOAT: case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: - format = BRW_DEPTHFORMAT_D32_FLOAT; + format = GEN6_ZFORMAT_D32_FLOAT; break; case PIPE_FORMAT_Z24X8_UNORM: case PIPE_FORMAT_Z24_UNORM_S8_UINT: - format = BRW_DEPTHFORMAT_D24_UNORM_X8_UINT; + format = GEN6_ZFORMAT_D24_UNORM_X8_UINT; break; default: /* FLOAT surface is assumed when there is no depth buffer */ - format = BRW_DEPTHFORMAT_D32_FLOAT; + format = GEN6_ZFORMAT_D32_FLOAT; break; } - payload[0] |= format << GEN7_SF_DEPTH_BUFFER_SURFACE_FORMAT_SHIFT; + payload[0] |= format << GEN7_SF_DW1_DEPTH_FORMAT__SHIFT; } } @@ -277,9 +277,9 @@ ilo_gpe_gen6_fill_3dstate_sf_sbe(const struct ilo_dev_info *dev, memset(dw, 0, sizeof(dw[0]) * num_dwords); if (dev->gen >= ILO_GEN(7)) - dw[0] = 1 << GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT; + dw[0] = 1 << GEN7_SBE_DW1_URB_READ_LEN__SHIFT; else - dw[0] = 1 << GEN6_SF_URB_ENTRY_READ_LENGTH_SHIFT; + dw[0] = 1 << GEN7_SBE_DW1_URB_READ_LEN__SHIFT; return; } @@ -298,26 +298,26 @@ ilo_gpe_gen6_fill_3dstate_sf_sbe(const struct ilo_dev_info *dev, vue_len = 1; if (dev->gen >= ILO_GEN(7)) { - dw[0] = output_count << GEN7_SBE_NUM_OUTPUTS_SHIFT | - vue_len << GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT | - vue_offset << GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT; + dw[0] = output_count << GEN7_SBE_DW1_ATTR_COUNT__SHIFT | + vue_len << GEN7_SBE_DW1_URB_READ_LEN__SHIFT | + vue_offset << GEN7_SBE_DW1_URB_READ_OFFSET__SHIFT; if (routing->swizzle_enable) - dw[0] |= GEN7_SBE_SWIZZLE_ENABLE; + dw[0] |= GEN7_SBE_DW1_ATTR_SWIZZLE_ENABLE; } else { - dw[0] = output_count << GEN6_SF_NUM_OUTPUTS_SHIFT | - vue_len << GEN6_SF_URB_ENTRY_READ_LENGTH_SHIFT | - vue_offset << GEN6_SF_URB_ENTRY_READ_OFFSET_SHIFT; + dw[0] = output_count << GEN7_SBE_DW1_ATTR_COUNT__SHIFT | + vue_len << GEN7_SBE_DW1_URB_READ_LEN__SHIFT | + vue_offset << GEN7_SBE_DW1_URB_READ_OFFSET__SHIFT; if (routing->swizzle_enable) - dw[0] |= GEN6_SF_SWIZZLE_ENABLE; + dw[0] |= GEN7_SBE_DW1_ATTR_SWIZZLE_ENABLE; } switch (rasterizer->state.sprite_coord_mode) { case PIPE_SPRITE_COORD_UPPER_LEFT: - dw[0] |= GEN6_SF_POINT_SPRITE_UPPERLEFT; + dw[0] |= GEN7_SBE_DW1_POINT_SPRITE_TEXCOORD_UPPERLEFT; break; case PIPE_SPRITE_COORD_LOWER_LEFT: - dw[0] |= GEN6_SF_POINT_SPRITE_LOWERLEFT; + dw[0] |= GEN7_SBE_DW1_POINT_SPRITE_TEXCOORD_LOWERLEFT; break; } @@ -710,9 +710,9 @@ gen6_emit_3DSTATE_BINDING_TABLE_POINTERS(const struct ilo_dev_info *dev, ilo_cp_begin(cp, cmd_len); ilo_cp_write(cp, cmd | (cmd_len - 2) | - GEN6_BINDING_TABLE_MODIFY_VS | - GEN6_BINDING_TABLE_MODIFY_GS | - GEN6_BINDING_TABLE_MODIFY_PS); + GEN6_PTR_BINDING_TABLE_DW0_VS_CHANGED | + GEN6_PTR_BINDING_TABLE_DW0_GS_CHANGED | + GEN6_PTR_BINDING_TABLE_DW0_PS_CHANGED); ilo_cp_write(cp, vs_binding_table); ilo_cp_write(cp, gs_binding_table); ilo_cp_write(cp, ps_binding_table); @@ -733,9 +733,9 @@ gen6_emit_3DSTATE_SAMPLER_STATE_POINTERS(const struct ilo_dev_info *dev, ilo_cp_begin(cp, cmd_len); ilo_cp_write(cp, cmd | (cmd_len - 2) | - VS_SAMPLER_STATE_CHANGE | - GS_SAMPLER_STATE_CHANGE | - PS_SAMPLER_STATE_CHANGE); + GEN6_PTR_SAMPLER_DW0_VS_CHANGED | + GEN6_PTR_SAMPLER_DW0_GS_CHANGED | + GEN6_PTR_SAMPLER_DW0_PS_CHANGED); ilo_cp_write(cp, vs_sampler_state); ilo_cp_write(cp, gs_sampler_state); ilo_cp_write(cp, ps_sampler_state); @@ -780,10 +780,10 @@ gen6_emit_3DSTATE_URB(const struct ilo_dev_info *dev, ilo_cp_begin(cp, cmd_len); ilo_cp_write(cp, cmd | (cmd_len - 2)); - ilo_cp_write(cp, (vs_alloc_size - 1) << GEN6_URB_VS_SIZE_SHIFT | - vs_num_entries << GEN6_URB_VS_ENTRIES_SHIFT); - ilo_cp_write(cp, gs_num_entries << GEN6_URB_GS_ENTRIES_SHIFT | - (gs_alloc_size - 1) << GEN6_URB_GS_SIZE_SHIFT); + ilo_cp_write(cp, (vs_alloc_size - 1) << GEN6_URB_DW1_VS_ENTRY_SIZE__SHIFT | + vs_num_entries << GEN6_URB_DW1_VS_ENTRY_COUNT__SHIFT); + ilo_cp_write(cp, gs_num_entries << GEN6_URB_DW2_GS_ENTRY_COUNT__SHIFT | + (gs_alloc_size - 1) << GEN6_URB_DW2_GS_ENTRY_SIZE__SHIFT); ilo_cp_end(cp); } @@ -820,15 +820,15 @@ gen6_emit_3DSTATE_VERTEX_BUFFERS(const struct ilo_dev_info *dev, const struct pipe_vertex_buffer *cso = &vb->states[pipe_idx]; uint32_t dw; - dw = hw_idx << GEN6_VB0_INDEX_SHIFT; + dw = hw_idx << GEN6_VB_STATE_DW0_INDEX__SHIFT; if (instance_divisor) - dw |= GEN6_VB0_ACCESS_INSTANCEDATA; + dw |= GEN6_VB_STATE_DW0_ACCESS_INSTANCEDATA; else - dw |= GEN6_VB0_ACCESS_VERTEXDATA; + dw |= GEN6_VB_STATE_DW0_ACCESS_VERTEXDATA; if (dev->gen >= ILO_GEN(7)) - dw |= GEN7_VB0_ADDRESS_MODIFYENABLE; + dw |= GEN7_VB_STATE_DW0_ADDR_MODIFIED; /* use null vb if there is no buffer or the stride is out of range */ if (cso->buffer && cso->stride <= 2048) { @@ -836,7 +836,7 @@ gen6_emit_3DSTATE_VERTEX_BUFFERS(const struct ilo_dev_info *dev, const uint32_t start_offset = cso->buffer_offset; const uint32_t end_offset = buf->bo_size - 1; - dw |= cso->stride << BRW_VB0_PITCH_SHIFT; + dw |= cso->stride << GEN6_VB_STATE_DW0_PITCH__SHIFT; ilo_cp_write(cp, dw); ilo_cp_write_bo(cp, start_offset, buf->bo, INTEL_DOMAIN_VERTEX, 0); @@ -864,12 +864,12 @@ ve_init_cso_with_components(const struct ilo_dev_info *dev, ILO_GPE_VALID_GEN(dev, 6, 7.5); STATIC_ASSERT(Elements(cso->payload) >= 2); - cso->payload[0] = GEN6_VE0_VALID; + cso->payload[0] = GEN6_VE_STATE_DW0_VALID; cso->payload[1] = - comp0 << BRW_VE1_COMPONENT_0_SHIFT | - comp1 << BRW_VE1_COMPONENT_1_SHIFT | - comp2 << BRW_VE1_COMPONENT_2_SHIFT | - comp3 << BRW_VE1_COMPONENT_3_SHIFT; + comp0 << GEN6_VE_STATE_DW1_COMP0__SHIFT | + comp1 << GEN6_VE_STATE_DW1_COMP1__SHIFT | + comp2 << GEN6_VE_STATE_DW1_COMP2__SHIFT | + comp3 << GEN6_VE_STATE_DW1_COMP3__SHIFT; } static inline void @@ -897,30 +897,30 @@ ve_set_cso_edgeflag(const struct ilo_dev_info *dev, * types (e.g., POLYGONs) prior to submission to the 3D pipeline." */ - cso->payload[0] |= GEN6_VE0_EDGE_FLAG_ENABLE; + cso->payload[0] |= GEN6_VE_STATE_DW0_EDGE_FLAG_ENABLE; cso->payload[1] = - BRW_VE1_COMPONENT_STORE_SRC << BRW_VE1_COMPONENT_0_SHIFT | - BRW_VE1_COMPONENT_NOSTORE << BRW_VE1_COMPONENT_1_SHIFT | - BRW_VE1_COMPONENT_NOSTORE << BRW_VE1_COMPONENT_2_SHIFT | - BRW_VE1_COMPONENT_NOSTORE << BRW_VE1_COMPONENT_3_SHIFT; + GEN6_VFCOMP_STORE_SRC << GEN6_VE_STATE_DW1_COMP0__SHIFT | + GEN6_VFCOMP_NOSTORE << GEN6_VE_STATE_DW1_COMP1__SHIFT | + GEN6_VFCOMP_NOSTORE << GEN6_VE_STATE_DW1_COMP2__SHIFT | + GEN6_VFCOMP_NOSTORE << GEN6_VE_STATE_DW1_COMP3__SHIFT; /* - * Edge flags have format BRW_SURFACEFORMAT_R8_UINT when defined via - * glEdgeFlagPointer(), and format BRW_SURFACEFORMAT_R32_FLOAT when defined + * Edge flags have format GEN6_FORMAT_R8_UINT when defined via + * glEdgeFlagPointer(), and format GEN6_FORMAT_R32_FLOAT when defined * via glEdgeFlag(), as can be seen in vbo_attrib_tmp.h. * * Since all the hardware cares about is whether the flags are zero or not, - * we can treat them as BRW_SURFACEFORMAT_R32_UINT in the latter case. + * we can treat them as GEN6_FORMAT_R32_UINT in the latter case. */ - format = (cso->payload[0] >> BRW_VE0_FORMAT_SHIFT) & 0x1ff; - if (format == BRW_SURFACEFORMAT_R32_FLOAT) { - STATIC_ASSERT(BRW_SURFACEFORMAT_R32_UINT == - BRW_SURFACEFORMAT_R32_FLOAT - 1); + format = (cso->payload[0] >> GEN6_VE_STATE_DW0_FORMAT__SHIFT) & 0x1ff; + if (format == GEN6_FORMAT_R32_FLOAT) { + STATIC_ASSERT(GEN6_FORMAT_R32_UINT == + GEN6_FORMAT_R32_FLOAT - 1); - cso->payload[0] -= (1 << BRW_VE0_FORMAT_SHIFT); + cso->payload[0] -= (1 << GEN6_VE_STATE_DW0_FORMAT__SHIFT); } else { - assert(format == BRW_SURFACEFORMAT_R8_UINT); + assert(format == GEN6_FORMAT_R8_UINT); } } @@ -948,10 +948,10 @@ gen6_emit_3DSTATE_VERTEX_ELEMENTS(const struct ilo_dev_info *dev, struct ilo_ve_cso dummy; ve_init_cso_with_components(dev, - BRW_VE1_COMPONENT_STORE_0, - BRW_VE1_COMPONENT_STORE_0, - BRW_VE1_COMPONENT_STORE_0, - BRW_VE1_COMPONENT_STORE_1_FLT, + GEN6_VFCOMP_STORE_0, + GEN6_VFCOMP_STORE_0, + GEN6_VFCOMP_STORE_0, + GEN6_VFCOMP_STORE_1_FP, &dummy); cmd_len = 3; @@ -972,10 +972,10 @@ gen6_emit_3DSTATE_VERTEX_ELEMENTS(const struct ilo_dev_info *dev, struct ilo_ve_cso gen_ids; ve_init_cso_with_components(dev, - BRW_VE1_COMPONENT_STORE_VID, - BRW_VE1_COMPONENT_STORE_IID, - BRW_VE1_COMPONENT_NOSTORE, - BRW_VE1_COMPONENT_NOSTORE, + GEN6_VFCOMP_STORE_VID, + GEN6_VFCOMP_STORE_IID, + GEN6_VFCOMP_NOSTORE, + GEN6_VFCOMP_NOSTORE, &gen_ids); ilo_cp_write_multi(cp, gen_ids.payload, 2); @@ -1022,17 +1022,17 @@ gen6_emit_3DSTATE_INDEX_BUFFER(const struct ilo_dev_info *dev, switch (ib->hw_index_size) { case 4: - format = BRW_INDEX_DWORD; + format = GEN6_IB_DW0_FORMAT_DWORD >> GEN6_IB_DW0_FORMAT__SHIFT; break; case 2: - format = BRW_INDEX_WORD; + format = GEN6_IB_DW0_FORMAT_WORD >> GEN6_IB_DW0_FORMAT__SHIFT; break; case 1: - format = BRW_INDEX_BYTE; + format = GEN6_IB_DW0_FORMAT_BYTE >> GEN6_IB_DW0_FORMAT__SHIFT; break; default: assert(!"unknown index size"); - format = BRW_INDEX_BYTE; + format = GEN6_IB_DW0_FORMAT_BYTE >> GEN6_IB_DW0_FORMAT__SHIFT; break; } @@ -1049,7 +1049,7 @@ gen6_emit_3DSTATE_INDEX_BUFFER(const struct ilo_dev_info *dev, ilo_cp_begin(cp, cmd_len); ilo_cp_write(cp, cmd | (cmd_len - 2) | - ((enable_cut_index) ? BRW_CUT_INDEX_ENABLE : 0) | + ((enable_cut_index) ? GEN6_IB_DW0_CUT_INDEX_ENABLE : 0) | format << 8); ilo_cp_write_bo(cp, start_offset, buf->bo, INTEL_DOMAIN_VERTEX, 0); ilo_cp_write_bo(cp, end_offset, buf->bo, INTEL_DOMAIN_VERTEX, 0); @@ -1070,9 +1070,9 @@ gen6_emit_3DSTATE_VIEWPORT_STATE_POINTERS(const struct ilo_dev_info *dev, ilo_cp_begin(cp, cmd_len); ilo_cp_write(cp, cmd | (cmd_len - 2) | - GEN6_CLIP_VIEWPORT_MODIFY | - GEN6_SF_VIEWPORT_MODIFY | - GEN6_CC_VIEWPORT_MODIFY); + GEN6_PTR_VP_DW0_CLIP_CHANGED | + GEN6_PTR_VP_DW0_SF_CHANGED | + GEN6_PTR_VP_DW0_CC_CHANGED); ilo_cp_write(cp, clip_viewport); ilo_cp_write(cp, sf_viewport); ilo_cp_write(cp, cc_viewport); @@ -1145,7 +1145,7 @@ gen6_emit_3DSTATE_VS(const struct ilo_dev_info *dev, dw4 = cso->payload[1]; dw5 = cso->payload[2]; - dw2 |= ((num_samplers + 3) / 4) << GEN6_VS_SAMPLER_COUNT_SHIFT; + dw2 |= ((num_samplers + 3) / 4) << GEN6_THREADDISP_SAMPLER_COUNT__SHIFT; ilo_cp_begin(cp, cmd_len); ilo_cp_write(cp, cmd | (cmd_len - 2)); @@ -1210,8 +1210,8 @@ gen6_emit_3DSTATE_GS(const struct ilo_dev_info *dev, else { dw1 = 0; dw2 = 0; - dw4 = 1 << GEN6_GS_URB_READ_LENGTH_SHIFT; - dw5 = GEN6_GS_STATISTICS_ENABLE; + dw4 = 1 << GEN6_GS_DW4_URB_READ_LEN__SHIFT; + dw5 = GEN6_GS_DW5_STATISTICS; dw6 = 0; } @@ -1248,17 +1248,17 @@ gen6_emit_3DSTATE_CLIP(const struct ilo_dev_info *dev, dw3 = rasterizer->clip.payload[2]; if (enable_guardband && rasterizer->clip.can_enable_guardband) - dw2 |= GEN6_CLIP_GB_TEST; + dw2 |= GEN6_CLIP_DW2_GB_TEST_ENABLE; interps = (fs) ? ilo_shader_get_kernel_param(fs, ILO_KERNEL_FS_BARYCENTRIC_INTERPOLATIONS) : 0; - if (interps & (1 << BRW_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC | - 1 << BRW_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC | - 1 << BRW_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC)) - dw2 |= GEN6_CLIP_NON_PERSPECTIVE_BARYCENTRIC_ENABLE; + if (interps & (GEN6_INTERP_NONPERSPECTIVE_PIXEL | + GEN6_INTERP_NONPERSPECTIVE_CENTROID | + GEN6_INTERP_NONPERSPECTIVE_SAMPLE)) + dw2 |= GEN6_CLIP_DW2_NONPERSPECTIVE_BARYCENTRIC_ENABLE; - dw3 |= GEN6_CLIP_FORCE_ZERO_RTAINDEX | + dw3 |= GEN6_CLIP_DW3_RTAINDEX_FORCED_ZERO | (num_viewports - 1); } else { @@ -1328,7 +1328,7 @@ gen6_emit_3DSTATE_WM(const struct ilo_dev_info *dev, ilo_cp_write(cp, 0); ilo_cp_write(cp, hiz_op); /* honor the valid range even if dispatching is disabled */ - ilo_cp_write(cp, (max_threads - 1) << GEN6_WM_MAX_THREADS_SHIFT); + ilo_cp_write(cp, (max_threads - 1) << GEN6_WM_DW5_MAX_THREADS__SHIFT); ilo_cp_write(cp, 0); ilo_cp_write(cp, 0); ilo_cp_write(cp, 0); @@ -1343,7 +1343,7 @@ gen6_emit_3DSTATE_WM(const struct ilo_dev_info *dev, dw5 = fs_cso->payload[2]; dw6 = fs_cso->payload[3]; - dw2 |= (num_samplers + 3) / 4 << GEN6_WM_SAMPLER_COUNT_SHIFT; + dw2 |= (num_samplers + 3) / 4 << GEN6_THREADDISP_SAMPLER_COUNT__SHIFT; /* * From the Sandy Bridge PRM, volume 2 part 1, page 248: @@ -1353,15 +1353,15 @@ gen6_emit_3DSTATE_WM(const struct ilo_dev_info *dev, * Enable or Depth Buffer Resolve Enable." */ assert(!hiz_op); - dw4 |= GEN6_WM_STATISTICS_ENABLE; + dw4 |= GEN6_WM_DW4_STATISTICS; if (cc_may_kill) { - dw5 |= GEN6_WM_KILL_ENABLE | - GEN6_WM_DISPATCH_ENABLE; + dw5 |= GEN6_WM_DW5_PS_KILL | + GEN6_WM_DW5_PS_ENABLE; } if (dual_blend) - dw5 |= GEN6_WM_DUAL_SOURCE_BLEND_ENABLE; + dw5 |= GEN6_WM_DW5_DUAL_SOURCE_BLEND; dw5 |= rasterizer->wm.payload[0]; @@ -1736,9 +1736,9 @@ gen6_emit_3DSTATE_GS_SVB_INDEX(const struct ilo_dev_info *dev, ILO_GPE_VALID_GEN(dev, 6, 6); assert(index >= 0 && index < 4); - dw1 = index << SVB_INDEX_SHIFT; + dw1 = index << GEN6_SVBI_DW1_INDEX__SHIFT; if (load_vertex_count) - dw1 |= SVB_LOAD_INTERNAL_VERTEX_COUNT; + dw1 |= GEN6_SVBI_DW1_LOAD_INTERNAL_VERTEX_COUNT; ilo_cp_begin(cp, cmd_len); ilo_cp_write(cp, cmd | (cmd_len - 2)); @@ -1762,29 +1762,29 @@ gen6_emit_3DSTATE_MULTISAMPLE(const struct ilo_dev_info *dev, ILO_GPE_VALID_GEN(dev, 6, 7.5); dw1 = (pixel_location_center) ? - MS_PIXEL_LOCATION_CENTER : MS_PIXEL_LOCATION_UPPER_LEFT; + GEN6_MULTISAMPLE_DW1_PIXLOC_CENTER : GEN6_MULTISAMPLE_DW1_PIXLOC_UL_CORNER; switch (num_samples) { case 0: case 1: - dw1 |= MS_NUMSAMPLES_1; + dw1 |= GEN6_MULTISAMPLE_DW1_NUMSAMPLES_1; dw2 = 0; dw3 = 0; break; case 4: - dw1 |= MS_NUMSAMPLES_4; + dw1 |= GEN6_MULTISAMPLE_DW1_NUMSAMPLES_4; dw2 = packed_sample_pos[0]; dw3 = 0; break; case 8: assert(dev->gen >= ILO_GEN(7)); - dw1 |= MS_NUMSAMPLES_8; + dw1 |= GEN7_MULTISAMPLE_DW1_NUMSAMPLES_8; dw2 = packed_sample_pos[0]; dw3 = packed_sample_pos[1]; break; default: assert(!"unsupported sample count"); - dw1 |= MS_NUMSAMPLES_1; + dw1 |= GEN6_MULTISAMPLE_DW1_NUMSAMPLES_1; dw2 = 0; dw3 = 0; break; @@ -1853,7 +1853,7 @@ gen6_emit_3DSTATE_CLEAR_PARAMS(const struct ilo_dev_info *dev, ilo_cp_begin(cp, cmd_len); ilo_cp_write(cp, cmd | (cmd_len - 2) | - GEN5_DEPTH_CLEAR_VALID); + GEN6_CLEAR_PARAMS_DW0_VALID); ilo_cp_write(cp, clear_val); ilo_cp_end(cp); } @@ -1874,7 +1874,7 @@ gen6_emit_PIPE_CONTROL(const struct ilo_dev_info *dev, assert(bo_offset % ((write_qword) ? 8 : 4) == 0); - if (dw1 & PIPE_CONTROL_CS_STALL) { + if (dw1 & GEN6_PIPE_CONTROL_CS_STALL) { /* * From the Sandy Bridge PRM, volume 2 part 1, page 73: * @@ -1897,23 +1897,23 @@ gen6_emit_PIPE_CONTROL(const struct ilo_dev_info *dev, * * Depth Stall ([13] of DW1) * * Post-Sync Operation ([13] of DW1)" */ - uint32_t bit_test = PIPE_CONTROL_WRITE_FLUSH | - PIPE_CONTROL_DEPTH_CACHE_FLUSH | - PIPE_CONTROL_STALL_AT_SCOREBOARD | - PIPE_CONTROL_DEPTH_STALL; + uint32_t bit_test = GEN6_PIPE_CONTROL_RENDER_CACHE_FLUSH | + GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH | + GEN6_PIPE_CONTROL_PIXEL_SCOREBOARD_STALL | + GEN6_PIPE_CONTROL_DEPTH_STALL; /* post-sync op */ - bit_test |= PIPE_CONTROL_WRITE_IMMEDIATE | - PIPE_CONTROL_WRITE_DEPTH_COUNT | - PIPE_CONTROL_WRITE_TIMESTAMP; + bit_test |= GEN6_PIPE_CONTROL_WRITE_IMM | + GEN6_PIPE_CONTROL_WRITE_PS_DEPTH_COUNT | + GEN6_PIPE_CONTROL_WRITE_TIMESTAMP; if (dev->gen == ILO_GEN(6)) - bit_test |= PIPE_CONTROL_INTERRUPT_ENABLE; + bit_test |= GEN6_PIPE_CONTROL_NOTIFY_ENABLE; assert(dw1 & bit_test); } - if (dw1 & PIPE_CONTROL_DEPTH_STALL) { + if (dw1 & GEN6_PIPE_CONTROL_DEPTH_STALL) { /* * From the Sandy Bridge PRM, volume 2 part 1, page 73: * @@ -1922,8 +1922,8 @@ gen6_emit_PIPE_CONTROL(const struct ilo_dev_info *dev, * * Render Target Cache Flush Enable ([12] of DW1) * * Depth Cache Flush Enable ([0] of DW1)" */ - assert(!(dw1 & (PIPE_CONTROL_WRITE_FLUSH | - PIPE_CONTROL_DEPTH_CACHE_FLUSH))); + assert(!(dw1 & (GEN6_PIPE_CONTROL_RENDER_CACHE_FLUSH | + GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH))); } /* @@ -1936,7 +1936,7 @@ gen6_emit_PIPE_CONTROL(const struct ilo_dev_info *dev, * INTEL_DOMAIN_INSTRUCTION). */ if (dev->gen == ILO_GEN(6) && bo) - bo_offset |= PIPE_CONTROL_GLOBAL_GTT_WRITE; + bo_offset |= GEN6_PIPE_CONTROL_DW2_USE_GGTT; ilo_cp_begin(cp, cmd_len); ilo_cp_write(cp, cmd | (cmd_len - 2)); @@ -1958,10 +1958,10 @@ gen6_emit_3DPRIMITIVE(const struct ilo_dev_info *dev, const uint32_t cmd = ILO_GPE_CMD(0x3, 0x3, 0x00); const uint8_t cmd_len = 6; const int prim = (rectlist) ? - _3DPRIM_RECTLIST : ilo_gpe_gen6_translate_pipe_prim(info->mode); + GEN6_3DPRIM_RECTLIST : ilo_gpe_gen6_translate_pipe_prim(info->mode); const int vb_access = (info->indexed) ? - GEN4_3DPRIM_VERTEXBUFFER_ACCESS_RANDOM : - GEN4_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL; + GEN6_3DPRIM_DW0_ACCESS_RANDOM : + GEN6_3DPRIM_DW0_ACCESS_SEQUENTIAL; const uint32_t vb_start = info->start + ((info->indexed) ? ib->draw_start_offset : 0); @@ -1969,7 +1969,7 @@ gen6_emit_3DPRIMITIVE(const struct ilo_dev_info *dev, ilo_cp_begin(cp, cmd_len); ilo_cp_write(cp, cmd | (cmd_len - 2) | - prim << GEN4_3DPRIM_TOPOLOGY_TYPE_SHIFT | + prim << GEN6_3DPRIM_DW0_TYPE__SHIFT | vb_access); ilo_cp_write(cp, info->count); ilo_cp_write(cp, vb_start); @@ -2164,7 +2164,7 @@ gen6_emit_COLOR_CALC_STATE(const struct ilo_dev_info *dev, dw[0] = stencil_ref->ref_value[0] << 24 | stencil_ref->ref_value[1] << 16 | - BRW_ALPHATEST_FORMAT_UNORM8; + GEN6_CC_DW0_ALPHATEST_UNORM8; dw[1] = alpha_ref; dw[2] = fui(blend_color->color[0]); dw[3] = fui(blend_color->color[1]); @@ -2228,7 +2228,7 @@ gen6_emit_BLEND_STATE(const struct ilo_dev_info *dev, case PIPE_FORMAT_B8G8R8X8_UNORM: /* force alpha to one when the HW format has alpha */ assert(ilo_translate_render_format(PIPE_FORMAT_B8G8R8X8_UNORM) - == BRW_SURFACEFORMAT_B8G8R8A8_UNORM); + == GEN6_FORMAT_B8G8R8A8_UNORM); rt_dst_alpha_forced_one = true; break; default: diff --git a/src/gallium/drivers/ilo/ilo_gpe_gen7.c b/src/gallium/drivers/ilo/ilo_gpe_gen7.c index f5a32695140..5dd427374f9 100644 --- a/src/gallium/drivers/ilo/ilo_gpe_gen7.c +++ b/src/gallium/drivers/ilo/ilo_gpe_gen7.c @@ -61,16 +61,16 @@ ilo_gpe_init_gs_cso_gen7(const struct ilo_dev_info *dev, break; } - dw2 = (true) ? 0 : GEN6_GS_FLOATING_POINT_MODE_ALT; + dw2 = (true) ? 0 : GEN6_THREADDISP_FP_MODE_ALT; - dw4 = vue_read_len << GEN6_GS_URB_READ_LENGTH_SHIFT | - GEN7_GS_INCLUDE_VERTEX_HANDLES | - 0 << GEN6_GS_URB_ENTRY_READ_OFFSET_SHIFT | - start_grf << GEN6_GS_DISPATCH_START_GRF_SHIFT; + dw4 = vue_read_len << GEN6_GS_DW4_URB_READ_LEN__SHIFT | + GEN7_GS_DW4_INCLUDE_VERTEX_HANDLES | + 0 << GEN6_GS_DW4_URB_READ_OFFSET__SHIFT | + start_grf << GEN6_GS_DW4_URB_GRF_START__SHIFT; - dw5 = (max_threads - 1) << GEN6_GS_MAX_THREADS_SHIFT | - GEN6_GS_STATISTICS_ENABLE | - GEN6_GS_ENABLE; + dw5 = (max_threads - 1) << GEN6_GS_DW5_MAX_THREADS__SHIFT | + GEN6_GS_DW5_STATISTICS | + GEN6_GS_DW6_GS_ENABLE; STATIC_ASSERT(Elements(cso->payload) >= 3); cso->payload[0] = dw2; @@ -87,23 +87,23 @@ ilo_gpe_init_rasterizer_wm_gen7(const struct ilo_dev_info *dev, ILO_GPE_VALID_GEN(dev, 7, 7.5); - dw1 = GEN7_WM_POSITION_ZW_PIXEL | - GEN7_WM_LINE_AA_WIDTH_2_0 | - GEN7_WM_MSRAST_OFF_PIXEL; + dw1 = GEN7_WM_DW1_ZW_INTERP_PIXEL | + GEN7_WM_DW1_AA_LINE_WIDTH_2_0 | + GEN7_WM_DW1_MSRASTMODE_OFF_PIXEL; /* same value as in 3DSTATE_SF */ if (state->line_smooth) - dw1 |= GEN7_WM_LINE_END_CAP_AA_WIDTH_1_0; + dw1 |= GEN7_WM_DW1_AA_LINE_CAP_1_0; if (state->poly_stipple_enable) - dw1 |= GEN7_WM_POLYGON_STIPPLE_ENABLE; + dw1 |= GEN7_WM_DW1_POLY_STIPPLE_ENABLE; if (state->line_stipple_enable) - dw1 |= GEN7_WM_LINE_STIPPLE_ENABLE; + dw1 |= GEN7_WM_DW1_LINE_STIPPLE_ENABLE; if (state->bottom_edge_rule) - dw1 |= GEN7_WM_POINT_RASTRULE_UPPER_RIGHT; + dw1 |= GEN7_WM_DW1_POINT_RASTRULE_UPPER_RIGHT; - dw2 = GEN7_WM_MSDISPMODE_PERSAMPLE; + dw2 = GEN7_WM_DW2_MSDISPMODE_PERSAMPLE; /* * assertion that makes sure @@ -113,12 +113,12 @@ ilo_gpe_init_rasterizer_wm_gen7(const struct ilo_dev_info *dev, * * is valid */ - STATIC_ASSERT(GEN7_WM_MSRAST_OFF_PIXEL == 0 && - GEN7_WM_MSDISPMODE_PERSAMPLE == 0); + STATIC_ASSERT(GEN7_WM_DW1_MSRASTMODE_OFF_PIXEL == 0 && + GEN7_WM_DW2_MSDISPMODE_PERSAMPLE == 0); wm->dw_msaa_rast = - (state->multisample) ? GEN7_WM_MSRAST_ON_PATTERN : 0; - wm->dw_msaa_disp = GEN7_WM_MSDISPMODE_PERPIXEL; + (state->multisample) ? GEN7_WM_DW1_MSRASTMODE_ON_PATTERN : 0; + wm->dw_msaa_disp = GEN7_WM_DW2_MSDISPMODE_PERPIXEL; STATIC_ASSERT(Elements(wm->payload) >= 2); wm->payload[0] = dw1; @@ -138,36 +138,36 @@ ilo_gpe_init_fs_cso_gen7(const struct ilo_dev_info *dev, start_grf = ilo_shader_get_kernel_param(fs, ILO_KERNEL_URB_DATA_START_REG); - dw2 = (true) ? 0 : GEN7_PS_FLOATING_POINT_MODE_ALT; + dw2 = (true) ? 0 : GEN6_THREADDISP_FP_MODE_ALT; - dw4 = GEN7_PS_POSOFFSET_NONE; + dw4 = GEN7_PS_DW4_POSOFFSET_NONE; /* see brwCreateContext() */ switch (dev->gen) { case ILO_GEN(7.5): max_threads = (dev->gt == 3) ? 408 : (dev->gt == 2) ? 204 : 102; - dw4 |= (max_threads - 1) << HSW_PS_MAX_THREADS_SHIFT; - dw4 |= 1 << HSW_PS_SAMPLE_MASK_SHIFT; + dw4 |= (max_threads - 1) << GEN75_PS_DW4_MAX_THREADS__SHIFT; + dw4 |= 1 << GEN75_PS_DW4_SAMPLE_MASK__SHIFT; break; case ILO_GEN(7): default: max_threads = (dev->gt == 2) ? 172 : 48; - dw4 |= (max_threads - 1) << IVB_PS_MAX_THREADS_SHIFT; + dw4 |= (max_threads - 1) << GEN7_PS_DW4_MAX_THREADS__SHIFT; break; } if (ilo_shader_get_kernel_param(fs, ILO_KERNEL_PCB_CBUF0_SIZE)) - dw4 |= GEN7_PS_PUSH_CONSTANT_ENABLE; + dw4 |= GEN7_PS_DW4_PUSH_CONSTANT_ENABLE; if (ilo_shader_get_kernel_param(fs, ILO_KERNEL_INPUT_COUNT)) - dw4 |= GEN7_PS_ATTRIBUTE_ENABLE; + dw4 |= GEN7_PS_DW4_ATTR_ENABLE; assert(!ilo_shader_get_kernel_param(fs, ILO_KERNEL_FS_DISPATCH_16_OFFSET)); - dw4 |= GEN7_PS_8_DISPATCH_ENABLE; + dw4 |= GEN7_PS_DW4_8_PIXEL_DISPATCH; - dw5 = start_grf << GEN7_PS_DISPATCH_START_GRF_SHIFT_0 | - 0 << GEN7_PS_DISPATCH_START_GRF_SHIFT_1 | - 0 << GEN7_PS_DISPATCH_START_GRF_SHIFT_2; + dw5 = start_grf << GEN7_PS_DW5_URB_GRF_START0__SHIFT | + 0 << GEN7_PS_DW5_URB_GRF_START1__SHIFT | + 0 << GEN7_PS_DW5_URB_GRF_START2__SHIFT; /* FS affects 3DSTATE_WM too */ wm_dw1 = 0; @@ -179,7 +179,7 @@ ilo_gpe_init_fs_cso_gen7(const struct ilo_dev_info *dev, * b) fs writes depth, or * c) fs or cc kills */ - wm_dw1 |= GEN7_WM_DISPATCH_ENABLE; + wm_dw1 |= GEN7_WM_DW1_PS_ENABLE; /* * From the Ivy Bridge PRM, volume 2 part 1, page 278: @@ -208,21 +208,21 @@ ilo_gpe_init_fs_cso_gen7(const struct ilo_dev_info *dev, * to ENABLE this bit due to ClipDistance clipping." */ if (ilo_shader_get_kernel_param(fs, ILO_KERNEL_FS_USE_KILL)) - wm_dw1 |= GEN7_WM_KILL_ENABLE; + wm_dw1 |= GEN7_WM_DW1_PS_KILL; if (ilo_shader_get_kernel_param(fs, ILO_KERNEL_FS_OUTPUT_Z)) - wm_dw1 |= GEN7_WM_PSCDEPTH_ON; + wm_dw1 |= GEN7_WM_DW1_PSCDEPTH_ON; if (ilo_shader_get_kernel_param(fs, ILO_KERNEL_FS_INPUT_Z)) - wm_dw1 |= GEN7_WM_USES_SOURCE_DEPTH; + wm_dw1 |= GEN7_WM_DW1_PS_USE_DEPTH; if (ilo_shader_get_kernel_param(fs, ILO_KERNEL_FS_INPUT_W)) - wm_dw1 |= GEN7_WM_USES_SOURCE_W; + wm_dw1 |= GEN7_WM_DW1_PS_USE_W; wm_interps = ilo_shader_get_kernel_param(fs, ILO_KERNEL_FS_BARYCENTRIC_INTERPOLATIONS); - wm_dw1 |= wm_interps << GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT; + wm_dw1 |= wm_interps << GEN7_WM_DW1_BARYCENTRIC_INTERP__SHIFT; STATIC_ASSERT(Elements(cso->payload) >= 4); cso->payload[0] = dw2; @@ -275,9 +275,9 @@ ilo_gpe_init_view_surface_null_gen7(const struct ilo_dev_info *dev, STATIC_ASSERT(Elements(surf->payload) >= 8); dw = surf->payload; - dw[0] = BRW_SURFACE_NULL << BRW_SURFACE_TYPE_SHIFT | - BRW_SURFACEFORMAT_B8G8R8A8_UNORM << BRW_SURFACE_FORMAT_SHIFT | - BRW_SURFACE_TILED << 13; + dw[0] = GEN6_SURFTYPE_NULL << GEN6_SURFACE_DW0_TYPE__SHIFT | + GEN6_FORMAT_B8G8R8A8_UNORM << GEN6_SURFACE_DW0_FORMAT__SHIFT | + GEN6_TILING_X << 13; dw[1] = 0; @@ -314,10 +314,10 @@ ilo_gpe_init_view_surface_for_buffer_gen7(const struct ilo_dev_info *dev, ILO_GPE_VALID_GEN(dev, 7, 7.5); - surface_type = (structured) ? 5 : BRW_SURFACE_BUFFER; + surface_type = (structured) ? 5 : GEN6_SURFTYPE_BUFFER; surface_format = (typed) ? - ilo_translate_color_format(elem_format) : BRW_SURFACEFORMAT_RAW; + ilo_translate_color_format(elem_format) : GEN6_FORMAT_RAW; num_entries = size / struct_size; /* see if there is enough space to fit another element */ @@ -390,10 +390,10 @@ ilo_gpe_init_view_surface_for_buffer_gen7(const struct ilo_dev_info *dev, STATIC_ASSERT(Elements(surf->payload) >= 8); dw = surf->payload; - dw[0] = surface_type << BRW_SURFACE_TYPE_SHIFT | - surface_format << BRW_SURFACE_FORMAT_SHIFT; + dw[0] = surface_type << GEN6_SURFACE_DW0_TYPE__SHIFT | + surface_format << GEN6_SURFACE_DW0_FORMAT__SHIFT; if (render_cache_rw) - dw[0] |= BRW_SURFACE_RC_READ_WRITE; + dw[0] |= GEN6_SURFACE_DW0_RENDER_CACHE_RW; dw[1] = offset; @@ -410,10 +410,10 @@ ilo_gpe_init_view_surface_for_buffer_gen7(const struct ilo_dev_info *dev, dw[7] = 0; if (dev->gen >= ILO_GEN(7.5)) { - dw[7] |= SET_FIELD(HSW_SCS_RED, GEN7_SURFACE_SCS_R) | - SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) | - SET_FIELD(HSW_SCS_BLUE, GEN7_SURFACE_SCS_B) | - SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A); + dw[7] |= SET_FIELD(GEN75_SCS_RED, GEN7_SURFACE_SCS_R) | + SET_FIELD(GEN75_SCS_GREEN, GEN7_SURFACE_SCS_G) | + SET_FIELD(GEN75_SCS_BLUE, GEN7_SURFACE_SCS_B) | + SET_FIELD(GEN75_SCS_ALPHA, GEN7_SURFACE_SCS_A); } /* do not increment reference count */ @@ -439,7 +439,7 @@ ilo_gpe_init_view_surface_for_texture_gen7(const struct ilo_dev_info *dev, ILO_GPE_VALID_GEN(dev, 7, 7.5); surface_type = ilo_gpe_gen6_translate_texture(tex->base.target); - assert(surface_type != BRW_SURFACE_BUFFER); + assert(surface_type != GEN6_SURFTYPE_BUFFER); if (format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT && tex->separate_s8) format = PIPE_FORMAT_Z32_FLOAT; @@ -456,7 +456,7 @@ ilo_gpe_init_view_surface_for_texture_gen7(const struct ilo_dev_info *dev, tex->base.depth0 : num_layers; pitch = tex->bo_stride; - if (surface_type == BRW_SURFACE_CUBE) { + if (surface_type == GEN6_SURFTYPE_CUBE) { /* * From the Ivy Bridge PRM, volume 4 part 1, page 70: * @@ -469,7 +469,7 @@ ilo_gpe_init_view_surface_for_texture_gen7(const struct ilo_dev_info *dev, * restriction. */ if (is_rt) { - surface_type = BRW_SURFACE_2D; + surface_type = GEN6_SURFTYPE_2D; } else { assert(num_layers % 6 == 0); @@ -481,18 +481,18 @@ ilo_gpe_init_view_surface_for_texture_gen7(const struct ilo_dev_info *dev, assert(width >= 1 && height >= 1 && depth >= 1 && pitch >= 1); assert(first_layer < 2048 && num_layers <= 2048); switch (surface_type) { - case BRW_SURFACE_1D: + case GEN6_SURFTYPE_1D: assert(width <= 16384 && height == 1 && depth <= 2048); break; - case BRW_SURFACE_2D: + case GEN6_SURFTYPE_2D: assert(width <= 16384 && height <= 16384 && depth <= 2048); break; - case BRW_SURFACE_3D: + case GEN6_SURFTYPE_3D: assert(width <= 2048 && height <= 2048 && depth <= 2048); if (!is_rt) assert(first_layer == 0); break; - case BRW_SURFACE_CUBE: + case GEN6_SURFTYPE_CUBE: assert(width <= 16384 && height <= 16384 && depth <= 86); assert(width == height); if (is_rt) @@ -580,8 +580,8 @@ ilo_gpe_init_view_surface_for_texture_gen7(const struct ilo_dev_info *dev, STATIC_ASSERT(Elements(surf->payload) >= 8); dw = surf->payload; - dw[0] = surface_type << BRW_SURFACE_TYPE_SHIFT | - surface_format << BRW_SURFACE_FORMAT_SHIFT | + dw[0] = surface_type << GEN6_SURFACE_DW0_TYPE__SHIFT | + surface_format << GEN6_SURFACE_DW0_FORMAT__SHIFT | ilo_gpe_gen6_translate_winsys_tiling(tex->tiling) << 13; /* @@ -595,29 +595,29 @@ ilo_gpe_init_view_surface_for_texture_gen7(const struct ilo_dev_info *dev, * For non-3D sampler surfaces, resinfo (the sampler message) always * returns zero for the number of layers when this field is not set. */ - if (surface_type != BRW_SURFACE_3D) { + if (surface_type != GEN6_SURFTYPE_3D) { if (util_resource_is_array_texture(&tex->base)) - dw[0] |= GEN7_SURFACE_IS_ARRAY; + dw[0] |= GEN7_SURFACE_DW0_IS_ARRAY; else assert(depth == 1); } if (tex->valign_4) - dw[0] |= GEN7_SURFACE_VALIGN_4; + dw[0] |= GEN7_SURFACE_DW0_VALIGN_4; if (tex->halign_8) - dw[0] |= GEN7_SURFACE_HALIGN_8; + dw[0] |= GEN7_SURFACE_DW0_HALIGN_8; if (tex->array_spacing_full) - dw[0] |= GEN7_SURFACE_ARYSPC_FULL; + dw[0] |= GEN7_SURFACE_DW0_ARYSPC_FULL; else - dw[0] |= GEN7_SURFACE_ARYSPC_LOD0; + dw[0] |= GEN7_SURFACE_DW0_ARYSPC_LOD0; if (is_rt) - dw[0] |= BRW_SURFACE_RC_READ_WRITE; + dw[0] |= GEN6_SURFACE_DW0_RENDER_CACHE_RW; - if (surface_type == BRW_SURFACE_CUBE && !is_rt) - dw[0] |= BRW_SURFACE_CUBEFACE_ENABLES; + if (surface_type == GEN6_SURFTYPE_CUBE && !is_rt) + dw[0] |= GEN6_SURFACE_DW0_CUBE_FACE_ENABLES__MASK; dw[1] = layer_offset; @@ -637,21 +637,21 @@ ilo_gpe_init_view_surface_for_texture_gen7(const struct ilo_dev_info *dev, */ if (tex->interleaved && tex->base.nr_samples > 1) { assert(!is_rt); - dw[4] |= GEN7_SURFACE_MSFMT_DEPTH_STENCIL; + dw[4] |= GEN7_SURFACE_DW4_MSFMT_DEPTH_STENCIL; } else { - dw[4] |= GEN7_SURFACE_MSFMT_MSS; + dw[4] |= GEN7_SURFACE_DW4_MSFMT_MSS; } if (tex->base.nr_samples > 4) - dw[4] |= GEN7_SURFACE_MULTISAMPLECOUNT_8; + dw[4] |= GEN7_SURFACE_DW4_MULTISAMPLECOUNT_8; else if (tex->base.nr_samples > 2) - dw[4] |= GEN7_SURFACE_MULTISAMPLECOUNT_4; + dw[4] |= GEN7_SURFACE_DW4_MULTISAMPLECOUNT_4; else - dw[4] |= GEN7_SURFACE_MULTISAMPLECOUNT_1; + dw[4] |= GEN7_SURFACE_DW4_MULTISAMPLECOUNT_1; - dw[5] = x_offset << BRW_SURFACE_X_OFFSET_SHIFT | - y_offset << BRW_SURFACE_Y_OFFSET_SHIFT | + dw[5] = x_offset << GEN6_SURFACE_DW5_X_OFFSET__SHIFT | + y_offset << GEN6_SURFACE_DW5_Y_OFFSET__SHIFT | SET_FIELD(first_level, GEN7_SURFACE_MIN_LOD) | lod; @@ -659,10 +659,10 @@ ilo_gpe_init_view_surface_for_texture_gen7(const struct ilo_dev_info *dev, dw[7] = 0; if (dev->gen >= ILO_GEN(7.5)) { - dw[7] |= SET_FIELD(HSW_SCS_RED, GEN7_SURFACE_SCS_R) | - SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) | - SET_FIELD(HSW_SCS_BLUE, GEN7_SURFACE_SCS_B) | - SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A); + dw[7] |= SET_FIELD(GEN75_SCS_RED, GEN7_SURFACE_SCS_R) | + SET_FIELD(GEN75_SCS_GREEN, GEN7_SURFACE_SCS_G) | + SET_FIELD(GEN75_SCS_BLUE, GEN7_SURFACE_SCS_B) | + SET_FIELD(GEN75_SCS_ALPHA, GEN7_SURFACE_SCS_A); } /* do not increment reference count */ diff --git a/src/gallium/drivers/ilo/ilo_gpe_gen7.h b/src/gallium/drivers/ilo/ilo_gpe_gen7.h index e4612fb391c..ddddf0809f2 100644 --- a/src/gallium/drivers/ilo/ilo_gpe_gen7.h +++ b/src/gallium/drivers/ilo/ilo_gpe_gen7.h @@ -184,7 +184,7 @@ gen7_emit_3DSTATE_VF(const struct ilo_dev_info *dev, ilo_cp_begin(cp, cmd_len); ilo_cp_write(cp, cmd | (cmd_len - 2) | - ((enable_cut_index) ? HSW_CUT_INDEX_ENABLE : 0)); + ((enable_cut_index) ? GEN75_VF_DW0_CUT_INDEX_ENABLE : 0)); ilo_cp_write(cp, cut_index); ilo_cp_end(cp); } @@ -233,7 +233,7 @@ gen7_emit_3DSTATE_GS(const struct ilo_dev_info *dev, ilo_cp_write(cp, 0); ilo_cp_write(cp, 0); ilo_cp_write(cp, 0); - ilo_cp_write(cp, GEN6_GS_STATISTICS_ENABLE); + ilo_cp_write(cp, GEN6_GS_DW5_STATISTICS); ilo_cp_write(cp, 0); ilo_cp_end(cp); return; @@ -244,7 +244,7 @@ gen7_emit_3DSTATE_GS(const struct ilo_dev_info *dev, dw4 = cso->payload[1]; dw5 = cso->payload[2]; - dw2 |= ((num_samplers + 3) / 4) << GEN6_GS_SAMPLER_COUNT_SHIFT; + dw2 |= ((num_samplers + 3) / 4) << GEN6_THREADDISP_SAMPLER_COUNT__SHIFT; ilo_cp_begin(cp, cmd_len); ilo_cp_write(cp, cmd | (cmd_len - 2)); @@ -300,7 +300,7 @@ gen7_emit_3DSTATE_WM(const struct ilo_dev_info *dev, dw2 = rasterizer->wm.payload[1]; assert(!hiz_op); - dw1 |= GEN7_WM_STATISTICS_ENABLE; + dw1 |= GEN7_WM_DW1_STATISTICS; } else { dw1 = hiz_op; @@ -314,8 +314,8 @@ gen7_emit_3DSTATE_WM(const struct ilo_dev_info *dev, } if (cc_may_kill) { - dw1 |= GEN7_WM_DISPATCH_ENABLE | - GEN7_WM_KILL_ENABLE; + dw1 |= GEN7_WM_DW1_PS_ENABLE | + GEN7_WM_DW1_PS_KILL; } if (num_samples > 1) { @@ -553,9 +553,9 @@ gen7_emit_3DSTATE_STREAMOUT(const struct ilo_dev_info *dev, ILO_GPE_VALID_GEN(dev, 7, 7.5); if (!enable) { - dw1 = 0 << SO_RENDER_STREAM_SELECT_SHIFT; + dw1 = 0 << GEN7_SO_DW1_RENDER_STREAM_SELECT__SHIFT; if (rasterizer_discard) - dw1 |= SO_RENDERING_DISABLE; + dw1 |= GEN7_SO_DW1_RENDER_DISABLE; dw2 = 0; @@ -571,26 +571,26 @@ gen7_emit_3DSTATE_STREAMOUT(const struct ilo_dev_info *dev, if (!read_len) read_len = 1; - dw1 = SO_FUNCTION_ENABLE | - 0 << SO_RENDER_STREAM_SELECT_SHIFT | - SO_STATISTICS_ENABLE | + dw1 = GEN7_SO_DW1_SO_ENABLE | + 0 << GEN7_SO_DW1_RENDER_STREAM_SELECT__SHIFT | + GEN7_SO_DW1_STATISTICS | buffer_mask << 8; if (rasterizer_discard) - dw1 |= SO_RENDERING_DISABLE; + dw1 |= GEN7_SO_DW1_RENDER_DISABLE; /* API_OPENGL */ if (true) - dw1 |= SO_REORDER_TRAILING; + dw1 |= GEN7_SO_DW1_REORDER_TRAILING; - dw2 = 0 << SO_STREAM_3_VERTEX_READ_OFFSET_SHIFT | - 0 << SO_STREAM_3_VERTEX_READ_LENGTH_SHIFT | - 0 << SO_STREAM_2_VERTEX_READ_OFFSET_SHIFT | - 0 << SO_STREAM_2_VERTEX_READ_LENGTH_SHIFT | - 0 << SO_STREAM_1_VERTEX_READ_OFFSET_SHIFT | - 0 << SO_STREAM_1_VERTEX_READ_LENGTH_SHIFT | - 0 << SO_STREAM_0_VERTEX_READ_OFFSET_SHIFT | - (read_len - 1) << SO_STREAM_0_VERTEX_READ_LENGTH_SHIFT; + dw2 = 0 << GEN7_SO_DW2_STREAM3_READ_OFFSET__SHIFT | + 0 << GEN7_SO_DW2_STREAM3_READ_LEN__SHIFT | + 0 << GEN7_SO_DW2_STREAM2_READ_OFFSET__SHIFT | + 0 << GEN7_SO_DW2_STREAM2_READ_LEN__SHIFT | + 0 << GEN7_SO_DW2_STREAM1_READ_OFFSET__SHIFT | + 0 << GEN7_SO_DW2_STREAM1_READ_LEN__SHIFT | + 0 << GEN7_SO_DW2_STREAM0_READ_OFFSET__SHIFT | + (read_len - 1) << GEN7_SO_DW2_STREAM0_READ_LEN__SHIFT; ilo_cp_begin(cp, cmd_len); ilo_cp_write(cp, cmd | (cmd_len - 2)); @@ -636,18 +636,18 @@ gen7_emit_3DSTATE_PS(const struct ilo_dev_info *dev, int max_threads; /* GPU hangs if none of the dispatch enable bits is set */ - dw4 = GEN7_PS_8_DISPATCH_ENABLE; + dw4 = GEN7_PS_DW4_8_PIXEL_DISPATCH; /* see brwCreateContext() */ switch (dev->gen) { case ILO_GEN(7.5): max_threads = (dev->gt == 3) ? 408 : (dev->gt == 2) ? 204 : 102; - dw4 |= (max_threads - 1) << HSW_PS_MAX_THREADS_SHIFT; + dw4 |= (max_threads - 1) << GEN75_PS_DW4_MAX_THREADS__SHIFT; break; case ILO_GEN(7): default: max_threads = (dev->gt == 2) ? 172 : 48; - dw4 |= (max_threads - 1) << IVB_PS_MAX_THREADS_SHIFT; + dw4 |= (max_threads - 1) << GEN7_PS_DW4_MAX_THREADS__SHIFT; break; } @@ -670,10 +670,10 @@ gen7_emit_3DSTATE_PS(const struct ilo_dev_info *dev, dw4 = cso->payload[1]; dw5 = cso->payload[2]; - dw2 |= (num_samplers + 3) / 4 << GEN7_PS_SAMPLER_COUNT_SHIFT; + dw2 |= (num_samplers + 3) / 4 << GEN6_THREADDISP_SAMPLER_COUNT__SHIFT; if (dual_blend) - dw4 |= GEN7_PS_DUAL_SOURCE_BLEND_ENABLE; + dw4 |= GEN7_PS_DW4_DUAL_SOURCE_BLEND; ilo_cp_begin(cp, cmd_len); ilo_cp_write(cp, cmd | (cmd_len - 2)); @@ -884,8 +884,8 @@ gen7_emit_3dstate_urb(const struct ilo_dev_info *dev, ilo_cp_begin(cp, cmd_len); ilo_cp_write(cp, cmd | (cmd_len - 2)); - ilo_cp_write(cp, offset << GEN7_URB_STARTING_ADDRESS_SHIFT | - (alloc_size - 1) << GEN7_URB_ENTRY_SIZE_SHIFT | + ilo_cp_write(cp, offset << GEN7_URB_ANY_DW1_OFFSET__SHIFT | + (alloc_size - 1) << GEN7_URB_ANY_DW1_ENTRY_SIZE__SHIFT | num_entries); ilo_cp_end(cp); } @@ -976,7 +976,7 @@ gen7_emit_3dstate_push_constant_alloc(const struct ilo_dev_info *dev, ilo_cp_begin(cp, cmd_len); ilo_cp_write(cp, cmd | (cmd_len - 2)); - ilo_cp_write(cp, offset << GEN7_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT | + ilo_cp_write(cp, offset << GEN7_PCB_ALLOC_ANY_DW1_OFFSET__SHIFT | size); ilo_cp_end(cp); } @@ -1055,9 +1055,9 @@ gen7_emit_3DSTATE_SO_DECL_LIST(const struct ilo_dev_info *dev, if (num_dwords > 4) num_dwords = 4; - decl = buf << SO_DECL_OUTPUT_BUFFER_SLOT_SHIFT | - SO_DECL_HOLE_FLAG | - ((1 << num_dwords) - 1) << SO_DECL_COMPONENT_MASK_SHIFT; + decl = buf << GEN7_SO_DECL_OUTPUT_SLOT__SHIFT | + GEN7_SO_DECL_HOLE_FLAG | + ((1 << num_dwords) - 1) << GEN7_SO_DECL_COMPONENT_MASK__SHIFT; so_decls[num_entries++] = decl; buffer_offsets[buf] += num_dwords; @@ -1067,9 +1067,9 @@ gen7_emit_3DSTATE_SO_DECL_LIST(const struct ilo_dev_info *dev, mask = ((1 << so_info->output[i].num_components) - 1) << so_info->output[i].start_component; - decl = buf << SO_DECL_OUTPUT_BUFFER_SLOT_SHIFT | - reg << SO_DECL_REGISTER_INDEX_SHIFT | - mask << SO_DECL_COMPONENT_MASK_SHIFT; + decl = buf << GEN7_SO_DECL_OUTPUT_SLOT__SHIFT | + reg << GEN7_SO_DECL_REG_INDEX__SHIFT | + mask << GEN7_SO_DECL_COMPONENT_MASK__SHIFT; so_decls[num_entries++] = decl; buffer_selects |= 1 << buf; @@ -1091,14 +1091,14 @@ gen7_emit_3DSTATE_SO_DECL_LIST(const struct ilo_dev_info *dev, ilo_cp_begin(cp, cmd_len); ilo_cp_write(cp, cmd | (cmd_len - 2)); - ilo_cp_write(cp, 0 << SO_STREAM_TO_BUFFER_SELECTS_3_SHIFT | - 0 << SO_STREAM_TO_BUFFER_SELECTS_2_SHIFT | - 0 << SO_STREAM_TO_BUFFER_SELECTS_1_SHIFT | - buffer_selects << SO_STREAM_TO_BUFFER_SELECTS_0_SHIFT); - ilo_cp_write(cp, 0 << SO_NUM_ENTRIES_3_SHIFT | - 0 << SO_NUM_ENTRIES_2_SHIFT | - 0 << SO_NUM_ENTRIES_1_SHIFT | - num_entries << SO_NUM_ENTRIES_0_SHIFT); + ilo_cp_write(cp, 0 << GEN7_SO_DECL_DW1_STREAM3_BUFFER_SELECTS__SHIFT | + 0 << GEN7_SO_DECL_DW1_STREAM2_BUFFER_SELECTS__SHIFT | + 0 << GEN7_SO_DECL_DW1_STREAM1_BUFFER_SELECTS__SHIFT | + buffer_selects << GEN7_SO_DECL_DW1_STREAM0_BUFFER_SELECTS__SHIFT); + ilo_cp_write(cp, 0 << GEN7_SO_DECL_DW2_STREAM3_ENTRY_COUNT__SHIFT | + 0 << GEN7_SO_DECL_DW2_STREAM2_ENTRY_COUNT__SHIFT | + 0 << GEN7_SO_DECL_DW2_STREAM1_ENTRY_COUNT__SHIFT | + num_entries << GEN7_SO_DECL_DW2_STREAM0_ENTRY_COUNT__SHIFT); for (i = 0; i < num_entries; i++) { ilo_cp_write(cp, so_decls[i]); @@ -1128,7 +1128,7 @@ gen7_emit_3DSTATE_SO_BUFFER(const struct ilo_dev_info *dev, if (!so_target || !so_target->buffer) { ilo_cp_begin(cp, cmd_len); ilo_cp_write(cp, cmd | (cmd_len - 2)); - ilo_cp_write(cp, index << SO_BUFFER_INDEX_SHIFT); + ilo_cp_write(cp, index << GEN7_SO_BUF_DW1_INDEX__SHIFT); ilo_cp_write(cp, 0); ilo_cp_write(cp, 0); ilo_cp_end(cp); @@ -1147,7 +1147,7 @@ gen7_emit_3DSTATE_SO_BUFFER(const struct ilo_dev_info *dev, ilo_cp_begin(cp, cmd_len); ilo_cp_write(cp, cmd | (cmd_len - 2)); - ilo_cp_write(cp, index << SO_BUFFER_INDEX_SHIFT | + ilo_cp_write(cp, index << GEN7_SO_BUF_DW1_INDEX__SHIFT | stride); ilo_cp_write_bo(cp, base, buf->bo, INTEL_DOMAIN_RENDER, INTEL_DOMAIN_RENDER); ilo_cp_write_bo(cp, end, buf->bo, INTEL_DOMAIN_RENDER, INTEL_DOMAIN_RENDER); @@ -1164,10 +1164,10 @@ gen7_emit_3DPRIMITIVE(const struct ilo_dev_info *dev, const uint32_t cmd = ILO_GPE_CMD(0x3, 0x3, 0x00); const uint8_t cmd_len = 7; const int prim = (rectlist) ? - _3DPRIM_RECTLIST : ilo_gpe_gen6_translate_pipe_prim(info->mode); + GEN6_3DPRIM_RECTLIST : ilo_gpe_gen6_translate_pipe_prim(info->mode); const int vb_access = (info->indexed) ? - GEN7_3DPRIM_VERTEXBUFFER_ACCESS_RANDOM : - GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL; + GEN7_3DPRIM_DW1_ACCESS_RANDOM : + GEN7_3DPRIM_DW1_ACCESS_SEQUENTIAL; const uint32_t vb_start = info->start + ((info->indexed) ? ib->draw_start_offset : 0); diff --git a/src/gallium/drivers/ilo/ilo_screen.c b/src/gallium/drivers/ilo/ilo_screen.c index 8c2e04e220d..c368fe5ac9d 100644 --- a/src/gallium/drivers/ilo/ilo_screen.c +++ b/src/gallium/drivers/ilo/ilo_screen.c @@ -28,7 +28,7 @@ #include "util/u_format_s3tc.h" #include "vl/vl_decoder.h" #include "vl/vl_video_buffer.h" -#include "genhw/genhw.h" /* for TIMESTAMP */ +#include "genhw/genhw.h" /* for GEN6_REG_TIMESTAMP */ #include "intel_winsys.h" #include "ilo_context.h" @@ -425,7 +425,7 @@ ilo_get_param(struct pipe_screen *screen, enum pipe_cap param) case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK: return 0; case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE: - /* a BRW_SURFACE_BUFFER can have up to 2^27 elements */ + /* a GEN6_SURFTYPE_BUFFER can have up to 2^27 elements */ return 1 << 27; case PIPE_CAP_MAX_VIEWPORTS: return ILO_MAX_VIEWPORTS; @@ -501,7 +501,7 @@ ilo_get_timestamp(struct pipe_screen *screen) uint32_t dw[2]; } timestamp; - intel_winsys_read_reg(is->winsys, TIMESTAMP, ×tamp.val); + intel_winsys_read_reg(is->winsys, GEN6_REG_TIMESTAMP, ×tamp.val); /* * From the Ivy Bridge PRM, volume 1 part 3, page 107: diff --git a/src/gallium/drivers/ilo/ilo_shader.c b/src/gallium/drivers/ilo/ilo_shader.c index 480166a89b4..6182aa571c9 100644 --- a/src/gallium/drivers/ilo/ilo_shader.c +++ b/src/gallium/drivers/ilo/ilo_shader.c @@ -309,7 +309,7 @@ ilo_shader_variant_init(struct ilo_shader_variant *variant, /* * When non-nearest filter and PIPE_TEX_WRAP_CLAMP wrap mode is used, - * the HW wrap mode is set to BRW_TEXCOORDMODE_CLAMP_BORDER, and we need + * the HW wrap mode is set to GEN6_TEXCOORDMODE_CLAMP_BORDER, and we need * to manually saturate the texture coordinates. */ if (sampler) { diff --git a/src/gallium/drivers/ilo/shader/ilo_shader_fs.c b/src/gallium/drivers/ilo/shader/ilo_shader_fs.c index 817b12743bb..c7a6ff9faa6 100644 --- a/src/gallium/drivers/ilo/shader/ilo_shader_fs.c +++ b/src/gallium/drivers/ilo/shader/ilo_shader_fs.c @@ -42,7 +42,7 @@ struct fs_compile_context { struct toy_compiler tc; struct toy_tgsi tgsi; - enum brw_message_target const_cache; + int const_cache; int dispatch_mode; struct { @@ -218,7 +218,7 @@ fetch_attr(struct fs_compile_context *fcc, struct toy_dst dst, int slot) uv = tsrc(TOY_FILE_GRF, interp, 0); for (ch = 0; ch < 4; ch++) { - tc_add2(tc, BRW_OPCODE_PLN, real_dst[ch], + tc_add2(tc, GEN6_OPCODE_PLN, real_dst[ch], tsrc_rect(attr[ch], TOY_RECT_010), uv); } } @@ -273,15 +273,15 @@ fs_lower_opcode_tgsi_indirect_const(struct fs_compile_context *fcc, /* set offset */ inst = tc_MOV(tc, offset, real_src[0]); - inst->mask_ctrl = BRW_MASK_DISABLE; + inst->mask_ctrl = GEN6_MASKCTRL_NOMASK; switch (inst->exec_size) { - case BRW_EXECUTE_8: - simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8; + case GEN6_EXECSIZE_8: + simd_mode = GEN6_MSG_SAMPLER_SIMD8; param_size = 1; break; - case BRW_EXECUTE_16: - simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16; + case GEN6_EXECSIZE_16: + simd_mode = GEN6_MSG_SAMPLER_SIMD16; param_size = 2; break; default: @@ -293,13 +293,13 @@ fs_lower_opcode_tgsi_indirect_const(struct fs_compile_context *fcc, desc = tsrc_imm_mdesc_sampler(tc, param_size, param_size * 4, false, simd_mode, - GEN5_SAMPLER_MESSAGE_SAMPLE_LD, + GEN6_MSG_SAMPLER_LD, 0, ILO_WM_CONST_SURFACE(dim)); tmp = tdst(TOY_FILE_VRF, tc_alloc_vrf(tc, param_size * 4), 0); - inst = tc_SEND(tc, tmp, tsrc_from(offset), desc, BRW_SFID_SAMPLER); - inst->mask_ctrl = BRW_MASK_DISABLE; + inst = tc_SEND(tc, tmp, tsrc_from(offset), desc, GEN6_SFID_SAMPLER); + inst->mask_ctrl = GEN6_MASKCTRL_NOMASK; tdst_transpose(dst, real_dst); for (i = 0; i < 4; i++) { @@ -358,16 +358,16 @@ fs_lower_opcode_tgsi_const_gen6(struct fs_compile_context *fcc, /* set message header */ inst = tc_MOV(tc, header, r0); - inst->mask_ctrl = BRW_MASK_DISABLE; + inst->mask_ctrl = GEN6_MASKCTRL_NOMASK; /* set global offset */ inst = tc_MOV(tc, global_offset, idx); - inst->mask_ctrl = BRW_MASK_DISABLE; - inst->exec_size = BRW_EXECUTE_1; + inst->mask_ctrl = GEN6_MASKCTRL_NOMASK; + inst->exec_size = GEN6_EXECSIZE_1; inst->src[0].rect = TOY_RECT_010; - msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ; - msg_ctrl = BRW_DATAPORT_OWORD_BLOCK_1_OWORDLOW << 8; + msg_type = GEN6_MSG_DP_OWORD_BLOCK_READ; + msg_ctrl = GEN6_MSG_DP_OWORD_BLOCK_SIZE_1_LO; msg_len = 1; desc = tsrc_imm_mdesc_data_port(tc, false, msg_len, 1, true, false, @@ -411,19 +411,19 @@ fs_lower_opcode_tgsi_const_gen7(struct fs_compile_context *fcc, /* set offset */ inst = tc_MOV(tc, offset, tsrc_rect(idx, TOY_RECT_010)); - inst->exec_size = BRW_EXECUTE_8; - inst->mask_ctrl = BRW_MASK_DISABLE; + inst->exec_size = GEN6_EXECSIZE_8; + inst->mask_ctrl = GEN6_MASKCTRL_NOMASK; desc = tsrc_imm_mdesc_sampler(tc, 1, 1, false, - BRW_SAMPLER_SIMD_MODE_SIMD4X2, - GEN5_SAMPLER_MESSAGE_SAMPLE_LD, + GEN6_MSG_SAMPLER_SIMD4X2, + GEN6_MSG_SAMPLER_LD, 0, ILO_WM_CONST_SURFACE(dim)); tmp = tc_alloc_tmp(tc); - inst = tc_SEND(tc, tmp, tsrc_from(offset), desc, BRW_SFID_SAMPLER); - inst->exec_size = BRW_EXECUTE_8; - inst->mask_ctrl = BRW_MASK_DISABLE; + inst = tc_SEND(tc, tmp, tsrc_from(offset), desc, GEN6_SFID_SAMPLER); + inst->exec_size = GEN6_EXECSIZE_8; + inst->mask_ctrl = GEN6_MASKCTRL_NOMASK; tdst_transpose(dst, real_dst); for (i = 0; i < 4; i++) { @@ -579,25 +579,25 @@ fs_add_sampler_params_gen6(struct toy_compiler *tc, int msg_type, #define SAMPLER_PARAM(p) (tdst(TOY_FILE_MRF, base_mrf + (p) * param_size, 0)) switch (msg_type) { - case GEN5_SAMPLER_MESSAGE_SAMPLE: + case GEN6_MSG_SAMPLER_SAMPLE: for (i = 0; i < num_coords; i++) tc_MOV(tc, SAMPLER_PARAM(i), coords[i]); num_params = num_coords; break; - case GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS: - case GEN5_SAMPLER_MESSAGE_SAMPLE_LOD: + case GEN6_MSG_SAMPLER_SAMPLE_B: + case GEN6_MSG_SAMPLER_SAMPLE_L: for (i = 0; i < num_coords; i++) tc_MOV(tc, SAMPLER_PARAM(i), coords[i]); tc_MOV(tc, SAMPLER_PARAM(4), bias_or_lod); num_params = 5; break; - case GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE: + case GEN6_MSG_SAMPLER_SAMPLE_C: for (i = 0; i < num_coords; i++) tc_MOV(tc, SAMPLER_PARAM(i), coords[i]); tc_MOV(tc, SAMPLER_PARAM(4), ref_or_si); num_params = 5; break; - case GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS: + case GEN6_MSG_SAMPLER_SAMPLE_D: for (i = 0; i < num_coords; i++) tc_MOV(tc, SAMPLER_PARAM(i), coords[i]); for (i = 0; i < num_derivs; i++) { @@ -606,15 +606,15 @@ fs_add_sampler_params_gen6(struct toy_compiler *tc, int msg_type, } num_params = 4 + num_derivs * 2; break; - case GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE: - case GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE: + case GEN6_MSG_SAMPLER_SAMPLE_B_C: + case GEN6_MSG_SAMPLER_SAMPLE_L_C: for (i = 0; i < num_coords; i++) tc_MOV(tc, SAMPLER_PARAM(i), coords[i]); tc_MOV(tc, SAMPLER_PARAM(4), ref_or_si); tc_MOV(tc, SAMPLER_PARAM(5), bias_or_lod); num_params = 6; break; - case GEN5_SAMPLER_MESSAGE_SAMPLE_LD: + case GEN6_MSG_SAMPLER_LD: assert(num_coords <= 3); for (i = 0; i < num_coords; i++) @@ -623,7 +623,7 @@ fs_add_sampler_params_gen6(struct toy_compiler *tc, int msg_type, tc_MOV(tc, tdst_d(SAMPLER_PARAM(4)), ref_or_si); num_params = 5; break; - case GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO: + case GEN6_MSG_SAMPLER_RESINFO: tc_MOV(tc, tdst_d(SAMPLER_PARAM(0)), bias_or_lod); num_params = 1; break; @@ -652,25 +652,25 @@ fs_add_sampler_params_gen7(struct toy_compiler *tc, int msg_type, #define SAMPLER_PARAM(p) (tdst(TOY_FILE_MRF, base_mrf + (p) * param_size, 0)) switch (msg_type) { - case GEN5_SAMPLER_MESSAGE_SAMPLE: + case GEN6_MSG_SAMPLER_SAMPLE: for (i = 0; i < num_coords; i++) tc_MOV(tc, SAMPLER_PARAM(i), coords[i]); num_params = num_coords; break; - case GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS: - case GEN5_SAMPLER_MESSAGE_SAMPLE_LOD: + case GEN6_MSG_SAMPLER_SAMPLE_B: + case GEN6_MSG_SAMPLER_SAMPLE_L: tc_MOV(tc, SAMPLER_PARAM(0), bias_or_lod); for (i = 0; i < num_coords; i++) tc_MOV(tc, SAMPLER_PARAM(1 + i), coords[i]); num_params = 1 + num_coords; break; - case GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE: + case GEN6_MSG_SAMPLER_SAMPLE_C: tc_MOV(tc, SAMPLER_PARAM(0), ref_or_si); for (i = 0; i < num_coords; i++) tc_MOV(tc, SAMPLER_PARAM(1 + i), coords[i]); num_params = 1 + num_coords; break; - case GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS: + case GEN6_MSG_SAMPLER_SAMPLE_D: for (i = 0; i < num_coords; i++) { tc_MOV(tc, SAMPLER_PARAM(i * 3), coords[i]); if (i < num_derivs) { @@ -680,15 +680,15 @@ fs_add_sampler_params_gen7(struct toy_compiler *tc, int msg_type, } num_params = num_coords * 3 - ((num_coords > num_derivs) ? 2 : 0); break; - case GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE: - case GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE: + case GEN6_MSG_SAMPLER_SAMPLE_B_C: + case GEN6_MSG_SAMPLER_SAMPLE_L_C: tc_MOV(tc, SAMPLER_PARAM(0), ref_or_si); tc_MOV(tc, SAMPLER_PARAM(1), bias_or_lod); for (i = 0; i < num_coords; i++) tc_MOV(tc, SAMPLER_PARAM(2 + i), coords[i]); num_params = 2 + num_coords; break; - case GEN5_SAMPLER_MESSAGE_SAMPLE_LD: + case GEN6_MSG_SAMPLER_LD: assert(num_coords >= 1 && num_coords <= 3); tc_MOV(tc, tdst_d(SAMPLER_PARAM(0)), coords[0]); @@ -697,7 +697,7 @@ fs_add_sampler_params_gen7(struct toy_compiler *tc, int msg_type, tc_MOV(tc, tdst_d(SAMPLER_PARAM(1 + i)), coords[i]); num_params = 1 + num_coords; break; - case GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO: + case GEN6_MSG_SAMPLER_RESINFO: tc_MOV(tc, tdst_d(SAMPLER_PARAM(0)), bias_or_lod); num_params = 1; break; @@ -725,12 +725,12 @@ fs_prepare_tgsi_sampling(struct toy_compiler *tc, const struct toy_inst *inst, int sampler_src, param_size, i; switch (inst->exec_size) { - case BRW_EXECUTE_8: - simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8; + case GEN6_EXECSIZE_8: + simd_mode = GEN6_MSG_SAMPLER_SIMD8; param_size = 1; break; - case BRW_EXECUTE_16: - simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16; + case GEN6_EXECSIZE_16: + simd_mode = GEN6_MSG_SAMPLER_SIMD16; param_size = 2; break; default: @@ -787,25 +787,25 @@ fs_prepare_tgsi_sampling(struct toy_compiler *tc, const struct toy_inst *inst, if (ref_pos >= 0) { assert(ref_pos < 4); - msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE; + msg_type = GEN6_MSG_SAMPLER_SAMPLE_C; ref_or_si = coords[ref_pos]; } else { - msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE; + msg_type = GEN6_MSG_SAMPLER_SAMPLE; } break; case TOY_OPCODE_TGSI_TXD: if (ref_pos >= 0) { assert(ref_pos < 4); - msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE; + msg_type = GEN7_MSG_SAMPLER_SAMPLE_D_C; ref_or_si = coords[ref_pos]; if (tc->dev->gen < ILO_GEN(7.5)) tc_fail(tc, "TXD with shadow sampler not supported"); } else { - msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS; + msg_type = GEN6_MSG_SAMPLER_SAMPLE_D; } tsrc_transpose(inst->src[1], ddx); @@ -817,11 +817,11 @@ fs_prepare_tgsi_sampling(struct toy_compiler *tc, const struct toy_inst *inst, if (ref_pos >= 0) { assert(ref_pos < 3); - msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE; + msg_type = GEN6_MSG_SAMPLER_SAMPLE_C; ref_or_si = coords[ref_pos]; } else { - msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE; + msg_type = GEN6_MSG_SAMPLER_SAMPLE; } /* project the coordinates */ @@ -846,11 +846,11 @@ fs_prepare_tgsi_sampling(struct toy_compiler *tc, const struct toy_inst *inst, if (ref_pos >= 0) { assert(ref_pos < 3); - msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE; + msg_type = GEN6_MSG_SAMPLER_SAMPLE_B_C; ref_or_si = coords[ref_pos]; } else { - msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS; + msg_type = GEN6_MSG_SAMPLER_SAMPLE_B; } bias_or_lod = coords[3]; @@ -859,17 +859,17 @@ fs_prepare_tgsi_sampling(struct toy_compiler *tc, const struct toy_inst *inst, if (ref_pos >= 0) { assert(ref_pos < 3); - msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE; + msg_type = GEN6_MSG_SAMPLER_SAMPLE_L_C; ref_or_si = coords[ref_pos]; } else { - msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD; + msg_type = GEN6_MSG_SAMPLER_SAMPLE_L; } bias_or_lod = coords[3]; break; case TOY_OPCODE_TGSI_TXF: - msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD; + msg_type = GEN6_MSG_SAMPLER_LD; switch (inst->tex.target) { case TGSI_TEXTURE_2D_MSAA: @@ -901,12 +901,12 @@ fs_prepare_tgsi_sampling(struct toy_compiler *tc, const struct toy_inst *inst, sampler_src = 1; break; case TOY_OPCODE_TGSI_TXQ: - msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO; + msg_type = GEN6_MSG_SAMPLER_RESINFO; num_coords = 0; bias_or_lod = coords[0]; break; case TOY_OPCODE_TGSI_TXQ_LZ: - msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO; + msg_type = GEN6_MSG_SAMPLER_RESINFO; num_coords = 0; sampler_src = 0; break; @@ -914,7 +914,7 @@ fs_prepare_tgsi_sampling(struct toy_compiler *tc, const struct toy_inst *inst, if (ref_pos >= 0) { assert(ref_pos < 5); - msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE; + msg_type = GEN6_MSG_SAMPLER_SAMPLE_C; if (ref_pos >= 4) { struct toy_src src1[4]; @@ -926,7 +926,7 @@ fs_prepare_tgsi_sampling(struct toy_compiler *tc, const struct toy_inst *inst, } } else { - msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE; + msg_type = GEN6_MSG_SAMPLER_SAMPLE; } sampler_src = 2; @@ -935,11 +935,11 @@ fs_prepare_tgsi_sampling(struct toy_compiler *tc, const struct toy_inst *inst, if (ref_pos >= 0) { assert(ref_pos < 4); - msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE; + msg_type = GEN6_MSG_SAMPLER_SAMPLE_B_C; ref_or_si = coords[ref_pos]; } else { - msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS; + msg_type = GEN6_MSG_SAMPLER_SAMPLE_B; } { @@ -954,11 +954,11 @@ fs_prepare_tgsi_sampling(struct toy_compiler *tc, const struct toy_inst *inst, if (ref_pos >= 0) { assert(ref_pos < 4); - msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE; + msg_type = GEN6_MSG_SAMPLER_SAMPLE_L_C; ref_or_si = coords[ref_pos]; } else { - msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD; + msg_type = GEN6_MSG_SAMPLER_SAMPLE_L; } { @@ -998,9 +998,9 @@ fs_prepare_tgsi_sampling(struct toy_compiler *tc, const struct toy_inst *inst, tc_alloc_tmp4(tc, tmp); tc_SEL(tc, tmp[3], tsrc_absolute(coords[0]), - tsrc_absolute(coords[1]), BRW_CONDITIONAL_GE); + tsrc_absolute(coords[1]), GEN6_COND_GE); tc_SEL(tc, tmp[3], tsrc_from(tmp[3]), - tsrc_absolute(coords[2]), BRW_CONDITIONAL_GE); + tsrc_absolute(coords[2]), GEN6_COND_GE); tc_INV(tc, tmp[3], tsrc_from(tmp[3])); for (i = 0; i < 3; i++) { @@ -1044,8 +1044,8 @@ fs_prepare_tgsi_sampling(struct toy_compiler *tc, const struct toy_inst *inst, min = tsrc_imm_f(0.0f); max = tsrc_imm_f(2048.0f); - tc_SEL(tc, tmp, coords[i], min, BRW_CONDITIONAL_G); - tc_SEL(tc, tmp, tsrc_from(tmp), max, BRW_CONDITIONAL_L); + tc_SEL(tc, tmp, coords[i], min, GEN6_COND_G); + tc_SEL(tc, tmp, tsrc_from(tmp), max, GEN6_COND_L); coords[i] = tsrc_from(tmp); } @@ -1117,7 +1117,7 @@ fs_lower_opcode_tgsi_sampling(struct fs_compile_context *fcc, break; } - toy_compiler_lower_to_send(tc, inst, false, BRW_SFID_SAMPLER); + toy_compiler_lower_to_send(tc, inst, false, GEN6_SFID_SAMPLER); inst->src[0] = tsrc(TOY_FILE_MRF, fcc->first_free_mrf, 0); inst->src[1] = desc; for (i = 2; i < Elements(inst->src); i++) @@ -1188,7 +1188,7 @@ fs_lower_opcode_derivative(struct toy_compiler *tc, struct toy_inst *inst) * * dst = src.zzww - src.xxyy * - * But since we are in BRW_ALIGN_1, swizzling does not work and we have to + * But since we are in GEN6_ALIGN_1, swizzling does not work and we have to * play with the region parameters. */ if (inst->opcode == TOY_OPCODE_DDX) { @@ -1221,7 +1221,7 @@ fs_lower_opcode_fb_write(struct toy_compiler *tc, struct toy_inst *inst) { /* fs_write_fb() has set up the message registers */ toy_compiler_lower_to_send(tc, inst, true, - GEN6_SFID_DATAPORT_RENDER_CACHE); + GEN6_SFID_DP_RC); } static void @@ -1235,24 +1235,24 @@ fs_lower_opcode_kil(struct toy_compiler *tc, struct toy_inst *inst) pixel_mask_dst = tdst_uw(tdst(TOY_FILE_GRF, 1, 7 * 4)); pixel_mask = tsrc_rect(tsrc_from(pixel_mask_dst), TOY_RECT_010); - f0 = tsrc_rect(tsrc_uw(tsrc(TOY_FILE_ARF, BRW_ARF_FLAG, 0)), TOY_RECT_010); + f0 = tsrc_rect(tsrc_uw(tsrc(TOY_FILE_ARF, GEN6_ARF_F0, 0)), TOY_RECT_010); /* KILL or KILL_IF */ if (tsrc_is_null(inst->src[0])) { struct toy_src dummy = tsrc_uw(tsrc(TOY_FILE_GRF, 0, 0)); - struct toy_dst f0_dst = tdst_uw(tdst(TOY_FILE_ARF, BRW_ARF_FLAG, 0)); + struct toy_dst f0_dst = tdst_uw(tdst(TOY_FILE_ARF, GEN6_ARF_F0, 0)); /* create a mask that masks out all pixels */ tmp = tc_MOV(tc, f0_dst, tsrc_rect(tsrc_imm_uw(0xffff), TOY_RECT_010)); - tmp->exec_size = BRW_EXECUTE_1; - tmp->mask_ctrl = BRW_MASK_DISABLE; + tmp->exec_size = GEN6_EXECSIZE_1; + tmp->mask_ctrl = GEN6_MASKCTRL_NOMASK; - tc_CMP(tc, tdst_null(), dummy, dummy, BRW_CONDITIONAL_NEQ); + tc_CMP(tc, tdst_null(), dummy, dummy, GEN6_COND_NZ); /* swapping the two src operands breaks glBitmap()!? */ tmp = tc_AND(tc, pixel_mask_dst, f0, pixel_mask); - tmp->exec_size = BRW_EXECUTE_1; - tmp->mask_ctrl = BRW_MASK_DISABLE; + tmp->exec_size = GEN6_EXECSIZE_1; + tmp->mask_ctrl = GEN6_MASKCTRL_NOMASK; } else { struct toy_src src[4]; @@ -1262,12 +1262,12 @@ fs_lower_opcode_kil(struct toy_compiler *tc, struct toy_inst *inst) /* mask out killed pixels */ for (i = 0; i < 4; i++) { tc_CMP(tc, tdst_null(), src[i], tsrc_imm_f(0.0f), - BRW_CONDITIONAL_GE); + GEN6_COND_GE); /* swapping the two src operands breaks glBitmap()!? */ tmp = tc_AND(tc, pixel_mask_dst, f0, pixel_mask); - tmp->exec_size = BRW_EXECUTE_1; - tmp->mask_ctrl = BRW_MASK_DISABLE; + tmp->exec_size = GEN6_EXECSIZE_1; + tmp->mask_ctrl = GEN6_MASKCTRL_NOMASK; } } @@ -1471,13 +1471,13 @@ fs_write_fb(struct fs_compile_context *fcc) struct toy_inst *inst; inst = tc_MOV(tc, header, r0); - inst->mask_ctrl = BRW_MASK_DISABLE; + inst->mask_ctrl = GEN6_MASKCTRL_NOMASK; base_mrf += fcc->num_grf_per_vrf; /* this is a two-register header */ - if (fcc->dispatch_mode == GEN6_WM_8_DISPATCH_ENABLE) { + if (fcc->dispatch_mode == GEN6_WM_DW5_8_PIXEL_DISPATCH) { inst = tc_MOV(tc, tdst_offset(header, 1, 0), tsrc_offset(r0, 1, 0)); - inst->mask_ctrl = BRW_MASK_DISABLE; + inst->mask_ctrl = GEN6_MASKCTRL_NOMASK; base_mrf += fcc->num_grf_per_vrf; } @@ -1531,8 +1531,8 @@ fs_write_fb(struct fs_compile_context *fcc) struct toy_inst *inst; inst = tc_MOV(tc, tdst_offset(header, 0, 2), tsrc_imm_ud(cbuf)); - inst->mask_ctrl = BRW_MASK_DISABLE; - inst->exec_size = BRW_EXECUTE_1; + inst->mask_ctrl = GEN6_MASKCTRL_NOMASK; + inst->exec_size = GEN6_EXECSIZE_1; inst->src[0].rect = TOY_RECT_010; } @@ -1558,9 +1558,9 @@ fs_write_fb(struct fs_compile_context *fcc) mrf += fcc->num_grf_per_vrf; } - msg_type = (fcc->dispatch_mode == GEN6_WM_16_DISPATCH_ENABLE) ? - BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE : - BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01; + msg_type = (fcc->dispatch_mode == GEN6_WM_DW5_16_PIXEL_DISPATCH) ? + GEN6_MSG_DP_RT_MODE_SIMD16 >> 8 : + GEN6_MSG_DP_RT_MODE_SIMD8_LO >> 8; ctrl = (cbuf == num_cbufs - 1) << 12 | msg_type << 8; @@ -1568,7 +1568,7 @@ fs_write_fb(struct fs_compile_context *fcc) desc = tsrc_imm_mdesc_data_port(tc, cbuf == num_cbufs - 1, mrf - fcc->first_free_mrf, 0, header_present, false, - GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE, + GEN6_MSG_DP_RT_WRITE, ctrl, ILO_WM_DRAW_SURFACE(cbuf)); tc_add2(tc, TOY_OPCODE_FB_WRITE, tdst_null(), @@ -1628,11 +1628,11 @@ fs_setup_shader_in(struct ilo_shader *sh, const struct toy_tgsi *tgsi, if (tgsi->inputs[i].centroid) { sh->in.barycentric_interpolation_mode |= - 1 << BRW_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC; + GEN6_INTERP_NONPERSPECTIVE_CENTROID; } else { sh->in.barycentric_interpolation_mode |= - 1 << BRW_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC; + GEN6_INTERP_NONPERSPECTIVE_PIXEL; } break; case TGSI_INTERPOLATE_COLOR: @@ -1644,11 +1644,11 @@ fs_setup_shader_in(struct ilo_shader *sh, const struct toy_tgsi *tgsi, case TGSI_INTERPOLATE_PERSPECTIVE: if (tgsi->inputs[i].centroid) { sh->in.barycentric_interpolation_mode |= - 1 << BRW_WM_PERSPECTIVE_CENTROID_BARYCENTRIC; + GEN6_INTERP_PERSPECTIVE_CENTROID; } else { sh->in.barycentric_interpolation_mode |= - 1 << BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC; + GEN6_INTERP_PERSPECTIVE_PIXEL; } break; default: @@ -1669,40 +1669,40 @@ fs_setup_payloads(struct fs_compile_context *fcc) grf++; /* r1-r2: coordinates and etc. */ - grf += (fcc->dispatch_mode == GEN6_WM_32_DISPATCH_ENABLE) ? 2 : 1; + grf += (fcc->dispatch_mode == GEN6_WM_DW5_32_PIXEL_DISPATCH) ? 2 : 1; for (i = 0; i < Elements(fcc->payloads); i++) { const int reg_scale = - (fcc->dispatch_mode == GEN6_WM_8_DISPATCH_ENABLE) ? 1 : 2; + (fcc->dispatch_mode == GEN6_WM_DW5_8_PIXEL_DISPATCH) ? 1 : 2; /* r3-r26 or r32-r55: barycentric interpolation parameters */ if (sh->in.barycentric_interpolation_mode & - (1 << BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC)) { + (GEN6_INTERP_PERSPECTIVE_PIXEL)) { fcc->payloads[i].interp_perspective_pixel = grf; grf += 2 * reg_scale; } if (sh->in.barycentric_interpolation_mode & - (1 << BRW_WM_PERSPECTIVE_CENTROID_BARYCENTRIC)) { + (GEN6_INTERP_PERSPECTIVE_CENTROID)) { fcc->payloads[i].interp_perspective_centroid = grf; grf += 2 * reg_scale; } if (sh->in.barycentric_interpolation_mode & - (1 << BRW_WM_PERSPECTIVE_SAMPLE_BARYCENTRIC)) { + (GEN6_INTERP_PERSPECTIVE_SAMPLE)) { fcc->payloads[i].interp_perspective_sample = grf; grf += 2 * reg_scale; } if (sh->in.barycentric_interpolation_mode & - (1 << BRW_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC)) { + (GEN6_INTERP_NONPERSPECTIVE_PIXEL)) { fcc->payloads[i].interp_nonperspective_pixel = grf; grf += 2 * reg_scale; } if (sh->in.barycentric_interpolation_mode & - (1 << BRW_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC)) { + (GEN6_INTERP_NONPERSPECTIVE_CENTROID)) { fcc->payloads[i].interp_nonperspective_centroid = grf; grf += 2 * reg_scale; } if (sh->in.barycentric_interpolation_mode & - (1 << BRW_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC)) { + (GEN6_INTERP_NONPERSPECTIVE_SAMPLE)) { fcc->payloads[i].interp_nonperspective_sample = grf; grf += 2 * reg_scale; } @@ -1725,7 +1725,7 @@ fs_setup_payloads(struct fs_compile_context *fcc) grf++; } - if (fcc->dispatch_mode != GEN6_WM_32_DISPATCH_ENABLE) + if (fcc->dispatch_mode != GEN6_WM_DW5_32_PIXEL_DISPATCH) break; } @@ -1784,16 +1784,16 @@ fs_setup(struct fs_compile_context *fcc, toy_compiler_init(&fcc->tc, state->info.dev); - fcc->dispatch_mode = GEN6_WM_8_DISPATCH_ENABLE; + fcc->dispatch_mode = GEN6_WM_DW5_8_PIXEL_DISPATCH; - fcc->tc.templ.access_mode = BRW_ALIGN_1; - if (fcc->dispatch_mode == GEN6_WM_16_DISPATCH_ENABLE) { - fcc->tc.templ.qtr_ctrl = GEN6_COMPRESSION_1H; - fcc->tc.templ.exec_size = BRW_EXECUTE_16; + fcc->tc.templ.access_mode = GEN6_ALIGN_1; + if (fcc->dispatch_mode == GEN6_WM_DW5_16_PIXEL_DISPATCH) { + fcc->tc.templ.qtr_ctrl = GEN6_QTRCTRL_1H; + fcc->tc.templ.exec_size = GEN6_EXECSIZE_16; } else { - fcc->tc.templ.qtr_ctrl = GEN6_COMPRESSION_1Q; - fcc->tc.templ.exec_size = BRW_EXECUTE_8; + fcc->tc.templ.qtr_ctrl = GEN6_QTRCTRL_1Q; + fcc->tc.templ.exec_size = GEN6_EXECSIZE_8; } fcc->tc.rect_linear_width = 8; @@ -1802,7 +1802,7 @@ fs_setup(struct fs_compile_context *fcc, * The classic driver uses the sampler cache (gen6) or the data cache * (gen7). Why? */ - fcc->const_cache = GEN6_SFID_DATAPORT_CONSTANT_CACHE; + fcc->const_cache = GEN6_SFID_DP_CC; if (!fs_setup_tgsi(&fcc->tc, state->info.tokens, &fcc->tgsi)) { toy_compiler_cleanup(&fcc->tc); @@ -1845,9 +1845,9 @@ fs_setup(struct fs_compile_context *fcc, fcc->first_free_mrf = 1; fcc->last_free_mrf = 15; - /* instructions are compressed with BRW_EXECUTE_16 */ + /* instructions are compressed with GEN6_EXECSIZE_16 */ fcc->num_grf_per_vrf = - (fcc->dispatch_mode == GEN6_WM_16_DISPATCH_ENABLE) ? 2 : 1; + (fcc->dispatch_mode == GEN6_WM_DW5_16_PIXEL_DISPATCH) ? 2 : 1; if (fcc->tc.dev->gen >= ILO_GEN(7)) { fcc->last_free_grf -= 15; @@ -1858,7 +1858,7 @@ fs_setup(struct fs_compile_context *fcc, fcc->shader->in.start_grf = fcc->first_const_grf; fcc->shader->has_kill = fcc->tgsi.uses_kill; fcc->shader->dispatch_16 = - (fcc->dispatch_mode == GEN6_WM_16_DISPATCH_ENABLE); + (fcc->dispatch_mode == GEN6_WM_DW5_16_PIXEL_DISPATCH); return true; } diff --git a/src/gallium/drivers/ilo/shader/ilo_shader_gs.c b/src/gallium/drivers/ilo/shader/ilo_shader_gs.c index 0741754189f..91c300bae9e 100644 --- a/src/gallium/drivers/ilo/shader/ilo_shader_gs.c +++ b/src/gallium/drivers/ilo/shader/ilo_shader_gs.c @@ -114,8 +114,8 @@ gs_COPY8(struct toy_compiler *tc, struct toy_dst dst, struct toy_src src) struct toy_inst *inst; inst = tc_MOV(tc, dst, src); - inst->exec_size = BRW_EXECUTE_8; - inst->mask_ctrl = BRW_MASK_DISABLE; + inst->exec_size = GEN6_EXECSIZE_8; + inst->mask_ctrl = GEN6_MASKCTRL_NOMASK; } static void @@ -128,8 +128,8 @@ gs_COPY4(struct toy_compiler *tc, inst = tc_MOV(tc, tdst_offset(dst, 0, dst_ch), tsrc_offset(src, 0, src_ch)); - inst->exec_size = BRW_EXECUTE_4; - inst->mask_ctrl = BRW_MASK_DISABLE; + inst->exec_size = GEN6_EXECSIZE_4; + inst->mask_ctrl = GEN6_MASKCTRL_NOMASK; } static void @@ -142,8 +142,8 @@ gs_COPY1(struct toy_compiler *tc, inst = tc_MOV(tc, tdst_offset(dst, 0, dst_ch), tsrc_rect(tsrc_offset(src, 0, src_ch), TOY_RECT_010)); - inst->exec_size = BRW_EXECUTE_1; - inst->mask_ctrl = BRW_MASK_DISABLE; + inst->exec_size = GEN6_EXECSIZE_1; + inst->mask_ctrl = GEN6_MASKCTRL_NOMASK; } static void @@ -161,13 +161,13 @@ gs_init_vars(struct gs_compile_context *gcc) gcc->vars.prim_end = false; switch (gcc->out_vue_min_count) { case 1: - gcc->vars.prim_type = _3DPRIM_POINTLIST; + gcc->vars.prim_type = GEN6_3DPRIM_POINTLIST; break; case 2: - gcc->vars.prim_type = _3DPRIM_LINESTRIP; + gcc->vars.prim_type = GEN6_3DPRIM_LINESTRIP; break; case 3: - gcc->vars.prim_type = _3DPRIM_TRISTRIP; + gcc->vars.prim_type = GEN6_3DPRIM_TRISTRIP; break; } @@ -212,11 +212,11 @@ gs_write_so(struct gs_compile_context *gcc, desc = tsrc_imm_mdesc_data_port(tc, false, 1, send_write_commit_message, true, send_write_commit_message, - GEN6_DATAPORT_WRITE_MESSAGE_STREAMED_VB_WRITE, 0, + GEN6_MSG_DP_SVB_WRITE, 0, binding_table_index); tc_SEND(tc, dst, tsrc_from(mrf_header), desc, - GEN6_SFID_DATAPORT_RENDER_CACHE); + GEN6_SFID_DP_RC); } static void @@ -262,12 +262,12 @@ gs_write_vue(struct gs_compile_context *gcc, if (complete) { desc = tsrc_imm_mdesc_urb(tc, eot, msg_len, !eot, true, true, !eot, - BRW_URB_SWIZZLE_NONE, sent, 0); + false, sent, 0); } else { desc = tsrc_imm_mdesc_urb(tc, false, msg_len, 0, false, true, false, - BRW_URB_SWIZZLE_NONE, sent, 0); + false, sent, 0); } tc_add2(tc, TOY_OPCODE_URB_WRITE, @@ -323,9 +323,9 @@ gs_ff_sync(struct gs_compile_context *gcc, struct toy_dst dst, allocate = true; desc = tsrc_imm_mdesc_urb(tc, false, 1, 1, false, false, allocate, - BRW_URB_SWIZZLE_NONE, 0, 1); + false, 0, 1); - tc_SEND(tc, dst, tsrc_from(mrf_header), desc, BRW_SFID_URB); + tc_SEND(tc, dst, tsrc_from(mrf_header), desc, GEN6_SFID_URB); } static void @@ -341,7 +341,7 @@ gs_discard(struct gs_compile_context *gcc) desc = tsrc_imm_mdesc_urb(tc, true, 1, 0, true, false, false, - BRW_URB_SWIZZLE_NONE, 0, 0); + false, 0, 0); tc_add2(tc, TOY_OPCODE_URB_WRITE, tdst_null(), tsrc_from(mrf_header), desc); @@ -374,7 +374,7 @@ gs_lower_opcode_emit_so_dynamic(struct gs_compile_context *gcc) tc_IF(tc, tdst_null(), tsrc_from(gcc->dynamic_data.num_vertices_in_prim), tsrc_imm_d(gcc->out_vue_min_count), - BRW_CONDITIONAL_GE); + GEN6_COND_GE); { tc_ADD(tc, gcc->vars.tmp, tsrc_from(gcc->vars.so_index), tsrc_imm_d(0x03020100)); @@ -407,7 +407,7 @@ gs_lower_opcode_emit_vue_static(struct gs_compile_context *gcc) tsrc_imm_d(gcc->vars.prim_type << 2 | gcc->vars.prim_start << 1 | gcc->vars.prim_end)); - inst2->exec_size = BRW_EXECUTE_1; + inst2->exec_size = GEN6_EXECSIZE_1; inst2->src[0] = tsrc_rect(inst2->src[0], TOY_RECT_010); inst2->src[1] = tsrc_rect(inst2->src[1], TOY_RECT_010); } @@ -443,8 +443,8 @@ gs_lower_opcode_emit_so_static(struct gs_compile_context *gcc) return; inst = tc_MOV(tc, tdst_w(gcc->vars.tmp), tsrc_imm_v(0x03020100)); - inst->exec_size = BRW_EXECUTE_8; - inst->mask_ctrl = BRW_MASK_DISABLE; + inst->exec_size = GEN6_EXECSIZE_8; + inst->mask_ctrl = GEN6_MASKCTRL_NOMASK; tc_ADD(tc, tdst_d(gcc->vars.tmp), tsrc_from(tdst_d(gcc->vars.tmp)), tsrc_rect(tsrc_from(gcc->vars.so_index), TOY_RECT_010)); @@ -452,7 +452,7 @@ gs_lower_opcode_emit_so_static(struct gs_compile_context *gcc) tc_IF(tc, tdst_null(), tsrc_rect(tsrc_offset(tsrc_from(tdst_d(gcc->vars.tmp)), 0, gcc->out_vue_min_count - 1), TOY_RECT_010), tsrc_rect(tsrc_offset(gcc->payload.svbi, 0, 4), TOY_RECT_010), - BRW_CONDITIONAL_LE); + GEN6_COND_LE); { for (i = 0; i < gcc->out_vue_min_count; i++) { for (j = 0; j < gcc->so_info->num_outputs; j++) { @@ -594,31 +594,31 @@ gs_lower_opcode_tgsi_in(struct gs_compile_context *gcc, return; } - /* fix vertex ordering for _3DPRIM_TRISTRIP_REVERSE */ + /* fix vertex ordering for GEN6_3DPRIM_TRISTRIP_REVERSE */ if (gcc->in_vue_count == 3 && dim < 2) { struct toy_inst *inst; /* get PrimType */ inst = tc_AND(tc, tdst_d(gcc->vars.tmp), tsrc_offset(gcc->payload.header, 0, 2), tsrc_imm_d(0x1f)); - inst->exec_size = BRW_EXECUTE_1; + inst->exec_size = GEN6_EXECSIZE_1; inst->src[0] = tsrc_rect(inst->src[0], TOY_RECT_010); inst->src[1] = tsrc_rect(inst->src[1], TOY_RECT_010); inst = tc_CMP(tc, tdst_null(), tsrc_from(tdst_d(gcc->vars.tmp)), - tsrc_imm_d(_3DPRIM_TRISTRIP_REVERSE), BRW_CONDITIONAL_NEQ); + tsrc_imm_d(GEN6_3DPRIM_TRISTRIP_REVERSE), GEN6_COND_NZ); inst->src[0] = tsrc_rect(inst->src[0], TOY_RECT_010); attr = tsrc_offset(gcc->payload.vues[dim], reg, subreg); inst = tc_MOV(tc, dst, attr); - inst->pred_ctrl = BRW_PREDICATE_NORMAL; + inst->pred_ctrl = GEN6_PREDCTRL_NORMAL; - /* swap IN[0] and IN[1] for _3DPRIM_TRISTRIP_REVERSE */ + /* swap IN[0] and IN[1] for GEN6_3DPRIM_TRISTRIP_REVERSE */ dim = !dim; attr = tsrc_offset(gcc->payload.vues[dim], reg, subreg); inst = tc_MOV(tc, dst, attr); - inst->pred_ctrl = BRW_PREDICATE_NORMAL; + inst->pred_ctrl = GEN6_PREDCTRL_NORMAL; inst->pred_inv = true; } else { @@ -645,7 +645,7 @@ gs_lower_opcode_tgsi_imm(struct gs_compile_context *gcc, inst = tc_MOV(&gcc->tc, tdst_writemask(tdst_ud(dst), 1 << ch), tsrc_imm_ud(imm[ch])); - inst->access_mode = BRW_ALIGN_16; + inst->access_mode = GEN6_ALIGN_16; } } @@ -773,7 +773,7 @@ gs_lower_virtual_opcodes(struct gs_compile_context *gcc) toy_compiler_lower_math(tc, inst); break; case TOY_OPCODE_URB_WRITE: - toy_compiler_lower_to_send(tc, inst, false, BRW_SFID_URB); + toy_compiler_lower_to_send(tc, inst, false, GEN6_SFID_URB); break; default: if (inst->opcode > 127) @@ -798,16 +798,16 @@ get_num_prims_static(struct gs_compile_context *gcc) tc_head(tc); while ((inst = tc_next_no_skip(tc)) != NULL) { switch (inst->opcode) { - case BRW_OPCODE_IF: + case GEN6_OPCODE_IF: if_depth++; break; - case BRW_OPCODE_ENDIF: + case GEN6_OPCODE_ENDIF: if_depth--; break; case TOY_OPCODE_DO: do_depth++; break; - case BRW_OPCODE_WHILE: + case GEN6_OPCODE_WHILE: do_depth--; break; case TOY_OPCODE_EMIT: @@ -1265,8 +1265,8 @@ gs_setup(struct gs_compile_context *gcc, gcc->write_so = (state->info.stream_output.num_outputs > 0); gcc->write_vue = !gcc->variant->u.gs.rasterizer_discard; - gcc->tc.templ.access_mode = BRW_ALIGN_16; - gcc->tc.templ.exec_size = BRW_EXECUTE_4; + gcc->tc.templ.access_mode = GEN6_ALIGN_16; + gcc->tc.templ.exec_size = GEN6_EXECSIZE_4; gcc->tc.rect_linear_width = 4; if (state->info.tokens) { @@ -1331,7 +1331,7 @@ gs_setup(struct gs_compile_context *gcc, } } - gcc->tc.templ.access_mode = BRW_ALIGN_1; + gcc->tc.templ.access_mode = GEN6_ALIGN_1; gs_setup_shader_in(gcc->shader, gcc->variant); gs_setup_shader_out(gcc->shader, &gcc->tgsi, false, gcc->output_map); diff --git a/src/gallium/drivers/ilo/shader/ilo_shader_vs.c b/src/gallium/drivers/ilo/shader/ilo_shader_vs.c index c20ecc6f6a2..c8a59e4d2d4 100644 --- a/src/gallium/drivers/ilo/shader/ilo_shader_vs.c +++ b/src/gallium/drivers/ilo/shader/ilo_shader_vs.c @@ -41,7 +41,7 @@ struct vs_compile_context { struct toy_compiler tc; struct toy_tgsi tgsi; - enum brw_message_target const_cache; + int const_cache; int output_map[PIPE_MAX_SHADER_OUTPUTS]; @@ -121,13 +121,13 @@ vs_lower_opcode_tgsi_const_gen6(struct vs_compile_context *vcc, /* set message header */ inst = tc_MOV(tc, header, r0); - inst->mask_ctrl = BRW_MASK_DISABLE; + inst->mask_ctrl = GEN6_MASKCTRL_NOMASK; /* set block offsets */ tc_MOV(tc, block_offsets, idx); - msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ; - msg_ctrl = BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD << 8;; + msg_type = GEN6_MSG_DP_OWORD_DUAL_BLOCK_READ; + msg_ctrl = GEN6_MSG_DP_OWORD_DUAL_BLOCK_SIZE_1;; msg_len = 2; desc = tsrc_imm_mdesc_data_port(tc, false, msg_len, 1, true, false, @@ -160,12 +160,12 @@ vs_lower_opcode_tgsi_const_gen7(struct vs_compile_context *vcc, tc_MOV(tc, offset, idx); desc = tsrc_imm_mdesc_sampler(tc, 1, 1, false, - BRW_SAMPLER_SIMD_MODE_SIMD4X2, - GEN5_SAMPLER_MESSAGE_SAMPLE_LD, + GEN6_MSG_SAMPLER_SIMD4X2, + GEN6_MSG_SAMPLER_LD, 0, ILO_VS_CONST_SURFACE(dim)); - tc_SEND(tc, dst, tsrc_from(offset), desc, BRW_SFID_SAMPLER); + tc_SEND(tc, dst, tsrc_from(offset), desc, GEN6_SFID_SAMPLER); } static void @@ -334,12 +334,12 @@ vs_add_sampler_params(struct toy_compiler *tc, int msg_type, int base_mrf, m[i] = tdst(TOY_FILE_MRF, base_mrf + i, 0); switch (msg_type) { - case GEN5_SAMPLER_MESSAGE_SAMPLE_LOD: + case GEN6_MSG_SAMPLER_SAMPLE_L: tc_MOV(tc, tdst_writemask(m[0], coords_writemask), coords); tc_MOV(tc, tdst_writemask(m[1], TOY_WRITEMASK_X), bias_or_lod); num_params = 5; break; - case GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS: + case GEN6_MSG_SAMPLER_SAMPLE_D: tc_MOV(tc, tdst_writemask(m[0], coords_writemask), coords); tc_MOV(tc, tdst_writemask(m[1], TOY_WRITEMASK_XZ), tsrc_swizzle(ddx, 0, 0, 1, 1)); @@ -353,13 +353,13 @@ vs_add_sampler_params(struct toy_compiler *tc, int msg_type, int base_mrf, } num_params = 4 + num_derivs * 2; break; - case GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE: + case GEN6_MSG_SAMPLER_SAMPLE_L_C: tc_MOV(tc, tdst_writemask(m[0], coords_writemask), coords); tc_MOV(tc, tdst_writemask(m[1], TOY_WRITEMASK_X), ref_or_si); tc_MOV(tc, tdst_writemask(m[1], TOY_WRITEMASK_Y), bias_or_lod); num_params = 6; break; - case GEN5_SAMPLER_MESSAGE_SAMPLE_LD: + case GEN6_MSG_SAMPLER_LD: assert(num_coords <= 3); tc_MOV(tc, tdst_writemask(tdst_d(m[0]), coords_writemask), coords); tc_MOV(tc, tdst_writemask(tdst_d(m[0]), TOY_WRITEMASK_W), bias_or_lod); @@ -371,7 +371,7 @@ vs_add_sampler_params(struct toy_compiler *tc, int msg_type, int base_mrf, num_params = 5; } break; - case GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO: + case GEN6_MSG_SAMPLER_RESINFO: tc_MOV(tc, tdst_writemask(tdst_d(m[0]), TOY_WRITEMASK_X), bias_or_lod); num_params = 1; break; @@ -396,7 +396,7 @@ vs_prepare_tgsi_sampling(struct toy_compiler *tc, const struct toy_inst *inst, int num_coords, ref_pos, num_derivs; int sampler_src; - simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD4X2; + simd_mode = GEN6_MSG_SAMPLER_SIMD4X2; coords = inst->src[0]; ddx = tsrc_null(); @@ -414,14 +414,14 @@ vs_prepare_tgsi_sampling(struct toy_compiler *tc, const struct toy_inst *inst, if (ref_pos >= 0) { assert(ref_pos < 4); - msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE; + msg_type = GEN7_MSG_SAMPLER_SAMPLE_D_C; ref_or_si = tsrc_swizzle1(coords, ref_pos); if (tc->dev->gen < ILO_GEN(7.5)) tc_fail(tc, "TXD with shadow sampler not supported"); } else { - msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS; + msg_type = GEN6_MSG_SAMPLER_SAMPLE_D; } ddx = inst->src[1]; @@ -433,17 +433,17 @@ vs_prepare_tgsi_sampling(struct toy_compiler *tc, const struct toy_inst *inst, if (ref_pos >= 0) { assert(ref_pos < 3); - msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE; + msg_type = GEN6_MSG_SAMPLER_SAMPLE_L_C; ref_or_si = tsrc_swizzle1(coords, ref_pos); } else { - msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD; + msg_type = GEN6_MSG_SAMPLER_SAMPLE_L; } bias_or_lod = tsrc_swizzle1(coords, TOY_SWIZZLE_W); break; case TOY_OPCODE_TGSI_TXF: - msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD; + msg_type = GEN6_MSG_SAMPLER_LD; switch (inst->tex.target) { case TGSI_TEXTURE_2D_MSAA: @@ -470,12 +470,12 @@ vs_prepare_tgsi_sampling(struct toy_compiler *tc, const struct toy_inst *inst, sampler_src = 1; break; case TOY_OPCODE_TGSI_TXQ: - msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO; + msg_type = GEN6_MSG_SAMPLER_RESINFO; num_coords = 0; bias_or_lod = tsrc_swizzle1(coords, TOY_SWIZZLE_X); break; case TOY_OPCODE_TGSI_TXQ_LZ: - msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO; + msg_type = GEN6_MSG_SAMPLER_RESINFO; num_coords = 0; sampler_src = 0; break; @@ -483,11 +483,11 @@ vs_prepare_tgsi_sampling(struct toy_compiler *tc, const struct toy_inst *inst, if (ref_pos >= 0) { assert(ref_pos < 4); - msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE; + msg_type = GEN6_MSG_SAMPLER_SAMPLE_L_C; ref_or_si = tsrc_swizzle1(coords, ref_pos); } else { - msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD; + msg_type = GEN6_MSG_SAMPLER_SAMPLE_L; } bias_or_lod = tsrc_swizzle1(inst->src[1], TOY_SWIZZLE_X); @@ -529,8 +529,8 @@ vs_prepare_tgsi_sampling(struct toy_compiler *tc, const struct toy_inst *inst, for (i = 0; i < 3; i++) abs_coords[i] = tsrc_absolute(tsrc_swizzle1(coords, i)); - tc_SEL(tc, max, abs_coords[0], abs_coords[0], BRW_CONDITIONAL_GE); - tc_SEL(tc, max, tsrc_from(max), abs_coords[0], BRW_CONDITIONAL_GE); + tc_SEL(tc, max, abs_coords[0], abs_coords[0], GEN6_COND_GE); + tc_SEL(tc, max, tsrc_from(max), abs_coords[0], GEN6_COND_GE); tc_INV(tc, max, tsrc_from(max)); for (i = 0; i < 3; i++) @@ -588,7 +588,7 @@ vs_lower_opcode_tgsi_sampling(struct vs_compile_context *vcc, break; } - toy_compiler_lower_to_send(tc, inst, false, BRW_SFID_SAMPLER); + toy_compiler_lower_to_send(tc, inst, false, GEN6_SFID_SAMPLER); inst->src[0] = tsrc(TOY_FILE_MRF, vcc->first_free_mrf, 0); inst->src[1] = desc; @@ -649,7 +649,7 @@ static void vs_lower_opcode_urb_write(struct toy_compiler *tc, struct toy_inst *inst) { /* vs_write_vue() has set up the message registers */ - toy_compiler_lower_to_send(tc, inst, false, BRW_SFID_URB); + toy_compiler_lower_to_send(tc, inst, false, GEN6_SFID_URB); } static void @@ -915,15 +915,15 @@ vs_write_vue(struct vs_compile_context *vcc) header = tdst_ud(tdst(TOY_FILE_MRF, vcc->first_free_mrf, 0)); r0 = tsrc_ud(tsrc(TOY_FILE_GRF, 0, 0)); inst = tc_MOV(tc, header, r0); - inst->mask_ctrl = BRW_MASK_DISABLE; + inst->mask_ctrl = GEN6_MASKCTRL_NOMASK; if (tc->dev->gen >= ILO_GEN(7)) { inst = tc_OR(tc, tdst_offset(header, 0, 5), tsrc_rect(tsrc_offset(r0, 0, 5), TOY_RECT_010), tsrc_rect(tsrc_imm_ud(0xff00), TOY_RECT_010)); - inst->exec_size = BRW_EXECUTE_1; - inst->access_mode = BRW_ALIGN_1; - inst->mask_ctrl = BRW_MASK_DISABLE; + inst->exec_size = GEN6_EXECSIZE_1; + inst->access_mode = GEN6_ALIGN_1; + inst->mask_ctrl = GEN6_MASKCTRL_NOMASK; } total_attrs = vs_collect_outputs(vcc, outs); @@ -986,7 +986,7 @@ vs_write_vue(struct vs_compile_context *vcc) assert(sent_attrs % 2 == 0); desc = tsrc_imm_mdesc_urb(tc, eot, msg_len, 0, - eot, true, false, BRW_URB_SWIZZLE_INTERLEAVE, sent_attrs / 2, 0); + eot, true, false, true, sent_attrs / 2, 0); tc_add2(tc, TOY_OPCODE_URB_WRITE, tdst_null(), tsrc_from(header), desc); @@ -1216,15 +1216,15 @@ vs_setup(struct vs_compile_context *vcc, vcc->variant = variant; toy_compiler_init(&vcc->tc, state->info.dev); - vcc->tc.templ.access_mode = BRW_ALIGN_16; - vcc->tc.templ.exec_size = BRW_EXECUTE_8; + vcc->tc.templ.access_mode = GEN6_ALIGN_16; + vcc->tc.templ.exec_size = GEN6_EXECSIZE_8; vcc->tc.rect_linear_width = 4; /* * The classic driver uses the sampler cache (gen6) or the data cache * (gen7). Why? */ - vcc->const_cache = GEN6_SFID_DATAPORT_CONSTANT_CACHE; + vcc->const_cache = GEN6_SFID_DP_CC; if (!vs_setup_tgsi(&vcc->tc, state->info.tokens, &vcc->tgsi)) { toy_compiler_cleanup(&vcc->tc); diff --git a/src/gallium/drivers/ilo/shader/toy_compiler.c b/src/gallium/drivers/ilo/shader/toy_compiler.c index 623d47821c3..6e9dac1bf50 100644 --- a/src/gallium/drivers/ilo/shader/toy_compiler.c +++ b/src/gallium/drivers/ilo/shader/toy_compiler.c @@ -71,30 +71,30 @@ tc_dump_operand(struct toy_compiler *tc, break; case TOY_FILE_ARF: switch (reg) { - case BRW_ARF_NULL: + case GEN6_ARF_NULL: ilo_printf("null"); break; - case BRW_ARF_ADDRESS: + case GEN6_ARF_A0: ilo_printf("a0.%d", subreg); break; - case BRW_ARF_ACCUMULATOR: - case BRW_ARF_ACCUMULATOR + 1: + case GEN6_ARF_ACC0: + case GEN6_ARF_ACC0 + 1: ilo_printf("acc%d.%d", (reg & 1), subreg); break; - case BRW_ARF_FLAG: + case GEN6_ARF_F0: ilo_printf("f0.%d", subreg); break; - case BRW_ARF_STATE: + case GEN6_ARF_SR0: ilo_printf("sr0.%d", subreg); break; - case BRW_ARF_CONTROL: + case GEN6_ARF_CR0: ilo_printf("cr0.%d", subreg); break; - case BRW_ARF_NOTIFICATION_COUNT: - case BRW_ARF_NOTIFICATION_COUNT + 1: + case GEN6_ARF_N0: + case GEN6_ARF_N0 + 1: ilo_printf("n%d.%d", (reg & 1), subreg); break; - case BRW_ARF_IP: + case GEN6_ARF_IP: ilo_printf("ip"); break; } @@ -259,59 +259,59 @@ static const char * get_opcode_name(unsigned opcode) { switch (opcode) { - case BRW_OPCODE_MOV: return "mov"; - case BRW_OPCODE_SEL: return "sel"; - case BRW_OPCODE_NOT: return "not"; - case BRW_OPCODE_AND: return "and"; - case BRW_OPCODE_OR: return "or"; - case BRW_OPCODE_XOR: return "xor"; - case BRW_OPCODE_SHR: return "shr"; - case BRW_OPCODE_SHL: return "shl"; - case BRW_OPCODE_RSR: return "rsr"; - case BRW_OPCODE_RSL: return "rsl"; - case BRW_OPCODE_ASR: return "asr"; - case BRW_OPCODE_CMP: return "cmp"; - case BRW_OPCODE_CMPN: return "cmpn"; - case BRW_OPCODE_JMPI: return "jmpi"; - case BRW_OPCODE_IF: return "if"; - case BRW_OPCODE_IFF: return "iff"; - case BRW_OPCODE_ELSE: return "else"; - case BRW_OPCODE_ENDIF: return "endif"; - case BRW_OPCODE_DO: return "do"; - case BRW_OPCODE_WHILE: return "while"; - case BRW_OPCODE_BREAK: return "break"; - case BRW_OPCODE_CONTINUE: return "continue"; - case BRW_OPCODE_HALT: return "halt"; - case BRW_OPCODE_MSAVE: return "msave"; - case BRW_OPCODE_MRESTORE: return "mrestore"; - case BRW_OPCODE_PUSH: return "push"; - case BRW_OPCODE_POP: return "pop"; - case BRW_OPCODE_WAIT: return "wait"; - case BRW_OPCODE_SEND: return "send"; - case BRW_OPCODE_SENDC: return "sendc"; - case BRW_OPCODE_MATH: return "math"; - case BRW_OPCODE_ADD: return "add"; - case BRW_OPCODE_MUL: return "mul"; - case BRW_OPCODE_AVG: return "avg"; - case BRW_OPCODE_FRC: return "frc"; - case BRW_OPCODE_RNDU: return "rndu"; - case BRW_OPCODE_RNDD: return "rndd"; - case BRW_OPCODE_RNDE: return "rnde"; - case BRW_OPCODE_RNDZ: return "rndz"; - case BRW_OPCODE_MAC: return "mac"; - case BRW_OPCODE_MACH: return "mach"; - case BRW_OPCODE_LZD: return "lzd"; - case BRW_OPCODE_SAD2: return "sad2"; - case BRW_OPCODE_SADA2: return "sada2"; - case BRW_OPCODE_DP4: return "dp4"; - case BRW_OPCODE_DPH: return "dph"; - case BRW_OPCODE_DP3: return "dp3"; - case BRW_OPCODE_DP2: return "dp2"; - case BRW_OPCODE_DPA2: return "dpa2"; - case BRW_OPCODE_LINE: return "line"; - case BRW_OPCODE_PLN: return "pln"; - case BRW_OPCODE_MAD: return "mad"; - case BRW_OPCODE_NOP: return "nop"; + case GEN6_OPCODE_MOV: return "mov"; + case GEN6_OPCODE_SEL: return "sel"; + case GEN6_OPCODE_NOT: return "not"; + case GEN6_OPCODE_AND: return "and"; + case GEN6_OPCODE_OR: return "or"; + case GEN6_OPCODE_XOR: return "xor"; + case GEN6_OPCODE_SHR: return "shr"; + case GEN6_OPCODE_SHL: return "shl"; + case 0xa: return "rsr"; + case 0xb: return "rsl"; + case GEN6_OPCODE_ASR: return "asr"; + case GEN6_OPCODE_CMP: return "cmp"; + case GEN6_OPCODE_CMPN: return "cmpn"; + case GEN6_OPCODE_JMPI: return "jmpi"; + case GEN6_OPCODE_IF: return "if"; + case 0x23: return "iff"; + case GEN6_OPCODE_ELSE: return "else"; + case GEN6_OPCODE_ENDIF: return "endif"; + case 0x26: return "do"; + case GEN6_OPCODE_WHILE: return "while"; + case GEN6_OPCODE_BREAK: return "break"; + case GEN6_OPCODE_CONT: return "continue"; + case GEN6_OPCODE_HALT: return "halt"; + case 0x2c: return "msave"; + case 0x2d: return "mrestore"; + case 0x2e: return "push"; + case 0x2f: return "pop"; + case GEN6_OPCODE_WAIT: return "wait"; + case GEN6_OPCODE_SEND: return "send"; + case GEN6_OPCODE_SENDC: return "sendc"; + case GEN6_OPCODE_MATH: return "math"; + case GEN6_OPCODE_ADD: return "add"; + case GEN6_OPCODE_MUL: return "mul"; + case GEN6_OPCODE_AVG: return "avg"; + case GEN6_OPCODE_FRC: return "frc"; + case GEN6_OPCODE_RNDU: return "rndu"; + case GEN6_OPCODE_RNDD: return "rndd"; + case GEN6_OPCODE_RNDE: return "rnde"; + case GEN6_OPCODE_RNDZ: return "rndz"; + case GEN6_OPCODE_MAC: return "mac"; + case GEN6_OPCODE_MACH: return "mach"; + case GEN6_OPCODE_LZD: return "lzd"; + case GEN6_OPCODE_SAD2: return "sad2"; + case GEN6_OPCODE_SADA2: return "sada2"; + case GEN6_OPCODE_DP4: return "dp4"; + case GEN6_OPCODE_DPH: return "dph"; + case GEN6_OPCODE_DP3: return "dp3"; + case GEN6_OPCODE_DP2: return "dp2"; + case 0x58: return "dpa2"; + case GEN6_OPCODE_LINE: return "line"; + case GEN6_OPCODE_PLN: return "pln"; + case GEN6_OPCODE_MAD: return "mad"; + case GEN6_OPCODE_NOP: return "nop"; case TOY_OPCODE_DO: return "do"; /* TGSI */ case TOY_OPCODE_TGSI_IN: return "tgsi.in"; @@ -373,47 +373,47 @@ static const char * get_cond_modifier_name(unsigned opcode, unsigned cond_modifier) { switch (opcode) { - case BRW_OPCODE_SEND: - case BRW_OPCODE_SENDC: + case GEN6_OPCODE_SEND: + case GEN6_OPCODE_SENDC: /* SFID */ switch (cond_modifier) { - case BRW_SFID_NULL: return "Null"; - case BRW_SFID_SAMPLER: return "Sampling Engine"; - case BRW_SFID_MESSAGE_GATEWAY: return "Message Gateway"; - case GEN6_SFID_DATAPORT_SAMPLER_CACHE: return "Data Port Sampler Cache"; - case GEN6_SFID_DATAPORT_RENDER_CACHE: return "Data Port Render Cache"; - case BRW_SFID_URB: return "URB"; - case BRW_SFID_THREAD_SPAWNER: return "Thread Spawner"; - case GEN6_SFID_DATAPORT_CONSTANT_CACHE: return "Constant Cache"; + case GEN6_SFID_NULL: return "Null"; + case GEN6_SFID_SAMPLER: return "Sampling Engine"; + case GEN6_SFID_GATEWAY: return "Message Gateway"; + case GEN6_SFID_DP_SAMPLER: return "Data Port Sampler Cache"; + case GEN6_SFID_DP_RC: return "Data Port Render Cache"; + case GEN6_SFID_URB: return "URB"; + case GEN6_SFID_SPAWNER: return "Thread Spawner"; + case GEN6_SFID_DP_CC: return "Constant Cache"; default: return "Unknown"; } break; - case BRW_OPCODE_MATH: + case GEN6_OPCODE_MATH: /* FC */ switch (cond_modifier) { - case BRW_MATH_FUNCTION_INV: return "INV"; - case BRW_MATH_FUNCTION_LOG: return "LOG"; - case BRW_MATH_FUNCTION_EXP: return "EXP"; - case BRW_MATH_FUNCTION_SQRT: return "SQRT"; - case BRW_MATH_FUNCTION_RSQ: return "RSQ"; - case BRW_MATH_FUNCTION_SIN: return "SIN"; - case BRW_MATH_FUNCTION_COS: return "COS"; - case BRW_MATH_FUNCTION_FDIV: return "FDIV"; - case BRW_MATH_FUNCTION_POW: return "POW"; - case BRW_MATH_FUNCTION_INT_DIV_QUOTIENT: return "INT DIV (quotient)"; - case BRW_MATH_FUNCTION_INT_DIV_REMAINDER: return "INT DIV (remainder)"; + case GEN6_MATH_INV: return "INV"; + case GEN6_MATH_LOG: return "LOG"; + case GEN6_MATH_EXP: return "EXP"; + case GEN6_MATH_SQRT: return "SQRT"; + case GEN6_MATH_RSQ: return "RSQ"; + case GEN6_MATH_SIN: return "SIN"; + case GEN6_MATH_COS: return "COS"; + case GEN6_MATH_FDIV: return "FDIV"; + case GEN6_MATH_POW: return "POW"; + case GEN6_MATH_INT_DIV_QUOTIENT: return "INT DIV (quotient)"; + case GEN6_MATH_INT_DIV_REMAINDER: return "INT DIV (remainder)"; default: return "UNK"; } break; default: switch (cond_modifier) { - case BRW_CONDITIONAL_NONE: return NULL; - case BRW_CONDITIONAL_Z: return "z"; - case BRW_CONDITIONAL_NZ: return "nz"; - case BRW_CONDITIONAL_G: return "g"; - case BRW_CONDITIONAL_GE: return "ge"; - case BRW_CONDITIONAL_L: return "l"; - case BRW_CONDITIONAL_LE: return "le"; + case GEN6_COND_NORMAL: return NULL; + case GEN6_COND_Z: return "z"; + case GEN6_COND_NZ: return "nz"; + case GEN6_COND_G: return "g"; + case GEN6_COND_GE: return "ge"; + case GEN6_COND_L: return "l"; + case GEN6_COND_LE: return "le"; default: return "unk"; } break; @@ -433,7 +433,7 @@ tc_dump_inst(struct toy_compiler *tc, const struct toy_inst *inst) ilo_printf(" %s", name); - if (inst->opcode == BRW_OPCODE_NOP) { + if (inst->opcode == GEN6_OPCODE_NOP) { ilo_printf("\n"); return; } @@ -506,16 +506,16 @@ tc_init_inst_templ(struct toy_compiler *tc) struct toy_inst *templ = &tc->templ; int i; - templ->opcode = BRW_OPCODE_NOP; - templ->access_mode = BRW_ALIGN_1; - templ->mask_ctrl = BRW_MASK_ENABLE; - templ->dep_ctrl = BRW_DEPENDENCY_NORMAL; - templ->qtr_ctrl = GEN6_COMPRESSION_1Q; - templ->thread_ctrl = BRW_THREAD_NORMAL; - templ->pred_ctrl = BRW_PREDICATE_NONE; + templ->opcode = GEN6_OPCODE_NOP; + templ->access_mode = GEN6_ALIGN_1; + templ->mask_ctrl = GEN6_MASKCTRL_NORMAL; + templ->dep_ctrl = GEN6_DEPCTRL_NORMAL; + templ->qtr_ctrl = GEN6_QTRCTRL_1Q; + templ->thread_ctrl = GEN6_THREADCTRL_NORMAL; + templ->pred_ctrl = GEN6_PREDCTRL_NONE; templ->pred_inv = false; - templ->exec_size = BRW_EXECUTE_1; - templ->cond_modifier = BRW_CONDITIONAL_NONE; + templ->exec_size = GEN6_EXECSIZE_1; + templ->cond_modifier = GEN6_COND_NORMAL; templ->acc_wr_ctrl = false; templ->saturate = false; diff --git a/src/gallium/drivers/ilo/shader/toy_compiler.h b/src/gallium/drivers/ilo/shader/toy_compiler.h index 372a2ac200d..c23d7fc88a9 100644 --- a/src/gallium/drivers/ilo/shader/toy_compiler.h +++ b/src/gallium/drivers/ilo/shader/toy_compiler.h @@ -38,7 +38,7 @@ * Toy opcodes. */ enum toy_opcode { - /* 0..127 are reserved for BRW_OPCODE_x */ + /* 0..127 are reserved for GEN6_OPCODE_x */ TOY_OPCODE_LAST_HW = 127, TOY_OPCODE_DO, @@ -108,15 +108,15 @@ enum toy_opcode { */ struct toy_inst { unsigned opcode:8; /* enum toy_opcode */ - unsigned access_mode:1; /* BRW_ALIGN_x */ - unsigned mask_ctrl:1; /* BRW_MASK_x */ - unsigned dep_ctrl:2; /* BRW_DEPENDENCY_x */ - unsigned qtr_ctrl:2; /* GEN6_COMPRESSION_x */ - unsigned thread_ctrl:2; /* BRW_THREAD_x */ - unsigned pred_ctrl:4; /* BRW_PREDICATE_x */ + unsigned access_mode:1; /* GEN6_ALIGN_x */ + unsigned mask_ctrl:1; /* GEN6_MASKCTRL_x */ + unsigned dep_ctrl:2; /* GEN6_DEPCTRL_x */ + unsigned qtr_ctrl:2; /* GEN6_QTRCTRL_x */ + unsigned thread_ctrl:2; /* GEN6_THREADCTRL_x */ + unsigned pred_ctrl:4; /* GEN6_PREDCTRL_x */ unsigned pred_inv:1; /* true or false */ - unsigned exec_size:3; /* BRW_EXECUTE_x */ - unsigned cond_modifier:4; /* BRW_CONDITIONAL_x */ + unsigned exec_size:3; /* GEN6_EXECSIZE_x */ + unsigned cond_modifier:4; /* GEN6_COND_x */ unsigned acc_wr_ctrl:1; /* true or false */ unsigned saturate:1; /* true or false */ @@ -351,30 +351,30 @@ func(struct toy_compiler *tc, \ return inst; \ } -TC_ALU0(tc_NOP, BRW_OPCODE_NOP) -TC_ALU0(tc_ELSE, BRW_OPCODE_ELSE) -TC_ALU0(tc_ENDIF, BRW_OPCODE_ENDIF) -TC_ALU1(tc_MOV, BRW_OPCODE_MOV) -TC_ALU1(tc_RNDD, BRW_OPCODE_RNDD) +TC_ALU0(tc_NOP, GEN6_OPCODE_NOP) +TC_ALU0(tc_ELSE, GEN6_OPCODE_ELSE) +TC_ALU0(tc_ENDIF, GEN6_OPCODE_ENDIF) +TC_ALU1(tc_MOV, GEN6_OPCODE_MOV) +TC_ALU1(tc_RNDD, GEN6_OPCODE_RNDD) TC_ALU1(tc_INV, TOY_OPCODE_INV) -TC_ALU1(tc_FRC, BRW_OPCODE_FRC) +TC_ALU1(tc_FRC, GEN6_OPCODE_FRC) TC_ALU1(tc_EXP, TOY_OPCODE_EXP) TC_ALU1(tc_LOG, TOY_OPCODE_LOG) -TC_ALU2(tc_ADD, BRW_OPCODE_ADD) -TC_ALU2(tc_MUL, BRW_OPCODE_MUL) -TC_ALU2(tc_AND, BRW_OPCODE_AND) -TC_ALU2(tc_OR, BRW_OPCODE_OR) -TC_ALU2(tc_DP2, BRW_OPCODE_DP2) -TC_ALU2(tc_DP3, BRW_OPCODE_DP3) -TC_ALU2(tc_DP4, BRW_OPCODE_DP4) -TC_ALU2(tc_SHL, BRW_OPCODE_SHL) -TC_ALU2(tc_SHR, BRW_OPCODE_SHR) +TC_ALU2(tc_ADD, GEN6_OPCODE_ADD) +TC_ALU2(tc_MUL, GEN6_OPCODE_MUL) +TC_ALU2(tc_AND, GEN6_OPCODE_AND) +TC_ALU2(tc_OR, GEN6_OPCODE_OR) +TC_ALU2(tc_DP2, GEN6_OPCODE_DP2) +TC_ALU2(tc_DP3, GEN6_OPCODE_DP3) +TC_ALU2(tc_DP4, GEN6_OPCODE_DP4) +TC_ALU2(tc_SHL, GEN6_OPCODE_SHL) +TC_ALU2(tc_SHR, GEN6_OPCODE_SHR) TC_ALU2(tc_POW, TOY_OPCODE_POW) -TC_ALU3(tc_MAC, BRW_OPCODE_MAC) -TC_CND2(tc_SEL, BRW_OPCODE_SEL) -TC_CND2(tc_CMP, BRW_OPCODE_CMP) -TC_CND2(tc_IF, BRW_OPCODE_IF) -TC_CND2(tc_SEND, BRW_OPCODE_SEND) +TC_ALU3(tc_MAC, GEN6_OPCODE_MAC) +TC_CND2(tc_SEL, GEN6_OPCODE_SEL) +TC_CND2(tc_CMP, GEN6_OPCODE_CMP) +TC_CND2(tc_IF, GEN6_OPCODE_IF) +TC_CND2(tc_SEND, GEN6_OPCODE_SEND) /** * Upcast a list_head to an instruction. diff --git a/src/gallium/drivers/ilo/shader/toy_compiler_asm.c b/src/gallium/drivers/ilo/shader/toy_compiler_asm.c index 09a00dd2211..cf57a902a78 100644 --- a/src/gallium/drivers/ilo/shader/toy_compiler_asm.c +++ b/src/gallium/drivers/ilo/shader/toy_compiler_asm.c @@ -73,8 +73,8 @@ src_is_null(const struct codegen *cg, int idx) { const struct codegen_src *src = &cg->src[idx]; - return (src->file == BRW_ARCHITECTURE_REGISTER_FILE && - src->origin == BRW_ARF_NULL << CG_REG_SHIFT); + return (src->file == GEN6_FILE_ARF && + src->origin == GEN6_ARF_NULL << CG_REG_SHIFT); } /** @@ -87,7 +87,7 @@ translate_src(const struct codegen *cg, int idx) uint32_t dw; /* special treatment may be needed if any of the operand is immediate */ - if (cg->src[0].file == BRW_IMMEDIATE_VALUE) { + if (cg->src[0].file == GEN6_FILE_IMM) { assert(!cg->src[0].absolute && !cg->src[0].negate); /* only the last src operand can be an immediate */ assert(src_is_null(cg, 1)); @@ -97,22 +97,22 @@ translate_src(const struct codegen *cg, int idx) else return cg->src[0].origin; } - else if (idx && cg->src[1].file == BRW_IMMEDIATE_VALUE) { + else if (idx && cg->src[1].file == GEN6_FILE_IMM) { assert(!cg->src[1].absolute && !cg->src[1].negate); return cg->src[1].origin; } - assert(src->file != BRW_IMMEDIATE_VALUE); + assert(src->file != GEN6_FILE_IMM); if (src->indirect) { const int offset = (int) src->origin; - assert(src->file == BRW_GENERAL_REGISTER_FILE); + assert(src->file == GEN6_FILE_GRF); assert(offset < 512 && offset >= -512); - if (cg->inst->access_mode == BRW_ALIGN_16) { - assert(src->width == BRW_WIDTH_4); - assert(src->horz_stride == BRW_HORIZONTAL_STRIDE_1); + if (cg->inst->access_mode == GEN6_ALIGN_16) { + assert(src->width == GEN6_WIDTH_4); + assert(src->horz_stride == GEN6_HORZSTRIDE_1); /* the lower 4 bits are reserved for the swizzle_[xy] */ assert(!(src->origin & 0xf)); @@ -120,7 +120,7 @@ translate_src(const struct codegen *cg, int idx) dw = src->vert_stride << 21 | src->swizzle[3] << 18 | src->swizzle[2] << 16 | - BRW_ADDRESS_REGISTER_INDIRECT_REGISTER << 15 | + GEN6_ADDRMODE_INDIRECT << 15 | src->negate << 14 | src->absolute << 13 | src->indirect_subreg << 10 | @@ -137,7 +137,7 @@ translate_src(const struct codegen *cg, int idx) dw = src->vert_stride << 21 | src->width << 18 | src->horz_stride << 16 | - BRW_ADDRESS_REGISTER_INDIRECT_REGISTER << 15 | + GEN6_ADDRMODE_INDIRECT << 15 | src->negate << 14 | src->absolute << 13 | src->indirect_subreg << 10 | @@ -146,25 +146,25 @@ translate_src(const struct codegen *cg, int idx) } else { switch (src->file) { - case BRW_ARCHITECTURE_REGISTER_FILE: + case GEN6_FILE_ARF: break; - case BRW_GENERAL_REGISTER_FILE: + case GEN6_FILE_GRF: assert(CG_REG_NUM(src->origin) < 128); break; - case BRW_MESSAGE_REGISTER_FILE: - assert(cg->inst->opcode == BRW_OPCODE_SEND || - cg->inst->opcode == BRW_OPCODE_SENDC); + case GEN6_FILE_MRF: + assert(cg->inst->opcode == GEN6_OPCODE_SEND || + cg->inst->opcode == GEN6_OPCODE_SENDC); assert(CG_REG_NUM(src->origin) < 16); break; - case BRW_IMMEDIATE_VALUE: + case GEN6_FILE_IMM: default: assert(!"invalid src file"); break; } - if (cg->inst->access_mode == BRW_ALIGN_16) { - assert(src->width == BRW_WIDTH_4); - assert(src->horz_stride == BRW_HORIZONTAL_STRIDE_1); + if (cg->inst->access_mode == GEN6_ALIGN_16) { + assert(src->width == GEN6_WIDTH_4); + assert(src->horz_stride == GEN6_HORZSTRIDE_1); /* the lower 4 bits are reserved for the swizzle_[xy] */ assert(!(src->origin & 0xf)); @@ -172,7 +172,7 @@ translate_src(const struct codegen *cg, int idx) dw = src->vert_stride << 21 | src->swizzle[3] << 18 | src->swizzle[2] << 16 | - BRW_ADDRESS_DIRECT << 15 | + GEN6_ADDRMODE_DIRECT << 15 | src->negate << 14 | src->absolute << 13 | src->origin | @@ -188,7 +188,7 @@ translate_src(const struct codegen *cg, int idx) dw = src->vert_stride << 21 | src->width << 18 | src->horz_stride << 16 | - BRW_ADDRESS_DIRECT << 15 | + GEN6_ADDRMODE_DIRECT << 15 | src->negate << 14 | src->absolute << 13 | src->origin; @@ -211,14 +211,14 @@ translate_dst_region(const struct codegen *cg) const struct codegen_dst *dst = &cg->dst; uint16_t dw1_region; - if (dst->file == BRW_IMMEDIATE_VALUE) { + if (dst->file == GEN6_FILE_IMM) { /* dst is immediate (JIP) when the opcode is a conditional branch */ switch (cg->inst->opcode) { - case BRW_OPCODE_IF: - case BRW_OPCODE_ELSE: - case BRW_OPCODE_ENDIF: - case BRW_OPCODE_WHILE: - assert(dst->type == BRW_REGISTER_TYPE_W); + case GEN6_OPCODE_IF: + case GEN6_OPCODE_ELSE: + case GEN6_OPCODE_ENDIF: + case GEN6_OPCODE_WHILE: + assert(dst->type == GEN6_TYPE_W); dw1_region = (dst->origin & 0xffff); break; default: @@ -233,21 +233,21 @@ translate_dst_region(const struct codegen *cg) if (dst->indirect) { const int offset = (int) dst->origin; - assert(dst->file == BRW_GENERAL_REGISTER_FILE); + assert(dst->file == GEN6_FILE_GRF); assert(offset < 512 && offset >= -512); - if (cg->inst->access_mode == BRW_ALIGN_16) { + if (cg->inst->access_mode == GEN6_ALIGN_16) { /* * From the Sandy Bridge PRM, volume 4 part 2, page 144: * * "Allthough Dst.HorzStride is a don't care for Align16, HW * needs this to be programmed as 01." */ - assert(dst->horz_stride == BRW_HORIZONTAL_STRIDE_1); + assert(dst->horz_stride == GEN6_HORZSTRIDE_1); /* the lower 4 bits are reserved for the writemask */ assert(!(dst->origin & 0xf)); - dw1_region = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER << 15 | + dw1_region = GEN6_ADDRMODE_INDIRECT << 15 | dst->horz_stride << 13 | dst->indirect_subreg << 10 | (dst->origin & 0x3f0) | @@ -256,25 +256,25 @@ translate_dst_region(const struct codegen *cg) else { assert(dst->writemask == TOY_WRITEMASK_XYZW); - dw1_region = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER << 15 | + dw1_region = GEN6_ADDRMODE_INDIRECT << 15 | dst->horz_stride << 13 | dst->indirect_subreg << 10 | (dst->origin & 0x3ff); } } else { - assert((dst->file == BRW_GENERAL_REGISTER_FILE && + assert((dst->file == GEN6_FILE_GRF && CG_REG_NUM(dst->origin) < 128) || - (dst->file == BRW_MESSAGE_REGISTER_FILE && + (dst->file == GEN6_FILE_MRF && CG_REG_NUM(dst->origin) < 16) || - (dst->file == BRW_ARCHITECTURE_REGISTER_FILE)); + (dst->file == GEN6_FILE_ARF)); - if (cg->inst->access_mode == BRW_ALIGN_16) { + if (cg->inst->access_mode == GEN6_ALIGN_16) { /* similar to the indirect case */ - assert(dst->horz_stride == BRW_HORIZONTAL_STRIDE_1); + assert(dst->horz_stride == GEN6_HORZSTRIDE_1); assert(!(dst->origin & 0xf)); - dw1_region = BRW_ADDRESS_DIRECT << 15 | + dw1_region = GEN6_ADDRMODE_DIRECT << 15 | dst->horz_stride << 13 | dst->origin | dst->writemask; @@ -282,7 +282,7 @@ translate_dst_region(const struct codegen *cg) else { assert(dst->writemask == TOY_WRITEMASK_XYZW); - dw1_region = BRW_ADDRESS_DIRECT << 15 | + dw1_region = GEN6_ADDRMODE_DIRECT << 15 | dst->horz_stride << 13 | dst->origin; } @@ -368,15 +368,15 @@ codegen_inst_3src(const struct codegen *cg, uint32_t *code) * - no regioning except replication control * (vert_stride == 0 && horz_stride == 0) */ - assert(cg->inst->access_mode == BRW_ALIGN_16); + assert(cg->inst->access_mode == GEN6_ALIGN_16); assert(!dst->indirect); - assert((dst->file == BRW_GENERAL_REGISTER_FILE && + assert((dst->file == GEN6_FILE_GRF && CG_REG_NUM(dst->origin) < 128) || - (dst->file == BRW_MESSAGE_REGISTER_FILE && + (dst->file == GEN6_FILE_MRF && CG_REG_NUM(dst->origin) < 16)); assert(!(dst->origin & 0x3)); - assert(dst->horz_stride == BRW_HORIZONTAL_STRIDE_1); + assert(dst->horz_stride == GEN6_HORZSTRIDE_1); dw1 = dst->origin << 19 | dst->writemask << 17 | @@ -387,29 +387,29 @@ codegen_inst_3src(const struct codegen *cg, uint32_t *code) cg->src[0].negate << 5 | cg->src[0].absolute << 4 | cg->flag_sub_reg_num << 1 | - (dst->file == BRW_MESSAGE_REGISTER_FILE); + (dst->file == GEN6_FILE_MRF); for (i = 0; i < 3; i++) { const struct codegen_src *src = &cg->src[i]; assert(!src->indirect); - assert(src->file == BRW_GENERAL_REGISTER_FILE && + assert(src->file == GEN6_FILE_GRF && CG_REG_NUM(src->origin) < 128); assert(!(src->origin & 0x3)); - assert((src->vert_stride == BRW_VERTICAL_STRIDE_4 && - src->horz_stride == BRW_HORIZONTAL_STRIDE_1) || - (src->vert_stride == BRW_VERTICAL_STRIDE_0 && - src->horz_stride == BRW_HORIZONTAL_STRIDE_0)); - assert(src->width == BRW_WIDTH_4); + assert((src->vert_stride == GEN6_VERTSTRIDE_4 && + src->horz_stride == GEN6_HORZSTRIDE_1) || + (src->vert_stride == GEN6_VERTSTRIDE_0 && + src->horz_stride == GEN6_HORZSTRIDE_0)); + assert(src->width == GEN6_WIDTH_4); dw_src[i] = src->origin << 7 | src->swizzle[3] << 7 | src->swizzle[2] << 5 | src->swizzle[1] << 3 | src->swizzle[0] << 1 | - (src->vert_stride == BRW_VERTICAL_STRIDE_0 && - src->horz_stride == BRW_HORIZONTAL_STRIDE_0); + (src->vert_stride == GEN6_VERTSTRIDE_0 && + src->horz_stride == GEN6_HORZSTRIDE_0); /* only the lower 20 bits are used */ assert((dw_src[i] & 0xfffff) == dw_src[i]); @@ -429,38 +429,38 @@ static void codegen_validate_region_restrictions(const struct codegen *cg) { const int exec_size_map[] = { - [BRW_EXECUTE_1] = 1, - [BRW_EXECUTE_2] = 2, - [BRW_EXECUTE_4] = 4, - [BRW_EXECUTE_8] = 8, - [BRW_EXECUTE_16] = 16, - [BRW_EXECUTE_32] = 32, + [GEN6_EXECSIZE_1] = 1, + [GEN6_EXECSIZE_2] = 2, + [GEN6_EXECSIZE_4] = 4, + [GEN6_EXECSIZE_8] = 8, + [GEN6_EXECSIZE_16] = 16, + [GEN6_EXECSIZE_32] = 32, }; const int width_map[] = { - [BRW_WIDTH_1] = 1, - [BRW_WIDTH_2] = 2, - [BRW_WIDTH_4] = 4, - [BRW_WIDTH_8] = 8, - [BRW_WIDTH_16] = 16, + [GEN6_WIDTH_1] = 1, + [GEN6_WIDTH_2] = 2, + [GEN6_WIDTH_4] = 4, + [GEN6_WIDTH_8] = 8, + [GEN6_WIDTH_16] = 16, }; const int horz_stride_map[] = { - [BRW_HORIZONTAL_STRIDE_0] = 0, - [BRW_HORIZONTAL_STRIDE_1] = 1, - [BRW_HORIZONTAL_STRIDE_2] = 2, - [BRW_HORIZONTAL_STRIDE_4] = 4, + [GEN6_HORZSTRIDE_0] = 0, + [GEN6_HORZSTRIDE_1] = 1, + [GEN6_HORZSTRIDE_2] = 2, + [GEN6_HORZSTRIDE_4] = 4, }; const int vert_stride_map[] = { - [BRW_VERTICAL_STRIDE_0] = 0, - [BRW_VERTICAL_STRIDE_1] = 1, - [BRW_VERTICAL_STRIDE_2] = 2, - [BRW_VERTICAL_STRIDE_4] = 4, - [BRW_VERTICAL_STRIDE_8] = 8, - [BRW_VERTICAL_STRIDE_16] = 16, - [BRW_VERTICAL_STRIDE_32] = 32, - [BRW_VERTICAL_STRIDE_64] = 64, - [BRW_VERTICAL_STRIDE_128] = 128, - [BRW_VERTICAL_STRIDE_256] = 256, - [BRW_VERTICAL_STRIDE_ONE_DIMENSIONAL] = 0, + [GEN6_VERTSTRIDE_0] = 0, + [GEN6_VERTSTRIDE_1] = 1, + [GEN6_VERTSTRIDE_2] = 2, + [GEN6_VERTSTRIDE_4] = 4, + [GEN6_VERTSTRIDE_8] = 8, + [GEN6_VERTSTRIDE_16] = 16, + [GEN6_VERTSTRIDE_32] = 32, + [7] = 64, + [8] = 128, + [9] = 256, + [GEN6_VERTSTRIDE_VXH] = 0, }; const int exec_size = exec_size_map[cg->inst->exec_size]; int i; @@ -502,20 +502,20 @@ codegen_validate_region_restrictions(const struct codegen *cg) } /* derived from 10.1.2. & 10.2. */ - assert(cg->dst.horz_stride != BRW_HORIZONTAL_STRIDE_0); + assert(cg->dst.horz_stride != GEN6_HORZSTRIDE_0); } static unsigned translate_vfile(enum toy_file file) { switch (file) { - case TOY_FILE_ARF: return BRW_ARCHITECTURE_REGISTER_FILE; - case TOY_FILE_GRF: return BRW_GENERAL_REGISTER_FILE; - case TOY_FILE_MRF: return BRW_MESSAGE_REGISTER_FILE; - case TOY_FILE_IMM: return BRW_IMMEDIATE_VALUE; + case TOY_FILE_ARF: return GEN6_FILE_ARF; + case TOY_FILE_GRF: return GEN6_FILE_GRF; + case TOY_FILE_MRF: return GEN6_FILE_MRF; + case TOY_FILE_IMM: return GEN6_FILE_IMM; default: assert(!"unhandled toy file"); - return BRW_GENERAL_REGISTER_FILE; + return GEN6_FILE_GRF; } } @@ -523,15 +523,15 @@ static unsigned translate_vtype(enum toy_type type) { switch (type) { - case TOY_TYPE_F: return BRW_REGISTER_TYPE_F; - case TOY_TYPE_D: return BRW_REGISTER_TYPE_D; - case TOY_TYPE_UD: return BRW_REGISTER_TYPE_UD; - case TOY_TYPE_W: return BRW_REGISTER_TYPE_W; - case TOY_TYPE_UW: return BRW_REGISTER_TYPE_UW; - case TOY_TYPE_V: return BRW_REGISTER_TYPE_V; + case TOY_TYPE_F: return GEN6_TYPE_F; + case TOY_TYPE_D: return GEN6_TYPE_D; + case TOY_TYPE_UD: return GEN6_TYPE_UD; + case TOY_TYPE_W: return GEN6_TYPE_W; + case TOY_TYPE_UW: return GEN6_TYPE_UW; + case TOY_TYPE_V: return GEN6_TYPE_V_IMM; default: assert(!"unhandled toy type"); - return BRW_REGISTER_TYPE_F; + return GEN6_TYPE_F; } } @@ -594,11 +594,11 @@ codegen_prepare(struct codegen *cg, const struct toy_inst *inst, switch (inst->dst.rect) { case TOY_RECT_LINEAR: - cg->dst.horz_stride = BRW_HORIZONTAL_STRIDE_1; + cg->dst.horz_stride = GEN6_HORZSTRIDE_1; break; default: assert(!"unsupported dst region"); - cg->dst.horz_stride = BRW_HORIZONTAL_STRIDE_1; + cg->dst.horz_stride = GEN6_HORZSTRIDE_1; break; } @@ -635,63 +635,63 @@ codegen_prepare(struct codegen *cg, const struct toy_inst *inst, case TOY_RECT_LINEAR: switch (rect_linear_width) { case 1: - src->vert_stride = BRW_VERTICAL_STRIDE_1; - src->width = BRW_WIDTH_1; + src->vert_stride = GEN6_VERTSTRIDE_1; + src->width = GEN6_WIDTH_1; break; case 2: - src->vert_stride = BRW_VERTICAL_STRIDE_2; - src->width = BRW_WIDTH_2; + src->vert_stride = GEN6_VERTSTRIDE_2; + src->width = GEN6_WIDTH_2; break; case 4: - src->vert_stride = BRW_VERTICAL_STRIDE_4; - src->width = BRW_WIDTH_4; + src->vert_stride = GEN6_VERTSTRIDE_4; + src->width = GEN6_WIDTH_4; break; case 8: - src->vert_stride = BRW_VERTICAL_STRIDE_8; - src->width = BRW_WIDTH_8; + src->vert_stride = GEN6_VERTSTRIDE_8; + src->width = GEN6_WIDTH_8; break; case 16: - src->vert_stride = BRW_VERTICAL_STRIDE_16; - src->width = BRW_WIDTH_16; + src->vert_stride = GEN6_VERTSTRIDE_16; + src->width = GEN6_WIDTH_16; break; default: assert(!"unsupported TOY_RECT_LINEAR width"); - src->vert_stride = BRW_VERTICAL_STRIDE_1; - src->width = BRW_WIDTH_1; + src->vert_stride = GEN6_VERTSTRIDE_1; + src->width = GEN6_WIDTH_1; break; } - src->horz_stride = BRW_HORIZONTAL_STRIDE_1; + src->horz_stride = GEN6_HORZSTRIDE_1; break; case TOY_RECT_041: - src->vert_stride = BRW_VERTICAL_STRIDE_0; - src->width = BRW_WIDTH_4; - src->horz_stride = BRW_HORIZONTAL_STRIDE_1; + src->vert_stride = GEN6_VERTSTRIDE_0; + src->width = GEN6_WIDTH_4; + src->horz_stride = GEN6_HORZSTRIDE_1; break; case TOY_RECT_010: - src->vert_stride = BRW_VERTICAL_STRIDE_0; - src->width = BRW_WIDTH_1; - src->horz_stride = BRW_HORIZONTAL_STRIDE_0; + src->vert_stride = GEN6_VERTSTRIDE_0; + src->width = GEN6_WIDTH_1; + src->horz_stride = GEN6_HORZSTRIDE_0; break; case TOY_RECT_220: - src->vert_stride = BRW_VERTICAL_STRIDE_2; - src->width = BRW_WIDTH_2; - src->horz_stride = BRW_HORIZONTAL_STRIDE_0; + src->vert_stride = GEN6_VERTSTRIDE_2; + src->width = GEN6_WIDTH_2; + src->horz_stride = GEN6_HORZSTRIDE_0; break; case TOY_RECT_440: - src->vert_stride = BRW_VERTICAL_STRIDE_4; - src->width = BRW_WIDTH_4; - src->horz_stride = BRW_HORIZONTAL_STRIDE_0; + src->vert_stride = GEN6_VERTSTRIDE_4; + src->width = GEN6_WIDTH_4; + src->horz_stride = GEN6_HORZSTRIDE_0; break; case TOY_RECT_240: - src->vert_stride = BRW_VERTICAL_STRIDE_2; - src->width = BRW_WIDTH_4; - src->horz_stride = BRW_HORIZONTAL_STRIDE_0; + src->vert_stride = GEN6_VERTSTRIDE_2; + src->width = GEN6_WIDTH_4; + src->horz_stride = GEN6_HORZSTRIDE_0; break; default: assert(!"unsupported src region"); - src->vert_stride = BRW_VERTICAL_STRIDE_1; - src->width = BRW_WIDTH_1; - src->horz_stride = BRW_HORIZONTAL_STRIDE_1; + src->vert_stride = GEN6_VERTSTRIDE_1; + src->width = GEN6_WIDTH_1; + src->horz_stride = GEN6_HORZSTRIDE_1; break; } } @@ -726,7 +726,7 @@ toy_compiler_assemble(struct toy_compiler *tc, int *size) codegen_validate_region_restrictions(&cg); switch (inst->opcode) { - case BRW_OPCODE_MAD: + case GEN6_OPCODE_MAD: codegen_inst_3src(&cg, dw); break; default: diff --git a/src/gallium/drivers/ilo/shader/toy_compiler_reg.h b/src/gallium/drivers/ilo/shader/toy_compiler_reg.h index 8c11b3a3275..36674f8bf69 100644 --- a/src/gallium/drivers/ilo/shader/toy_compiler_reg.h +++ b/src/gallium/drivers/ilo/shader/toy_compiler_reg.h @@ -213,7 +213,7 @@ toy_type_size(enum toy_type type) static inline bool tdst_is_null(struct toy_dst dst) { - /* BRW_ARF_NULL happens to be 0 */ + /* GEN6_ARF_NULL happens to be 0 */ return (dst.file == TOY_FILE_ARF && dst.val32 == 0); } @@ -431,7 +431,7 @@ tdst_imm_w(int16_t w) static inline bool tsrc_is_null(struct toy_src src) { - /* BRW_ARF_NULL happens to be 0 */ + /* GEN6_ARF_NULL happens to be 0 */ return (src.file == TOY_FILE_ARF && src.val32 == 0); } diff --git a/src/gallium/drivers/ilo/shader/toy_helpers.h b/src/gallium/drivers/ilo/shader/toy_helpers.h index 038a81f5b2b..2e96ef8ef38 100644 --- a/src/gallium/drivers/ilo/shader/toy_helpers.h +++ b/src/gallium/drivers/ilo/shader/toy_helpers.h @@ -208,7 +208,7 @@ tsrc_imm_mdesc_data_port(const struct toy_compiler *tc, } else { assert(!send_write_commit_message || - message_type == GEN6_DATAPORT_WRITE_MESSAGE_STREAMED_VB_WRITE); + message_type == GEN6_MSG_DP_SVB_WRITE); assert((message_specific_control & 0x1f00) == message_specific_control); ctrl = send_write_commit_message << 17 | diff --git a/src/gallium/drivers/ilo/shader/toy_legalize.c b/src/gallium/drivers/ilo/shader/toy_legalize.c index 2339b7d3b8e..d632a57da1c 100644 --- a/src/gallium/drivers/ilo/shader/toy_legalize.c +++ b/src/gallium/drivers/ilo/shader/toy_legalize.c @@ -32,7 +32,7 @@ #include "toy_legalize.h" /** - * Lower an instruction to BRW_OPCODE_SEND(C). + * Lower an instruction to GEN6_OPCODE_SEND(C). */ void toy_compiler_lower_to_send(struct toy_compiler *tc, struct toy_inst *inst, @@ -40,12 +40,12 @@ toy_compiler_lower_to_send(struct toy_compiler *tc, struct toy_inst *inst, { assert(inst->opcode >= 128); - inst->opcode = (sendc) ? BRW_OPCODE_SENDC : BRW_OPCODE_SEND; + inst->opcode = (sendc) ? GEN6_OPCODE_SENDC : GEN6_OPCODE_SEND; /* thread control is reserved */ assert(inst->thread_ctrl == 0); - assert(inst->cond_modifier == BRW_CONDITIONAL_NONE); + assert(inst->cond_modifier == GEN6_COND_NORMAL); inst->cond_modifier = sfid; } @@ -53,17 +53,17 @@ static int math_op_to_func(unsigned opcode) { switch (opcode) { - case TOY_OPCODE_INV: return BRW_MATH_FUNCTION_INV; - case TOY_OPCODE_LOG: return BRW_MATH_FUNCTION_LOG; - case TOY_OPCODE_EXP: return BRW_MATH_FUNCTION_EXP; - case TOY_OPCODE_SQRT: return BRW_MATH_FUNCTION_SQRT; - case TOY_OPCODE_RSQ: return BRW_MATH_FUNCTION_RSQ; - case TOY_OPCODE_SIN: return BRW_MATH_FUNCTION_SIN; - case TOY_OPCODE_COS: return BRW_MATH_FUNCTION_COS; - case TOY_OPCODE_FDIV: return BRW_MATH_FUNCTION_FDIV; - case TOY_OPCODE_POW: return BRW_MATH_FUNCTION_POW; - case TOY_OPCODE_INT_DIV_QUOTIENT: return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT; - case TOY_OPCODE_INT_DIV_REMAINDER: return BRW_MATH_FUNCTION_INT_DIV_REMAINDER; + case TOY_OPCODE_INV: return GEN6_MATH_INV; + case TOY_OPCODE_LOG: return GEN6_MATH_LOG; + case TOY_OPCODE_EXP: return GEN6_MATH_EXP; + case TOY_OPCODE_SQRT: return GEN6_MATH_SQRT; + case TOY_OPCODE_RSQ: return GEN6_MATH_RSQ; + case TOY_OPCODE_SIN: return GEN6_MATH_SIN; + case TOY_OPCODE_COS: return GEN6_MATH_COS; + case TOY_OPCODE_FDIV: return GEN6_MATH_FDIV; + case TOY_OPCODE_POW: return GEN6_MATH_POW; + case TOY_OPCODE_INT_DIV_QUOTIENT: return GEN6_MATH_INT_DIV_QUOTIENT; + case TOY_OPCODE_INT_DIV_REMAINDER: return GEN6_MATH_INT_DIV_REMAINDER; default: assert(!"unknown math opcode"); return -1; @@ -71,7 +71,7 @@ math_op_to_func(unsigned opcode) } /** - * Lower virtual math opcodes to BRW_OPCODE_MATH. + * Lower virtual math opcodes to GEN6_OPCODE_MATH. */ void toy_compiler_lower_math(struct toy_compiler *tc, struct toy_inst *inst) @@ -98,13 +98,13 @@ toy_compiler_lower_math(struct toy_compiler *tc, struct toy_inst *inst) } /* FC[0:3] */ - assert(inst->cond_modifier == BRW_CONDITIONAL_NONE); + assert(inst->cond_modifier == GEN6_COND_NORMAL); inst->cond_modifier = math_op_to_func(inst->opcode); /* FC[4:5] */ assert(inst->thread_ctrl == 0); inst->thread_ctrl = 0; - inst->opcode = BRW_OPCODE_MATH; + inst->opcode = GEN6_OPCODE_MATH; tc_move_inst(tc, inst); /* no writemask in align1 */ @@ -223,7 +223,7 @@ lower_opcode_mul(struct toy_compiler *tc, struct toy_inst *inst) { const enum toy_type inst_type = inst->dst.type; const struct toy_dst acc0 = - tdst_type(tdst(TOY_FILE_ARF, BRW_ARF_ACCUMULATOR, 0), inst_type); + tdst_type(tdst(TOY_FILE_ARF, GEN6_ARF_ACC0, 0), inst_type); struct toy_inst *inst2; /* only need to take care of integer multiplications */ @@ -234,7 +234,7 @@ lower_opcode_mul(struct toy_compiler *tc, struct toy_inst *inst) tc_MUL(tc, acc0, inst->src[0], inst->src[1]); /* acc0 = (src0 & 0xffff0000) * src1 + acc0 */ - inst2 = tc_add2(tc, BRW_OPCODE_MACH, tdst_type(tdst_null(), inst_type), + inst2 = tc_add2(tc, GEN6_OPCODE_MACH, tdst_type(tdst_null(), inst_type), inst->src[0], inst->src[1]); inst2->acc_wr_ctrl = true; @@ -250,7 +250,7 @@ lower_opcode_mac(struct toy_compiler *tc, struct toy_inst *inst) const enum toy_type inst_type = inst->dst.type; if (inst_type != TOY_TYPE_UD && inst_type != TOY_TYPE_D) { - const struct toy_dst acc0 = tdst(TOY_FILE_ARF, BRW_ARF_ACCUMULATOR, 0); + const struct toy_dst acc0 = tdst(TOY_FILE_ARF, GEN6_ARF_ACC0, 0); tc_MOV(tc, acc0, inst->src[2]); inst->src[2] = tsrc_null(); @@ -280,13 +280,13 @@ toy_compiler_legalize_for_ra(struct toy_compiler *tc) tc_head(tc); while ((inst = tc_next(tc)) != NULL) { switch (inst->opcode) { - case BRW_OPCODE_MAC: + case GEN6_OPCODE_MAC: lower_opcode_mac(tc, inst); break; - case BRW_OPCODE_MAD: + case GEN6_OPCODE_MAD: /* TODO operands must be floats */ break; - case BRW_OPCODE_MUL: + case GEN6_OPCODE_MUL: lower_opcode_mul(tc, inst); break; default: @@ -329,7 +329,7 @@ patch_while_jip(struct toy_compiler *tc, struct toy_inst *inst) continue; } - if (inst2->opcode == BRW_OPCODE_WHILE) + if (inst2->opcode == GEN6_OPCODE_WHILE) nest_level++; dist--; @@ -358,7 +358,7 @@ patch_if_else_jip(struct toy_compiler *tc, struct toy_inst *inst) if (inst2->marker) continue; - if (inst2->opcode == BRW_OPCODE_ENDIF) { + if (inst2->opcode == GEN6_OPCODE_ENDIF) { if (nest_level) { nest_level--; } @@ -369,8 +369,8 @@ patch_if_else_jip(struct toy_compiler *tc, struct toy_inst *inst) break; } } - else if (inst2->opcode == BRW_OPCODE_ELSE && - inst->opcode == BRW_OPCODE_IF) { + else if (inst2->opcode == GEN6_OPCODE_ELSE && + inst->opcode == GEN6_OPCODE_IF) { if (!nest_level) { /* the following instruction */ jip = (dist + 1) * 2; @@ -381,7 +381,7 @@ patch_if_else_jip(struct toy_compiler *tc, struct toy_inst *inst) } } } - else if (inst2->opcode == BRW_OPCODE_IF) { + else if (inst2->opcode == GEN6_OPCODE_IF) { nest_level++; } @@ -398,7 +398,7 @@ patch_if_else_jip(struct toy_compiler *tc, struct toy_inst *inst) inst->dst = tdst_imm_w(jip); } - inst->thread_ctrl = BRW_THREAD_SWITCH; + inst->thread_ctrl = GEN6_THREADCTRL_SWITCH; } static void @@ -414,9 +414,9 @@ patch_endif_jip(struct toy_compiler *tc, struct toy_inst *inst) continue; switch (inst2->opcode) { - case BRW_OPCODE_ENDIF: - case BRW_OPCODE_ELSE: - case BRW_OPCODE_WHILE: + case GEN6_OPCODE_ENDIF: + case GEN6_OPCODE_ELSE: + case GEN6_OPCODE_WHILE: found = true; break; default: @@ -438,7 +438,7 @@ patch_endif_jip(struct toy_compiler *tc, struct toy_inst *inst) else inst->dst = tdst_imm_w(dist * 2); - inst->thread_ctrl = BRW_THREAD_SWITCH; + inst->thread_ctrl = GEN6_THREADCTRL_SWITCH; } static void @@ -460,9 +460,9 @@ patch_break_continue_jip(struct toy_compiler *tc, struct toy_inst *inst) continue; } - if (inst2->opcode == BRW_OPCODE_ELSE || - inst2->opcode == BRW_OPCODE_ENDIF || - inst2->opcode == BRW_OPCODE_WHILE) { + if (inst2->opcode == GEN6_OPCODE_ELSE || + inst2->opcode == GEN6_OPCODE_ENDIF || + inst2->opcode == GEN6_OPCODE_WHILE) { jip = dist * 2; break; } @@ -479,13 +479,13 @@ patch_break_continue_jip(struct toy_compiler *tc, struct toy_inst *inst) continue; } - if (inst2->opcode == BRW_OPCODE_WHILE) { + if (inst2->opcode == GEN6_OPCODE_WHILE) { if (nest_level) { nest_level--; } else { /* the following instruction */ - if (tc->dev->gen == ILO_GEN(6) && inst->opcode == BRW_OPCODE_BREAK) + if (tc->dev->gen == ILO_GEN(6) && inst->opcode == GEN6_OPCODE_BREAK) dist++; uip = dist * 2; @@ -536,26 +536,26 @@ toy_compiler_legalize_for_asm(struct toy_compiler *tc) inst->src[1].type = inst->src[0].type; switch (inst->opcode) { - case BRW_OPCODE_MATH: + case GEN6_OPCODE_MATH: /* math does not support align16 nor exec_size > 8 */ - inst->access_mode = BRW_ALIGN_1; + inst->access_mode = GEN6_ALIGN_1; - if (inst->exec_size == BRW_EXECUTE_16) { + if (inst->exec_size == GEN6_EXECSIZE_16) { /* * From the Ivy Bridge PRM, volume 4 part 3, page 192: * * "INT DIV function does not support SIMD16." */ if (tc->dev->gen < ILO_GEN(7) || - inst->cond_modifier == BRW_MATH_FUNCTION_INT_DIV_QUOTIENT || - inst->cond_modifier == BRW_MATH_FUNCTION_INT_DIV_REMAINDER) { + inst->cond_modifier == GEN6_MATH_INT_DIV_QUOTIENT || + inst->cond_modifier == GEN6_MATH_INT_DIV_REMAINDER) { struct toy_inst *inst2; - inst->exec_size = BRW_EXECUTE_8; - inst->qtr_ctrl = GEN6_COMPRESSION_1Q; + inst->exec_size = GEN6_EXECSIZE_8; + inst->qtr_ctrl = GEN6_QTRCTRL_1Q; inst2 = tc_duplicate_inst(tc, inst); - inst2->qtr_ctrl = GEN6_COMPRESSION_2Q; + inst2->qtr_ctrl = GEN6_QTRCTRL_2Q; inst2->dst = tdst_offset(inst2->dst, 1, 0); inst2->src[0] = tsrc_offset(inst2->src[0], 1, 0); if (!tsrc_is_null(inst2->src[1])) @@ -565,22 +565,22 @@ toy_compiler_legalize_for_asm(struct toy_compiler *tc) } } break; - case BRW_OPCODE_IF: + case GEN6_OPCODE_IF: if (tc->dev->gen >= ILO_GEN(7) && - inst->cond_modifier != BRW_CONDITIONAL_NONE) { + inst->cond_modifier != GEN6_COND_NORMAL) { struct toy_inst *inst2; inst2 = tc_duplicate_inst(tc, inst); /* replace the original IF by CMP */ - inst->opcode = BRW_OPCODE_CMP; + inst->opcode = GEN6_OPCODE_CMP; /* predicate control instead of condition modifier */ inst2->dst = tdst_null(); inst2->src[0] = tsrc_null(); inst2->src[1] = tsrc_null(); - inst2->cond_modifier = BRW_CONDITIONAL_NONE; - inst2->pred_ctrl = BRW_PREDICATE_NORMAL; + inst2->cond_modifier = GEN6_COND_NORMAL; + inst2->pred_ctrl = GEN6_PREDCTRL_NORMAL; pc++; } @@ -611,18 +611,18 @@ toy_compiler_legalize_for_asm(struct toy_compiler *tc) tc_head(tc); while ((inst = tc_next(tc)) != NULL) { switch (inst->opcode) { - case BRW_OPCODE_IF: - case BRW_OPCODE_ELSE: + case GEN6_OPCODE_IF: + case GEN6_OPCODE_ELSE: patch_if_else_jip(tc, inst); break; - case BRW_OPCODE_ENDIF: + case GEN6_OPCODE_ENDIF: patch_endif_jip(tc, inst); break; - case BRW_OPCODE_WHILE: + case GEN6_OPCODE_WHILE: patch_while_jip(tc, inst); break; - case BRW_OPCODE_BREAK: - case BRW_OPCODE_CONTINUE: + case GEN6_OPCODE_BREAK: + case GEN6_OPCODE_CONT: patch_break_continue_jip(tc, inst); break; default: diff --git a/src/gallium/drivers/ilo/shader/toy_legalize_ra.c b/src/gallium/drivers/ilo/shader/toy_legalize_ra.c index ba05b0a1e2b..b725375fb67 100644 --- a/src/gallium/drivers/ilo/shader/toy_legalize_ra.c +++ b/src/gallium/drivers/ilo/shader/toy_legalize_ra.c @@ -244,7 +244,7 @@ linear_scan_run(struct linear_scan *ls) int reg, count; /* - * BRW_OPCODE_SEND may write to multiple consecutive registers and we need to + * GEN6_OPCODE_SEND may write to multiple consecutive registers and we need to * support that */ for (count = 1; i + count < ls->num_vrfs; count++) { @@ -355,7 +355,7 @@ linear_scan_init_live_intervals(struct linear_scan *ls, do_pc = pc; while_pc = pc + 1; - /* find the matching BRW_OPCODE_WHILE */ + /* find the matching GEN6_OPCODE_WHILE */ LIST_FOR_EACH_ENTRY_FROM(inst2, tc->iter_next, &tc->instructions, list) { if (inst2->marker) { @@ -364,7 +364,7 @@ linear_scan_init_live_intervals(struct linear_scan *ls, continue; } - if (inst2->opcode == BRW_OPCODE_WHILE) { + if (inst2->opcode == GEN6_OPCODE_WHILE) { loop_level--; if (!loop_level) break; @@ -380,13 +380,13 @@ linear_scan_init_live_intervals(struct linear_scan *ls, int num_dst; /* TODO this is a hack */ - if (inst->opcode == BRW_OPCODE_SEND || - inst->opcode == BRW_OPCODE_SENDC) { + if (inst->opcode == GEN6_OPCODE_SEND || + inst->opcode == GEN6_OPCODE_SENDC) { const uint32_t mdesc = inst->src[1].val32; int response_length = (mdesc >> 20) & 0x1f; num_dst = response_length; - if (num_dst > 1 && inst->exec_size == BRW_EXECUTE_16) + if (num_dst > 1 && inst->exec_size == GEN6_EXECSIZE_16) num_dst /= 2; } else { diff --git a/src/gallium/drivers/ilo/shader/toy_optimize.c b/src/gallium/drivers/ilo/shader/toy_optimize.c index 62a663f4901..97a04c88632 100644 --- a/src/gallium/drivers/ilo/shader/toy_optimize.c +++ b/src/gallium/drivers/ilo/shader/toy_optimize.c @@ -40,22 +40,22 @@ eliminate_dead_code(struct toy_compiler *tc) tc_head(tc); while ((inst = tc_next(tc)) != NULL) { switch (inst->opcode) { - case BRW_OPCODE_IF: - case BRW_OPCODE_ELSE: - case BRW_OPCODE_ENDIF: - case BRW_OPCODE_WHILE: - case BRW_OPCODE_BREAK: - case BRW_OPCODE_CONTINUE: - case BRW_OPCODE_SEND: - case BRW_OPCODE_SENDC: - case BRW_OPCODE_NOP: + case GEN6_OPCODE_IF: + case GEN6_OPCODE_ELSE: + case GEN6_OPCODE_ENDIF: + case GEN6_OPCODE_WHILE: + case GEN6_OPCODE_BREAK: + case GEN6_OPCODE_CONT: + case GEN6_OPCODE_SEND: + case GEN6_OPCODE_SENDC: + case GEN6_OPCODE_NOP: /* never eliminated */ break; default: if (tdst_is_null(inst->dst) || !inst->dst.writemask) { - /* math is always BRW_CONDITIONAL_NONE */ - if ((inst->opcode == BRW_OPCODE_MATH || - inst->cond_modifier == BRW_CONDITIONAL_NONE) && + /* math is always GEN6_COND_NORMAL */ + if ((inst->opcode == GEN6_OPCODE_MATH || + inst->cond_modifier == GEN6_COND_NORMAL) && !inst->acc_wr_ctrl) tc_discard_inst(tc, inst); } diff --git a/src/gallium/drivers/ilo/shader/toy_tgsi.c b/src/gallium/drivers/ilo/shader/toy_tgsi.c index a0db732279c..e816ab44c70 100644 --- a/src/gallium/drivers/ilo/shader/toy_tgsi.c +++ b/src/gallium/drivers/ilo/shader/toy_tgsi.c @@ -38,69 +38,69 @@ static const struct { int num_dst; int num_src; } aos_simple_opcode_map[TGSI_OPCODE_LAST] = { - [TGSI_OPCODE_ARL] = { BRW_OPCODE_RNDD, 1, 1 }, - [TGSI_OPCODE_MOV] = { BRW_OPCODE_MOV, 1, 1 }, + [TGSI_OPCODE_ARL] = { GEN6_OPCODE_RNDD, 1, 1 }, + [TGSI_OPCODE_MOV] = { GEN6_OPCODE_MOV, 1, 1 }, [TGSI_OPCODE_RCP] = { TOY_OPCODE_INV, 1, 1 }, [TGSI_OPCODE_RSQ] = { TOY_OPCODE_RSQ, 1, 1 }, - [TGSI_OPCODE_MUL] = { BRW_OPCODE_MUL, 1, 2 }, - [TGSI_OPCODE_ADD] = { BRW_OPCODE_ADD, 1, 2 }, - [TGSI_OPCODE_DP3] = { BRW_OPCODE_DP3, 1, 2 }, - [TGSI_OPCODE_DP4] = { BRW_OPCODE_DP4, 1, 2 }, - [TGSI_OPCODE_MIN] = { BRW_OPCODE_SEL, 1, 2 }, - [TGSI_OPCODE_MAX] = { BRW_OPCODE_SEL, 1, 2 }, + [TGSI_OPCODE_MUL] = { GEN6_OPCODE_MUL, 1, 2 }, + [TGSI_OPCODE_ADD] = { GEN6_OPCODE_ADD, 1, 2 }, + [TGSI_OPCODE_DP3] = { GEN6_OPCODE_DP3, 1, 2 }, + [TGSI_OPCODE_DP4] = { GEN6_OPCODE_DP4, 1, 2 }, + [TGSI_OPCODE_MIN] = { GEN6_OPCODE_SEL, 1, 2 }, + [TGSI_OPCODE_MAX] = { GEN6_OPCODE_SEL, 1, 2 }, /* a later pass will move src[2] to accumulator */ - [TGSI_OPCODE_MAD] = { BRW_OPCODE_MAC, 1, 3 }, - [TGSI_OPCODE_SUB] = { BRW_OPCODE_ADD, 1, 2 }, + [TGSI_OPCODE_MAD] = { GEN6_OPCODE_MAC, 1, 3 }, + [TGSI_OPCODE_SUB] = { GEN6_OPCODE_ADD, 1, 2 }, [TGSI_OPCODE_SQRT] = { TOY_OPCODE_SQRT, 1, 1 }, - [TGSI_OPCODE_FRC] = { BRW_OPCODE_FRC, 1, 1 }, - [TGSI_OPCODE_FLR] = { BRW_OPCODE_RNDD, 1, 1 }, - [TGSI_OPCODE_ROUND] = { BRW_OPCODE_RNDE, 1, 1 }, + [TGSI_OPCODE_FRC] = { GEN6_OPCODE_FRC, 1, 1 }, + [TGSI_OPCODE_FLR] = { GEN6_OPCODE_RNDD, 1, 1 }, + [TGSI_OPCODE_ROUND] = { GEN6_OPCODE_RNDE, 1, 1 }, [TGSI_OPCODE_EX2] = { TOY_OPCODE_EXP, 1, 1 }, [TGSI_OPCODE_LG2] = { TOY_OPCODE_LOG, 1, 1 }, [TGSI_OPCODE_POW] = { TOY_OPCODE_POW, 1, 2 }, - [TGSI_OPCODE_ABS] = { BRW_OPCODE_MOV, 1, 1 }, - [TGSI_OPCODE_DPH] = { BRW_OPCODE_DPH, 1, 2 }, + [TGSI_OPCODE_ABS] = { GEN6_OPCODE_MOV, 1, 1 }, + [TGSI_OPCODE_DPH] = { GEN6_OPCODE_DPH, 1, 2 }, [TGSI_OPCODE_COS] = { TOY_OPCODE_COS, 1, 1 }, [TGSI_OPCODE_KILL] = { TOY_OPCODE_KIL, 0, 0 }, [TGSI_OPCODE_SIN] = { TOY_OPCODE_SIN, 1, 1 }, - [TGSI_OPCODE_ARR] = { BRW_OPCODE_RNDZ, 1, 1 }, - [TGSI_OPCODE_DP2] = { BRW_OPCODE_DP2, 1, 2 }, - [TGSI_OPCODE_IF] = { BRW_OPCODE_IF, 0, 1 }, - [TGSI_OPCODE_UIF] = { BRW_OPCODE_IF, 0, 1 }, - [TGSI_OPCODE_ELSE] = { BRW_OPCODE_ELSE, 0, 0 }, - [TGSI_OPCODE_ENDIF] = { BRW_OPCODE_ENDIF, 0, 0 }, - [TGSI_OPCODE_I2F] = { BRW_OPCODE_MOV, 1, 1 }, - [TGSI_OPCODE_NOT] = { BRW_OPCODE_NOT, 1, 1 }, - [TGSI_OPCODE_TRUNC] = { BRW_OPCODE_RNDZ, 1, 1 }, - [TGSI_OPCODE_SHL] = { BRW_OPCODE_SHL, 1, 2 }, - [TGSI_OPCODE_AND] = { BRW_OPCODE_AND, 1, 2 }, - [TGSI_OPCODE_OR] = { BRW_OPCODE_OR, 1, 2 }, + [TGSI_OPCODE_ARR] = { GEN6_OPCODE_RNDZ, 1, 1 }, + [TGSI_OPCODE_DP2] = { GEN6_OPCODE_DP2, 1, 2 }, + [TGSI_OPCODE_IF] = { GEN6_OPCODE_IF, 0, 1 }, + [TGSI_OPCODE_UIF] = { GEN6_OPCODE_IF, 0, 1 }, + [TGSI_OPCODE_ELSE] = { GEN6_OPCODE_ELSE, 0, 0 }, + [TGSI_OPCODE_ENDIF] = { GEN6_OPCODE_ENDIF, 0, 0 }, + [TGSI_OPCODE_I2F] = { GEN6_OPCODE_MOV, 1, 1 }, + [TGSI_OPCODE_NOT] = { GEN6_OPCODE_NOT, 1, 1 }, + [TGSI_OPCODE_TRUNC] = { GEN6_OPCODE_RNDZ, 1, 1 }, + [TGSI_OPCODE_SHL] = { GEN6_OPCODE_SHL, 1, 2 }, + [TGSI_OPCODE_AND] = { GEN6_OPCODE_AND, 1, 2 }, + [TGSI_OPCODE_OR] = { GEN6_OPCODE_OR, 1, 2 }, [TGSI_OPCODE_MOD] = { TOY_OPCODE_INT_DIV_REMAINDER, 1, 2 }, - [TGSI_OPCODE_XOR] = { BRW_OPCODE_XOR, 1, 2 }, + [TGSI_OPCODE_XOR] = { GEN6_OPCODE_XOR, 1, 2 }, [TGSI_OPCODE_EMIT] = { TOY_OPCODE_EMIT, 0, 0 }, [TGSI_OPCODE_ENDPRIM] = { TOY_OPCODE_ENDPRIM, 0, 0 }, - [TGSI_OPCODE_NOP] = { BRW_OPCODE_NOP, 0, 0 }, + [TGSI_OPCODE_NOP] = { GEN6_OPCODE_NOP, 0, 0 }, [TGSI_OPCODE_KILL_IF] = { TOY_OPCODE_KIL, 0, 1 }, - [TGSI_OPCODE_END] = { BRW_OPCODE_NOP, 0, 0 }, - [TGSI_OPCODE_F2I] = { BRW_OPCODE_MOV, 1, 1 }, + [TGSI_OPCODE_END] = { GEN6_OPCODE_NOP, 0, 0 }, + [TGSI_OPCODE_F2I] = { GEN6_OPCODE_MOV, 1, 1 }, [TGSI_OPCODE_IDIV] = { TOY_OPCODE_INT_DIV_QUOTIENT, 1, 2 }, - [TGSI_OPCODE_IMAX] = { BRW_OPCODE_SEL, 1, 2 }, - [TGSI_OPCODE_IMIN] = { BRW_OPCODE_SEL, 1, 2 }, - [TGSI_OPCODE_INEG] = { BRW_OPCODE_MOV, 1, 1 }, - [TGSI_OPCODE_ISHR] = { BRW_OPCODE_ASR, 1, 2 }, - [TGSI_OPCODE_F2U] = { BRW_OPCODE_MOV, 1, 1 }, - [TGSI_OPCODE_U2F] = { BRW_OPCODE_MOV, 1, 1 }, - [TGSI_OPCODE_UADD] = { BRW_OPCODE_ADD, 1, 2 }, + [TGSI_OPCODE_IMAX] = { GEN6_OPCODE_SEL, 1, 2 }, + [TGSI_OPCODE_IMIN] = { GEN6_OPCODE_SEL, 1, 2 }, + [TGSI_OPCODE_INEG] = { GEN6_OPCODE_MOV, 1, 1 }, + [TGSI_OPCODE_ISHR] = { GEN6_OPCODE_ASR, 1, 2 }, + [TGSI_OPCODE_F2U] = { GEN6_OPCODE_MOV, 1, 1 }, + [TGSI_OPCODE_U2F] = { GEN6_OPCODE_MOV, 1, 1 }, + [TGSI_OPCODE_UADD] = { GEN6_OPCODE_ADD, 1, 2 }, [TGSI_OPCODE_UDIV] = { TOY_OPCODE_INT_DIV_QUOTIENT, 1, 2 }, /* a later pass will move src[2] to accumulator */ - [TGSI_OPCODE_UMAD] = { BRW_OPCODE_MAC, 1, 3 }, - [TGSI_OPCODE_UMAX] = { BRW_OPCODE_SEL, 1, 2 }, - [TGSI_OPCODE_UMIN] = { BRW_OPCODE_SEL, 1, 2 }, + [TGSI_OPCODE_UMAD] = { GEN6_OPCODE_MAC, 1, 3 }, + [TGSI_OPCODE_UMAX] = { GEN6_OPCODE_SEL, 1, 2 }, + [TGSI_OPCODE_UMIN] = { GEN6_OPCODE_SEL, 1, 2 }, [TGSI_OPCODE_UMOD] = { TOY_OPCODE_INT_DIV_REMAINDER, 1, 2 }, - [TGSI_OPCODE_UMUL] = { BRW_OPCODE_MUL, 1, 2 }, - [TGSI_OPCODE_USHR] = { BRW_OPCODE_SHR, 1, 2 }, - [TGSI_OPCODE_UARL] = { BRW_OPCODE_MOV, 1, 1 }, - [TGSI_OPCODE_IABS] = { BRW_OPCODE_MOV, 1, 1 }, + [TGSI_OPCODE_UMUL] = { GEN6_OPCODE_MUL, 1, 2 }, + [TGSI_OPCODE_USHR] = { GEN6_OPCODE_SHR, 1, 2 }, + [TGSI_OPCODE_UARL] = { GEN6_OPCODE_MOV, 1, 1 }, + [TGSI_OPCODE_IABS] = { GEN6_OPCODE_MOV, 1, 1 }, }; static void @@ -111,7 +111,7 @@ aos_simple(struct toy_compiler *tc, { struct toy_inst *inst; int opcode; - int cond_modifier = BRW_CONDITIONAL_NONE; + int cond_modifier = GEN6_COND_NORMAL; int num_dst = tgsi_inst->Instruction.NumDstRegs; int num_src = tgsi_inst->Instruction.NumSrcRegs; int i; @@ -125,7 +125,7 @@ aos_simple(struct toy_compiler *tc, } /* no need to emit nop */ - if (opcode == BRW_OPCODE_NOP) + if (opcode == GEN6_OPCODE_NOP) return; inst = tc_add(tc); @@ -138,12 +138,12 @@ aos_simple(struct toy_compiler *tc, case TGSI_OPCODE_MIN: case TGSI_OPCODE_IMIN: case TGSI_OPCODE_UMIN: - cond_modifier = BRW_CONDITIONAL_L; + cond_modifier = GEN6_COND_L; break; case TGSI_OPCODE_MAX: case TGSI_OPCODE_IMAX: case TGSI_OPCODE_UMAX: - cond_modifier = BRW_CONDITIONAL_GE; + cond_modifier = GEN6_COND_GE; break; case TGSI_OPCODE_SUB: src[1] = tsrc_negate(src[1]); @@ -153,14 +153,14 @@ aos_simple(struct toy_compiler *tc, src[0] = tsrc_absolute(src[0]); break; case TGSI_OPCODE_IF: - cond_modifier = BRW_CONDITIONAL_NEQ; + cond_modifier = GEN6_COND_NZ; num_src = 2; assert(src[0].type == TOY_TYPE_F); src[0] = tsrc_swizzle1(src[0], TOY_SWIZZLE_X); src[1] = tsrc_imm_f(0.0f); break; case TGSI_OPCODE_UIF: - cond_modifier = BRW_CONDITIONAL_NEQ; + cond_modifier = GEN6_COND_NZ; num_src = 2; assert(src[0].type == TOY_TYPE_UD); src[0] = tsrc_swizzle1(src[0], TOY_SWIZZLE_X); @@ -210,29 +210,29 @@ aos_set_on_cond(struct toy_compiler *tc, case TGSI_OPCODE_ISLT: case TGSI_OPCODE_USLT: case TGSI_OPCODE_FSLT: - cond = BRW_CONDITIONAL_L; + cond = GEN6_COND_L; break; case TGSI_OPCODE_SGE: case TGSI_OPCODE_ISGE: case TGSI_OPCODE_USGE: case TGSI_OPCODE_FSGE: - cond = BRW_CONDITIONAL_GE; + cond = GEN6_COND_GE; break; case TGSI_OPCODE_SEQ: case TGSI_OPCODE_USEQ: case TGSI_OPCODE_FSEQ: - cond = BRW_CONDITIONAL_EQ; + cond = GEN6_COND_Z; break; case TGSI_OPCODE_SGT: - cond = BRW_CONDITIONAL_G; + cond = GEN6_COND_G; break; case TGSI_OPCODE_SLE: - cond = BRW_CONDITIONAL_LE; + cond = GEN6_COND_LE; break; case TGSI_OPCODE_SNE: case TGSI_OPCODE_USNE: case TGSI_OPCODE_FSNE: - cond = BRW_CONDITIONAL_NEQ; + cond = GEN6_COND_NZ; break; default: assert(!"invalid aos_set_on_cond() call"); @@ -259,7 +259,7 @@ aos_set_on_cond(struct toy_compiler *tc, tc_MOV(tc, dst[0], zero); tc_CMP(tc, tdst_null(), src[0], src[1], cond); inst = tc_MOV(tc, dst[0], one); - inst->pred_ctrl = BRW_PREDICATE_NORMAL; + inst->pred_ctrl = GEN6_PREDCTRL_NORMAL; } static void @@ -283,9 +283,9 @@ aos_compare(struct toy_compiler *tc, return; } - tc_CMP(tc, tdst_null(), src[0], zero, BRW_CONDITIONAL_L); - inst = tc_SEL(tc, dst[0], src[1], src[2], BRW_CONDITIONAL_NONE); - inst->pred_ctrl = BRW_PREDICATE_NORMAL; + tc_CMP(tc, tdst_null(), src[0], zero, GEN6_COND_L); + inst = tc_SEL(tc, dst[0], src[1], src[2], GEN6_COND_NORMAL); + inst->pred_ctrl = GEN6_PREDCTRL_NORMAL; } static void @@ -315,13 +315,13 @@ aos_set_sign(struct toy_compiler *tc, tc_MOV(tc, dst[0], zero); - tc_CMP(tc, tdst_null(), src[0], zero, BRW_CONDITIONAL_G); + tc_CMP(tc, tdst_null(), src[0], zero, GEN6_COND_G); inst = tc_MOV(tc, dst[0], one); - inst->pred_ctrl = BRW_PREDICATE_NORMAL; + inst->pred_ctrl = GEN6_PREDCTRL_NORMAL; - tc_CMP(tc, tdst_null(), src[0], zero, BRW_CONDITIONAL_L); + tc_CMP(tc, tdst_null(), src[0], zero, GEN6_COND_L); inst = tc_MOV(tc, dst[0], neg_one); - inst->pred_ctrl = BRW_PREDICATE_NORMAL; + inst->pred_ctrl = GEN6_PREDCTRL_NORMAL; } static void @@ -475,19 +475,19 @@ aos_LIT(struct toy_compiler *tc, tc_CMP(tc, tdst_null(), tsrc_swizzle1(src[0], TOY_SWIZZLE_X), tsrc_imm_f(0.0f), - BRW_CONDITIONAL_G); + GEN6_COND_G); inst = tc_MOV(tc, tdst_writemask(dst[0], TOY_WRITEMASK_Y), tsrc_swizzle1(src[0], TOY_SWIZZLE_X)); - inst->pred_ctrl = BRW_PREDICATE_NORMAL; + inst->pred_ctrl = GEN6_PREDCTRL_NORMAL; /* clamp W to (-128, 128)? */ inst = tc_POW(tc, tdst_writemask(dst[0], TOY_WRITEMASK_Z), tsrc_swizzle1(src[0], TOY_SWIZZLE_Y), tsrc_swizzle1(src[0], TOY_SWIZZLE_W)); - inst->pred_ctrl = BRW_PREDICATE_NORMAL; + inst->pred_ctrl = GEN6_PREDCTRL_NORMAL; } static void @@ -578,9 +578,9 @@ aos_CND(struct toy_compiler *tc, assert(!"CND untested"); - tc_CMP(tc, tdst_null(), src[2], tsrc_imm_f(0.5f), BRW_CONDITIONAL_G); - inst = tc_SEL(tc, dst[0], src[0], src[1], BRW_CONDITIONAL_NONE); - inst->pred_ctrl = BRW_PREDICATE_NORMAL; + tc_CMP(tc, tdst_null(), src[2], tsrc_imm_f(0.5f), GEN6_COND_G); + inst = tc_SEL(tc, dst[0], src[0], src[1], GEN6_COND_NORMAL); + inst->pred_ctrl = GEN6_PREDCTRL_NORMAL; } static void @@ -605,8 +605,8 @@ aos_CLAMP(struct toy_compiler *tc, { assert(!"CLAMP untested"); - tc_SEL(tc, dst[0], src[0], src[1], BRW_CONDITIONAL_GE); - tc_SEL(tc, dst[0], src[2], tsrc_from(dst[0]), BRW_CONDITIONAL_L); + tc_SEL(tc, dst[0], src[0], src[1], GEN6_COND_GE); + tc_SEL(tc, dst[0], src[2], tsrc_from(dst[0]), GEN6_COND_L); } static void @@ -742,7 +742,7 @@ aos_BRK(struct toy_compiler *tc, struct toy_dst *dst, struct toy_src *src) { - tc_add0(tc, BRW_OPCODE_BREAK); + tc_add0(tc, GEN6_OPCODE_BREAK); } static void @@ -777,7 +777,7 @@ aos_CONT(struct toy_compiler *tc, struct toy_dst *dst, struct toy_src *src) { - tc_add0(tc, BRW_OPCODE_CONTINUE); + tc_add0(tc, GEN6_OPCODE_CONT); } static void @@ -799,7 +799,7 @@ aos_ENDLOOP(struct toy_compiler *tc, struct toy_dst *dst, struct toy_src *src) { - tc_add0(tc, BRW_OPCODE_WHILE); + tc_add0(tc, GEN6_OPCODE_WHILE); } static void @@ -1177,9 +1177,9 @@ soa_if(struct toy_compiler *tc, tsrc_transpose(src_[0], src0); if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_IF) - tc_IF(tc, tdst_null(), src0[0], tsrc_imm_f(0.0f), BRW_CONDITIONAL_NEQ); + tc_IF(tc, tdst_null(), src0[0], tsrc_imm_f(0.0f), GEN6_COND_NZ); else - tc_IF(tc, tdst_null(), src0[0], tsrc_imm_d(0), BRW_CONDITIONAL_NEQ); + tc_IF(tc, tdst_null(), src0[0], tsrc_imm_d(0), GEN6_COND_NZ); } static void @@ -1204,11 +1204,11 @@ soa_LIT(struct toy_compiler *tc, * POW is calculated first because math with pred_ctrl is broken here. * But, why? */ - tc_CMP(tc, tdst_null(), src0[0], tsrc_imm_f(0.0f), BRW_CONDITIONAL_L); + tc_CMP(tc, tdst_null(), src0[0], tsrc_imm_f(0.0f), GEN6_COND_L); inst = tc_MOV(tc, dst0[1], tsrc_imm_f(0.0f)); - inst->pred_ctrl = BRW_PREDICATE_NORMAL; + inst->pred_ctrl = GEN6_PREDCTRL_NORMAL; inst = tc_MOV(tc, dst0[2], tsrc_imm_f(0.0f)); - inst->pred_ctrl = BRW_PREDICATE_NORMAL; + inst->pred_ctrl = GEN6_PREDCTRL_NORMAL; } static void |