diff options
| author | Marek Olšák <[email protected]> | 2017-04-28 19:28:06 +0200 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2017-05-05 00:23:44 +0200 |
| commit | 283a1d1e27b5456cfda848a54b9d74be0993e038 (patch) | |
| tree | fb98ca1e2ef998492ae31a85bc6d5f912339311d /src/gallium/drivers | |
| parent | efa19f5a542709cab7c6aa7f03af959f4394962f (diff) | |
radeonsi/gfx9: make some PA & DB registers match the closed Vulkan driver
Cc: 17.1 <[email protected]>
Reviewed-by: Nicolai Hähnle <[email protected]>
Diffstat (limited to 'src/gallium/drivers')
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_state.c | 21 |
1 files changed, 18 insertions, 3 deletions
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index e967b4b493c..9d5804c380a 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -4568,15 +4568,30 @@ static void si_init_config(struct si_context *sctx) RADEON_PRIO_BORDER_COLORS); if (sctx->b.chip_class >= GFX9) { - si_pm4_set_reg(pm4, R_028060_DB_DFSM_CONTROL, 0); + unsigned num_se = sscreen->b.info.max_se; + unsigned pc_lines = 0; + + switch (sctx->b.family) { + case CHIP_VEGA10: + pc_lines = 4096; + break; + default: + assert(0); + } + + si_pm4_set_reg(pm4, R_028060_DB_DFSM_CONTROL, + S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF)); si_pm4_set_reg(pm4, R_028064_DB_RENDER_FILTER, 0); /* TODO: We can use this to disable RBs for rendering to GART: */ si_pm4_set_reg(pm4, R_02835C_PA_SC_TILE_STEERING_OVERRIDE, 0); si_pm4_set_reg(pm4, R_02883C_PA_SU_OVER_RASTERIZATION_CNTL, 0); /* TODO: Enable the binner: */ si_pm4_set_reg(pm4, R_028C44_PA_SC_BINNER_CNTL_0, - S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC)); - si_pm4_set_reg(pm4, R_028C48_PA_SC_BINNER_CNTL_1, 0); + S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) | + S_028C44_DISABLE_START_OF_PRIM(1)); + si_pm4_set_reg(pm4, R_028C48_PA_SC_BINNER_CNTL_1, + S_028C48_MAX_ALLOC_COUNT(MIN2(128, pc_lines / (4 * num_se))) | + S_028C48_MAX_PRIM_PER_BATCH(1023)); si_pm4_set_reg(pm4, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL, S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1)); si_pm4_set_reg(pm4, R_030968_VGT_INSTANCE_BASE_ID, 0); |