gallium: use PIPE_SHADER_* everywhere, remove TGSI_PROCESSOR_*

Acked-by: Jose Fonseca <[email protected]>

17 files changed, 169 insertions, 169 deletions

diff --git a/src/gallium/drivers/freedreno/a2xx/fd2_compiler.c b/src/gallium/drivers/freedreno/a2xx/fd2_compiler.c
index b48fb4659cd..6829544d354 100644
--- a/src/gallium/drivers/freedreno/a2xx/fd2_compiler.c
+++ b/src/gallium/drivers/freedreno/a2xx/fd2_compiler.c
@@ -167,7 +167,7 @@ compile_init(struct fd2_compile_context *ctx, struct fd_program_stateobj *prog,
 				ctx->output_export_idx[decl->Range.First] =
 						semantic_idx(&decl->Semantic);
 
-				if (ctx->type == TGSI_PROCESSOR_VERTEX) {
+				if (ctx->type == PIPE_SHADER_VERTEX) {
 					switch (name) {
 					case TGSI_SEMANTIC_POSITION:
 						ctx->position = ctx->num_regs[TGSI_FILE_OUTPUT];
@@ -307,7 +307,7 @@ static unsigned
 get_temp_gpr(struct fd2_compile_context *ctx, int idx)
 {
 	unsigned num = idx + ctx->num_regs[TGSI_FILE_INPUT];
-	if (ctx->type == TGSI_PROCESSOR_VERTEX)
+	if (ctx->type == PIPE_SHADER_VERTEX)
 		num++;
 	return num;
 }
@@ -322,7 +322,7 @@ add_dst_reg(struct fd2_compile_context *ctx, struct ir2_instruction *alu,
 	switch (dst->File) {
 	case TGSI_FILE_OUTPUT:
 		flags |= IR2_REG_EXPORT;
-		if (ctx->type == TGSI_PROCESSOR_VERTEX) {
+		if (ctx->type == PIPE_SHADER_VERTEX) {
 			if (dst->Index == ctx->position) {
 				num = 62;
 			} else if (dst->Index == ctx->psize) {
@@ -370,7 +370,7 @@ add_src_reg(struct fd2_compile_context *ctx, struct ir2_instruction *alu,
 		flags |= IR2_REG_CONST;
 		break;
 	case TGSI_FILE_INPUT:
-		if (ctx->type == TGSI_PROCESSOR_VERTEX) {
+		if (ctx->type == PIPE_SHADER_VERTEX) {
 			num = src->Index + 1;
 		} else {
 			num = export_linkage(ctx,
@@ -1162,9 +1162,9 @@ fd2_compile_shader(struct fd_program_stateobj *prog,
 	if (compile_init(&ctx, prog, so) != TGSI_PARSE_OK)
 		return -1;
 
-	if (ctx.type == TGSI_PROCESSOR_VERTEX) {
+	if (ctx.type == PIPE_SHADER_VERTEX) {
 		compile_vtx_fetch(&ctx);
-	} else if (ctx.type == TGSI_PROCESSOR_FRAGMENT) {
+	} else if (ctx.type == PIPE_SHADER_FRAGMENT) {
 		prog->num_exports = 0;
 		memset(prog->export_linkage, 0xff,
 				sizeof(prog->export_linkage));
diff --git a/src/gallium/drivers/freedreno/freedreno_program.c b/src/gallium/drivers/freedreno/freedreno_program.c
index e6a647852a3..9c51119d371 100644
--- a/src/gallium/drivers/freedreno/freedreno_program.c
+++ b/src/gallium/drivers/freedreno/freedreno_program.c
@@ -100,7 +100,7 @@ fd_prog_blit(struct pipe_context *pctx, int rts, bool depth)
 
 	debug_assert(rts <= MAX_RENDER_TARGETS);
 
-	ureg = ureg_create(TGSI_PROCESSOR_FRAGMENT);
+	ureg = ureg_create(PIPE_SHADER_FRAGMENT);
 	if (!ureg)
 		return NULL;
 
diff --git a/src/gallium/drivers/freedreno/ir3/ir3_cmdline.c b/src/gallium/drivers/freedreno/ir3/ir3_cmdline.c
index 7ae4e94f0b3..027673afe1c 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3_cmdline.c
+++ b/src/gallium/drivers/freedreno/ir3/ir3_cmdline.c
@@ -241,13 +241,13 @@ int main(int argc, char **argv)
 
 	tgsi_parse_init(&parse, toks);
 	switch (parse.FullHeader.Processor.Processor) {
-	case TGSI_PROCESSOR_FRAGMENT:
+	case PIPE_SHADER_FRAGMENT:
 		s.type = v.type = SHADER_FRAGMENT;
 		break;
-	case TGSI_PROCESSOR_VERTEX:
+	case PIPE_SHADER_VERTEX:
 		s.type = v.type = SHADER_VERTEX;
 		break;
-	case TGSI_PROCESSOR_COMPUTE:
+	case PIPE_SHADER_COMPUTE:
 		s.type = v.type = SHADER_COMPUTE;
 		break;
 	}
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_surface.c b/src/gallium/drivers/nouveau/nv50/nv50_surface.c
index a284f27c366..61dec3f7be5 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_surface.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_surface.c
@@ -900,7 +900,7 @@ nv50_blitter_make_fp(struct pipe_context *pipe,
        mode != NV50_BLIT_MODE_XS)
       cvt_un8 = true;
 
-   ureg = ureg_create(TGSI_PROCESSOR_FRAGMENT);
+   ureg = ureg_create(PIPE_SHADER_FRAGMENT);
    if (!ureg)
       return NULL;
 
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_program.c b/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
index d3024f9fa06..0f66e2a0bbd 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
@@ -848,7 +848,7 @@ nvc0_program_init_tcp_empty(struct nvc0_context *nvc0)
 {
    struct ureg_program *ureg;
 
-   ureg = ureg_create(TGSI_PROCESSOR_TESS_CTRL);
+   ureg = ureg_create(PIPE_SHADER_TESS_CTRL);
    if (!ureg)
       return;
 
diff --git a/src/gallium/drivers/r300/r300_fs.c b/src/gallium/drivers/r300/r300_fs.c
index 6a96e6720f7..7d76c06ed6b 100644
--- a/src/gallium/drivers/r300/r300_fs.c
+++ b/src/gallium/drivers/r300/r300_fs.c
@@ -220,7 +220,7 @@ static void r300_dummy_fragment_shader(
     struct ureg_src imm;
 
     /* Make a simple fragment shader which outputs (0, 0, 0, 1) */
-    ureg = ureg_create(TGSI_PROCESSOR_FRAGMENT);
+    ureg = ureg_create(PIPE_SHADER_FRAGMENT);
     out = ureg_DECL_output(ureg, TGSI_SEMANTIC_COLOR, 0);
     imm = ureg_imm4f(ureg, 0, 0, 0, 1);
 
diff --git a/src/gallium/drivers/r300/r300_vs.c b/src/gallium/drivers/r300/r300_vs.c
index 33612a322f7..62152714d20 100644
--- a/src/gallium/drivers/r300/r300_vs.c
+++ b/src/gallium/drivers/r300/r300_vs.c
@@ -187,7 +187,7 @@ static void r300_dummy_vertex_shader(
 
     /* Make a simple vertex shader which outputs (0, 0, 0, 1),
      * effectively rendering nothing. */
-    ureg = ureg_create(TGSI_PROCESSOR_VERTEX);
+    ureg = ureg_create(PIPE_SHADER_VERTEX);
     dst = ureg_DECL_output(ureg, TGSI_SEMANTIC_POSITION, 0);
     imm = ureg_imm4f(ureg, 0, 0, 0, 1);
 
diff --git a/src/gallium/drivers/r600/r600_asm.c b/src/gallium/drivers/r600/r600_asm.c
index 2ba6003637e..c48d7586cbb 100644
--- a/src/gallium/drivers/r600/r600_asm.c
+++ b/src/gallium/drivers/r600/r600_asm.c
@@ -1690,7 +1690,7 @@ int r600_bytecode_build(struct r600_bytecode *bc)
 	if (!bc->nstack) // If not 0, Stack_size already provided by llvm
 		bc->nstack = bc->stack.max_entries;
 
-	if ((bc->type == TGSI_PROCESSOR_VERTEX || bc->type == TGSI_PROCESSOR_TESS_EVAL || bc->type == TGSI_PROCESSOR_TESS_CTRL) && !bc->nstack) {
+	if ((bc->type == PIPE_SHADER_VERTEX || bc->type == PIPE_SHADER_TESS_EVAL || bc->type == PIPE_SHADER_TESS_CTRL) && !bc->nstack) {
 		bc->nstack = 1;
 	}
 
diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index 77658f53551..64b049a1ced 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -182,13 +182,13 @@ int r600_pipe_shader_create(struct pipe_context *ctx,
 		R600_ERR("translation from TGSI failed !\n");
 		goto error;
 	}
-	if (shader->shader.processor_type == TGSI_PROCESSOR_VERTEX) {
+	if (shader->shader.processor_type == PIPE_SHADER_VERTEX) {
 		/* only disable for vertex shaders in tess paths */
 		if (key.vs.as_ls)
 			use_sb = 0;
 	}
-	use_sb &= (shader->shader.processor_type != TGSI_PROCESSOR_TESS_CTRL);
-	use_sb &= (shader->shader.processor_type != TGSI_PROCESSOR_TESS_EVAL);
+	use_sb &= (shader->shader.processor_type != PIPE_SHADER_TESS_CTRL);
+	use_sb &= (shader->shader.processor_type != PIPE_SHADER_TESS_EVAL);
 
 	/* disable SB for shaders using doubles */
 	use_sb &= !shader->shader.uses_doubles;
@@ -234,16 +234,16 @@ int r600_pipe_shader_create(struct pipe_context *ctx,
 
 	/* Build state. */
 	switch (shader->shader.processor_type) {
-	case TGSI_PROCESSOR_TESS_CTRL:
+	case PIPE_SHADER_TESS_CTRL:
 		evergreen_update_hs_state(ctx, shader);
 		break;
-	case TGSI_PROCESSOR_TESS_EVAL:
+	case PIPE_SHADER_TESS_EVAL:
 		if (key.tes.as_es)
 			evergreen_update_es_state(ctx, shader);
 		else
 			evergreen_update_vs_state(ctx, shader);
 		break;
-	case TGSI_PROCESSOR_GEOMETRY:
+	case PIPE_SHADER_GEOMETRY:
 		if (rctx->b.chip_class >= EVERGREEN) {
 			evergreen_update_gs_state(ctx, shader);
 			evergreen_update_vs_state(ctx, shader->gs_copy_shader);
@@ -252,7 +252,7 @@ int r600_pipe_shader_create(struct pipe_context *ctx,
 			r600_update_vs_state(ctx, shader->gs_copy_shader);
 		}
 		break;
-	case TGSI_PROCESSOR_VERTEX:
+	case PIPE_SHADER_VERTEX:
 		export_shader = key.vs.as_es;
 		if (rctx->b.chip_class >= EVERGREEN) {
 			if (key.vs.as_ls)
@@ -268,7 +268,7 @@ int r600_pipe_shader_create(struct pipe_context *ctx,
 				r600_update_vs_state(ctx, shader);
 		}
 		break;
-	case TGSI_PROCESSOR_FRAGMENT:
+	case PIPE_SHADER_FRAGMENT:
 		if (rctx->b.chip_class >= EVERGREEN) {
 			evergreen_update_ps_state(ctx, shader);
 		} else {
@@ -412,12 +412,12 @@ static int tgsi_is_supported(struct r600_shader_ctx *ctx)
 		   case TGSI_FILE_CONSTANT:
 			   break;
 		   case TGSI_FILE_INPUT:
-			   if (ctx->type == TGSI_PROCESSOR_GEOMETRY ||
-			       ctx->type == TGSI_PROCESSOR_TESS_CTRL ||
-			       ctx->type == TGSI_PROCESSOR_TESS_EVAL)
+			   if (ctx->type == PIPE_SHADER_GEOMETRY ||
+			       ctx->type == PIPE_SHADER_TESS_CTRL ||
+			       ctx->type == PIPE_SHADER_TESS_EVAL)
 				   break;
 		   case TGSI_FILE_OUTPUT:
-			   if (ctx->type == TGSI_PROCESSOR_TESS_CTRL)
+			   if (ctx->type == PIPE_SHADER_TESS_CTRL)
 				   break;
 		   default:
 			   R600_ERR("unsupported src %d (file %d, dimension %d)\n", j,
@@ -429,7 +429,7 @@ static int tgsi_is_supported(struct r600_shader_ctx *ctx)
 	}
 	for (j = 0; j < i->Instruction.NumDstRegs; j++) {
 		if (i->Dst[j].Register.Dimension) {
-			if (ctx->type == TGSI_PROCESSOR_TESS_CTRL)
+			if (ctx->type == PIPE_SHADER_TESS_CTRL)
 				continue;
 			R600_ERR("unsupported dst (dimension)\n");
 			return -EINVAL;
@@ -864,7 +864,7 @@ static int tgsi_declaration(struct r600_shader_ctx *ctx)
 			ctx->shader->input[i].interpolate = d->Interp.Interpolate;
 			ctx->shader->input[i].interpolate_location = d->Interp.Location;
 			ctx->shader->input[i].gpr = ctx->file_offset[TGSI_FILE_INPUT] + d->Range.First + j;
-			if (ctx->type == TGSI_PROCESSOR_FRAGMENT) {
+			if (ctx->type == PIPE_SHADER_FRAGMENT) {
 				ctx->shader->input[i].spi_sid = r600_spi_sid(&ctx->shader->input[i]);
 				switch (ctx->shader->input[i].name) {
 				case TGSI_SEMANTIC_FACE:
@@ -889,7 +889,7 @@ static int tgsi_declaration(struct r600_shader_ctx *ctx)
 					if ((r = evergreen_interp_input(ctx, i)))
 						return r;
 				}
-			} else if (ctx->type == TGSI_PROCESSOR_GEOMETRY) {
+			} else if (ctx->type == PIPE_SHADER_GEOMETRY) {
 				/* FIXME probably skip inputs if they aren't passed in the ring */
 				ctx->shader->input[i].ring_offset = ctx->next_ring_offset;
 				ctx->next_ring_offset += 16;
@@ -908,9 +908,9 @@ static int tgsi_declaration(struct r600_shader_ctx *ctx)
 			ctx->shader->output[i].gpr = ctx->file_offset[TGSI_FILE_OUTPUT] + d->Range.First + j;
 			ctx->shader->output[i].interpolate = d->Interp.Interpolate;
 			ctx->shader->output[i].write_mask = d->Declaration.UsageMask;
-			if (ctx->type == TGSI_PROCESSOR_VERTEX ||
-			    ctx->type == TGSI_PROCESSOR_GEOMETRY ||
-			    ctx->type == TGSI_PROCESSOR_TESS_EVAL) {
+			if (ctx->type == PIPE_SHADER_VERTEX ||
+			    ctx->type == PIPE_SHADER_GEOMETRY ||
+			    ctx->type == PIPE_SHADER_TESS_EVAL) {
 				ctx->shader->output[i].spi_sid = r600_spi_sid(&ctx->shader->output[i]);
 				switch (d->Semantic.Name) {
 				case TGSI_SEMANTIC_CLIPDIST:
@@ -939,10 +939,10 @@ static int tgsi_declaration(struct r600_shader_ctx *ctx)
 					ctx->cv_output = i;
 					break;
 				}
-				if (ctx->type == TGSI_PROCESSOR_GEOMETRY) {
+				if (ctx->type == PIPE_SHADER_GEOMETRY) {
 					ctx->gs_out_ring_offset += 16;
 				}
-			} else if (ctx->type == TGSI_PROCESSOR_FRAGMENT) {
+			} else if (ctx->type == PIPE_SHADER_FRAGMENT) {
 				switch (d->Semantic.Name) {
 				case TGSI_SEMANTIC_COLOR:
 					ctx->shader->nr_ps_max_color_exports++;
@@ -1342,7 +1342,7 @@ static void tgsi_src(struct r600_shader_ctx *ctx,
 			r600_src->swizzle[2] = 0;
 			r600_src->swizzle[3] = 0;
 			r600_src->sel = 0;
-		} else if (ctx->type != TGSI_PROCESSOR_TESS_CTRL && ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INVOCATIONID) {
+		} else if (ctx->type != PIPE_SHADER_TESS_CTRL && ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INVOCATIONID) {
 			r600_src->swizzle[0] = 3;
 			r600_src->swizzle[1] = 3;
 			r600_src->swizzle[2] = 3;
@@ -1361,7 +1361,7 @@ static void tgsi_src(struct r600_shader_ctx *ctx,
 		} else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_TESSOUTER) {
 			r600_src->sel = 2;
 		} else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_VERTICESIN) {
-			if (ctx->type == TGSI_PROCESSOR_TESS_CTRL) {
+			if (ctx->type == PIPE_SHADER_TESS_CTRL) {
 				r600_src->sel = ctx->tess_input_info;
 				r600_src->swizzle[0] = 2;
 				r600_src->swizzle[1] = 2;
@@ -1374,13 +1374,13 @@ static void tgsi_src(struct r600_shader_ctx *ctx,
 				r600_src->swizzle[2] = 3;
 				r600_src->swizzle[3] = 3;
 			}
-		} else if (ctx->type == TGSI_PROCESSOR_TESS_CTRL && ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_PRIMID) {
+		} else if (ctx->type == PIPE_SHADER_TESS_CTRL && ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_PRIMID) {
 			r600_src->sel = 0;
 			r600_src->swizzle[0] = 0;
 			r600_src->swizzle[1] = 0;
 			r600_src->swizzle[2] = 0;
 			r600_src->swizzle[3] = 0;
-		} else if (ctx->type == TGSI_PROCESSOR_TESS_EVAL && ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_PRIMID) {
+		} else if (ctx->type == PIPE_SHADER_TESS_EVAL && ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_PRIMID) {
 			r600_src->sel = 0;
 			r600_src->swizzle[0] = 3;
 			r600_src->swizzle[1] = 3;
@@ -1853,19 +1853,19 @@ static int tgsi_split_lds_inputs(struct r600_shader_ctx *ctx)
 	for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
 		struct tgsi_full_src_register *src = &inst->Src[i];
 
-		if (ctx->type == TGSI_PROCESSOR_TESS_EVAL && src->Register.File == TGSI_FILE_INPUT) {
+		if (ctx->type == PIPE_SHADER_TESS_EVAL && src->Register.File == TGSI_FILE_INPUT) {
 			int treg = r600_get_temp(ctx);
 			fetch_tes_input(ctx, src, treg);
 			ctx->src[i].sel = treg;
 			ctx->src[i].rel = 0;
 		}
-		if (ctx->type == TGSI_PROCESSOR_TESS_CTRL && src->Register.File == TGSI_FILE_INPUT) {
+		if (ctx->type == PIPE_SHADER_TESS_CTRL && src->Register.File == TGSI_FILE_INPUT) {
 			int treg = r600_get_temp(ctx);
 			fetch_tcs_input(ctx, src, treg);
 			ctx->src[i].sel = treg;
 			ctx->src[i].rel = 0;
 		}
-		if (ctx->type == TGSI_PROCESSOR_TESS_CTRL && src->Register.File == TGSI_FILE_OUTPUT) {
+		if (ctx->type == PIPE_SHADER_TESS_CTRL && src->Register.File == TGSI_FILE_OUTPUT) {
 			int treg = r600_get_temp(ctx);
 			fetch_tcs_output(ctx, src, treg);
 			ctx->src[i].sel = treg;
@@ -2158,7 +2158,7 @@ static int generate_gs_copy_shader(struct r600_context *rctx,
 
 	ctx.shader = &cshader->shader;
 	ctx.bc = &ctx.shader->bc;
-	ctx.type = ctx.bc->type = TGSI_PROCESSOR_VERTEX;
+	ctx.type = ctx.bc->type = PIPE_SHADER_VERTEX;
 
 	r600_bytecode_init(ctx.bc, rctx->b.chip_class, rctx->b.family,
 			   rctx->screen->has_compressed_msaa_texturing);
@@ -2954,7 +2954,7 @@ static int r600_shader_from_tgsi(struct r600_context *rctx,
 	ctx.bc->type = shader->processor_type;
 
 	switch (ctx.type) {
-	case TGSI_PROCESSOR_VERTEX:
+	case PIPE_SHADER_VERTEX:
 		shader->vs_as_gs_a = key.vs.as_gs_a;
 		shader->vs_as_es = key.vs.as_es;
 		shader->vs_as_ls = key.vs.as_ls;
@@ -2963,21 +2963,21 @@ static int r600_shader_from_tgsi(struct r600_context *rctx,
 		if (shader->vs_as_ls)
 			lds_outputs = true;
 		break;
-	case TGSI_PROCESSOR_GEOMETRY:
+	case PIPE_SHADER_GEOMETRY:
 		ring_outputs = true;
 		break;
-	case TGSI_PROCESSOR_TESS_CTRL:
+	case PIPE_SHADER_TESS_CTRL:
 		shader->tcs_prim_mode = key.tcs.prim_mode;
 		lds_outputs = true;
 		lds_inputs = true;
 		break;
-	case TGSI_PROCESSOR_TESS_EVAL:
+	case PIPE_SHADER_TESS_EVAL:
 		shader->tes_as_es = key.tes.as_es;
 		lds_inputs = true;
 		if (shader->tes_as_es)
 			ring_outputs = true;
 		break;
-	case TGSI_PROCESSOR_FRAGMENT:
+	case PIPE_SHADER_FRAGMENT:
 		shader->two_side = key.ps.color_two_side;
 		break;
 	default:
@@ -3030,23 +3030,23 @@ static int r600_shader_from_tgsi(struct r600_context *rctx,
 		ctx.file_offset[i] = 0;
 	}
 
-	if (ctx.type == TGSI_PROCESSOR_VERTEX) {
+	if (ctx.type == PIPE_SHADER_VERTEX) {
 		ctx.file_offset[TGSI_FILE_INPUT] = 1;
 		r600_bytecode_add_cfinst(ctx.bc, CF_OP_CALL_FS);
 	}
-	if (ctx.type == TGSI_PROCESSOR_FRAGMENT) {
+	if (ctx.type == PIPE_SHADER_FRAGMENT) {
 		if (ctx.bc->chip_class >= EVERGREEN)
 			ctx.file_offset[TGSI_FILE_INPUT] = evergreen_gpr_count(&ctx);
 		else
 			ctx.file_offset[TGSI_FILE_INPUT] = allocate_system_value_inputs(&ctx, ctx.file_offset[TGSI_FILE_INPUT]);
 	}
-	if (ctx.type == TGSI_PROCESSOR_GEOMETRY) {
+	if (ctx.type == PIPE_SHADER_GEOMETRY) {
 		/* FIXME 1 would be enough in some cases (3 or less input vertices) */
 		ctx.file_offset[TGSI_FILE_INPUT] = 2;
 	}
-	if (ctx.type == TGSI_PROCESSOR_TESS_CTRL)
+	if (ctx.type == PIPE_SHADER_TESS_CTRL)
 		ctx.file_offset[TGSI_FILE_INPUT] = 1;
-	if (ctx.type == TGSI_PROCESSOR_TESS_EVAL) {
+	if (ctx.type == PIPE_SHADER_TESS_EVAL) {
 		bool add_tesscoord = false, add_tess_inout = false;
 		ctx.file_offset[TGSI_FILE_INPUT] = 1;
 		for (i = 0; i < PIPE_MAX_SHADER_INPUTS; i++) {
@@ -3079,15 +3079,15 @@ static int r600_shader_from_tgsi(struct r600_context *rctx,
 	ctx.bc->index_reg[0] = ctx.bc->ar_reg + 1;
 	ctx.bc->index_reg[1] = ctx.bc->ar_reg + 2;
 
-	if (ctx.type == TGSI_PROCESSOR_TESS_CTRL) {
+	if (ctx.type == PIPE_SHADER_TESS_CTRL) {
 		ctx.tess_input_info = ctx.bc->ar_reg + 3;
 		ctx.tess_output_info = ctx.bc->ar_reg + 4;
 		ctx.temp_reg = ctx.bc->ar_reg + 5;
-	} else if (ctx.type == TGSI_PROCESSOR_TESS_EVAL) {
+	} else if (ctx.type == PIPE_SHADER_TESS_EVAL) {
 		ctx.tess_input_info = 0;
 		ctx.tess_output_info = ctx.bc->ar_reg + 3;
 		ctx.temp_reg = ctx.bc->ar_reg + 4;
-	} else if (ctx.type == TGSI_PROCESSOR_GEOMETRY) {
+	} else if (ctx.type == PIPE_SHADER_GEOMETRY) {
 		ctx.gs_export_gpr_tregs[0] = ctx.bc->ar_reg + 3;
 		ctx.gs_export_gpr_tregs[1] = ctx.bc->ar_reg + 4;
 		ctx.gs_export_gpr_tregs[2] = ctx.bc->ar_reg + 5;
@@ -3126,7 +3126,7 @@ static int r600_shader_from_tgsi(struct r600_context *rctx,
 	if (shader->vs_as_gs_a)
 		vs_add_primid_output(&ctx, key.vs.prim_id_out);
 
-	if (ctx.type == TGSI_PROCESSOR_TESS_EVAL)
+	if (ctx.type == PIPE_SHADER_TESS_EVAL)
 		r600_fetch_tess_io_info(&ctx);
 
 	while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
@@ -3240,7 +3240,7 @@ static int r600_shader_from_tgsi(struct r600_context *rctx,
 		}
 	}
 
-	if (ctx.type == TGSI_PROCESSOR_GEOMETRY) {
+	if (ctx.type == PIPE_SHADER_GEOMETRY) {
 		struct r600_bytecode_alu alu;
 		int r;
 
@@ -3262,7 +3262,7 @@ static int r600_shader_from_tgsi(struct r600_context *rctx,
 		}
 	}
 
-	if (ctx.type == TGSI_PROCESSOR_TESS_CTRL)
+	if (ctx.type == PIPE_SHADER_TESS_CTRL)
 		r600_fetch_tess_io_info(&ctx);
 
 	if (shader->two_side && ctx.colors_used) {
@@ -3287,7 +3287,7 @@ static int r600_shader_from_tgsi(struct r600_context *rctx,
 				goto out_err;
 			if ((r = tgsi_split_literal_constant(&ctx)))
 				goto out_err;
-			if (ctx.type == TGSI_PROCESSOR_GEOMETRY) {
+			if (ctx.type == PIPE_SHADER_GEOMETRY) {
 				if ((r = tgsi_split_gs_inputs(&ctx)))
 					goto out_err;
 			} else if (lds_inputs) {
@@ -3304,7 +3304,7 @@ static int r600_shader_from_tgsi(struct r600_context *rctx,
 			if (r)
 				goto out_err;
 
-			if (ctx.type == TGSI_PROCESSOR_TESS_CTRL) {
+			if (ctx.type == PIPE_SHADER_TESS_CTRL) {
 				r = r600_store_tcs_output(&ctx);
 				if (r)
 					goto out_err;
@@ -3372,9 +3372,9 @@ static int r600_shader_from_tgsi(struct r600_context *rctx,
 	/* Add stream outputs. */
 	if (so.num_outputs) {
 		bool emit = false;
-		if (!lds_outputs && !ring_outputs && ctx.type == TGSI_PROCESSOR_VERTEX)
+		if (!lds_outputs && !ring_outputs && ctx.type == PIPE_SHADER_VERTEX)
 			emit = true;
-		if (!ring_outputs && ctx.type == TGSI_PROCESSOR_TESS_EVAL)
+		if (!ring_outputs && ctx.type == PIPE_SHADER_TESS_EVAL)
 			emit = true;
 		if (emit)
 			emit_streamout(&ctx, &so, -1, NULL);
@@ -3382,11 +3382,11 @@ static int r600_shader_from_tgsi(struct r600_context *rctx,
 	pipeshader->enabled_stream_buffers_mask = ctx.enabled_stream_buffers_mask;
 	convert_edgeflag_to_int(&ctx);
 
-	if (ctx.type == TGSI_PROCESSOR_TESS_CTRL)
+	if (ctx.type == PIPE_SHADER_TESS_CTRL)
 		r600_emit_tess_factor(&ctx);
 
 	if (lds_outputs) {
-		if (ctx.type == TGSI_PROCESSOR_VERTEX) {
+		if (ctx.type == PIPE_SHADER_VERTEX) {
 			if (ctx.shader->noutput)
 				emit_lds_vs_writes(&ctx);
 		}
@@ -3415,8 +3415,8 @@ static int r600_shader_from_tgsi(struct r600_context *rctx,
 			output[j].type = -1;
 			output[j].op = CF_OP_EXPORT;
 			switch (ctx.type) {
-			case TGSI_PROCESSOR_VERTEX:
-			case TGSI_PROCESSOR_TESS_EVAL:
+			case PIPE_SHADER_VERTEX:
+			case PIPE_SHADER_TESS_EVAL:
 				switch (shader->output[i].name) {
 				case TGSI_SEMANTIC_POSITION:
 					output[j].array_base = 60;
@@ -3506,7 +3506,7 @@ static int r600_shader_from_tgsi(struct r600_context *rctx,
 				}
 
 				break;
-			case TGSI_PROCESSOR_FRAGMENT:
+			case PIPE_SHADER_FRAGMENT:
 				if (shader->output[i].name == TGSI_SEMANTIC_COLOR) {
 					/* never export more colors than the number of CBs */
 					if (shader->output[i].sid >= max_color_exports) {
@@ -3560,7 +3560,7 @@ static int r600_shader_from_tgsi(struct r600_context *rctx,
 					goto out_err;
 				}
 				break;
-			case TGSI_PROCESSOR_TESS_CTRL:
+			case PIPE_SHADER_TESS_CTRL:
 				break;
 			default:
 				R600_ERR("unsupported processor type %d\n", ctx.type);
@@ -3575,7 +3575,7 @@ static int r600_shader_from_tgsi(struct r600_context *rctx,
 		}
 
 		/* add fake position export */
-		if ((ctx.type == TGSI_PROCESSOR_VERTEX || ctx.type == TGSI_PROCESSOR_TESS_EVAL) && pos_emitted == false) {
+		if ((ctx.type == PIPE_SHADER_VERTEX || ctx.type == PIPE_SHADER_TESS_EVAL) && pos_emitted == false) {
 			memset(&output[j], 0, sizeof(struct r600_bytecode_output));
 			output[j].gpr = 0;
 			output[j].elem_size = 3;
@@ -3591,7 +3591,7 @@ static int r600_shader_from_tgsi(struct r600_context *rctx,
 		}
 
 		/* add fake param output for vertex shader if no param is exported */
-		if ((ctx.type == TGSI_PROCESSOR_VERTEX || ctx.type == TGSI_PROCESSOR_TESS_EVAL) && next_param_base == 0) {
+		if ((ctx.type == PIPE_SHADER_VERTEX || ctx.type == PIPE_SHADER_TESS_EVAL) && next_param_base == 0) {
 			memset(&output[j], 0, sizeof(struct r600_bytecode_output));
 			output[j].gpr = 0;
 			output[j].elem_size = 3;
@@ -3607,7 +3607,7 @@ static int r600_shader_from_tgsi(struct r600_context *rctx,
 		}
 
 		/* add fake pixel export */
-		if (ctx.type == TGSI_PROCESSOR_FRAGMENT && shader->nr_ps_color_exports == 0) {
+		if (ctx.type == PIPE_SHADER_FRAGMENT && shader->nr_ps_color_exports == 0) {
 			memset(&output[j], 0, sizeof(struct r600_bytecode_output));
 			output[j].gpr = 0;
 			output[j].elem_size = 3;
@@ -3664,7 +3664,7 @@ static int r600_shader_from_tgsi(struct r600_context *rctx,
 		goto out_err;
 	}
 
-	if (ctx.type == TGSI_PROCESSOR_GEOMETRY) {
+	if (ctx.type == PIPE_SHADER_GEOMETRY) {
 		if ((r = generate_gs_copy_shader(rctx, pipeshader, &so)))
 			return r;
 	}
@@ -3731,7 +3731,7 @@ static void tgsi_dst(struct r600_shader_ctx *ctx,
 	if (inst->Instruction.Saturate) {
 		r600_dst->clamp = 1;
 	}
-	if (ctx->type == TGSI_PROCESSOR_TESS_CTRL) {
+	if (ctx->type == PIPE_SHADER_TESS_CTRL) {
 		if (tgsi_dst->Register.File == TGSI_FILE_OUTPUT) {
 			return;
 		}
@@ -6569,7 +6569,7 @@ static inline boolean tgsi_tex_src_requires_loading(struct r600_shader_ctx *ctx,
 		inst->Src[index].Register.File != TGSI_FILE_INPUT &&
 		inst->Src[index].Register.File != TGSI_FILE_OUTPUT) ||
 		ctx->src[index].neg || ctx->src[index].abs ||
-		(inst->Src[index].Register.File == TGSI_FILE_INPUT && ctx->type == TGSI_PROCESSOR_GEOMETRY);
+		(inst->Src[index].Register.File == TGSI_FILE_INPUT && ctx->type == PIPE_SHADER_GEOMETRY);
 }
 
 static inline unsigned tgsi_tex_get_src_gpr(struct r600_shader_ctx *ctx,
diff --git a/src/gallium/drivers/r600/r600_state_common.c b/src/gallium/drivers/r600/r600_state_common.c
index 19c61ff4435..abc41e00846 100644
--- a/src/gallium/drivers/r600/r600_state_common.c
+++ b/src/gallium/drivers/r600/r600_state_common.c
@@ -1378,7 +1378,7 @@ static void r600_generate_fixed_func_tcs(struct r600_context *rctx)
 {
 	struct ureg_src const0, const1;
 	struct ureg_dst tessouter, tessinner;
-	struct ureg_program *ureg = ureg_create(TGSI_PROCESSOR_TESS_CTRL);
+	struct ureg_program *ureg = ureg_create(PIPE_SHADER_TESS_CTRL);
 
 	if (!ureg)
 		return; /* if we get here, we're screwed */
diff --git a/src/gallium/drivers/r600/sb/sb_bc_parser.cpp b/src/gallium/drivers/r600/sb/sb_bc_parser.cpp
index 65aa801fb79..8124525bf4c 100644
--- a/src/gallium/drivers/r600/sb/sb_bc_parser.cpp
+++ b/src/gallium/drivers/r600/sb/sb_bc_parser.cpp
@@ -56,18 +56,18 @@ int bc_parser::decode() {
 
 	if (pshader) {
 		switch (bc->type) {
-		case TGSI_PROCESSOR_FRAGMENT: t = TARGET_PS; break;
-		case TGSI_PROCESSOR_VERTEX:
+		case PIPE_SHADER_FRAGMENT: t = TARGET_PS; break;
+		case PIPE_SHADER_VERTEX:
 			t = pshader->vs_as_ls ? TARGET_LS : (pshader->vs_as_es ? TARGET_ES : TARGET_VS);
 			break;
-		case TGSI_PROCESSOR_GEOMETRY: t = TARGET_GS; break;
-		case TGSI_PROCESSOR_COMPUTE: t = TARGET_COMPUTE; break;
-		case TGSI_PROCESSOR_TESS_CTRL: t = TARGET_HS; break;
-		case TGSI_PROCESSOR_TESS_EVAL: t = pshader->tes_as_es ? TARGET_ES : TARGET_VS; break;
+		case PIPE_SHADER_GEOMETRY: t = TARGET_GS; break;
+		case PIPE_SHADER_COMPUTE: t = TARGET_COMPUTE; break;
+		case PIPE_SHADER_TESS_CTRL: t = TARGET_HS; break;
+		case PIPE_SHADER_TESS_EVAL: t = pshader->tes_as_es ? TARGET_ES : TARGET_VS; break;
 		default: assert(!"unknown shader target"); return -1; break;
 		}
 	} else {
-		if (bc->type == TGSI_PROCESSOR_COMPUTE)
+		if (bc->type == PIPE_SHADER_COMPUTE)
 			t = TARGET_COMPUTE;
 		else
 			t = TARGET_FETCH;
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c b/src/gallium/drivers/radeon/r600_pipe_common.c
index 9ed6da6a82b..929fecb9284 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -965,17 +965,17 @@ bool r600_can_dump_shader(struct r600_common_screen *rscreen,
 			  unsigned processor)
 {
 	switch (processor) {
-	case TGSI_PROCESSOR_VERTEX:
+	case PIPE_SHADER_VERTEX:
 		return (rscreen->debug_flags & DBG_VS) != 0;
-	case TGSI_PROCESSOR_TESS_CTRL:
+	case PIPE_SHADER_TESS_CTRL:
 		return (rscreen->debug_flags & DBG_TCS) != 0;
-	case TGSI_PROCESSOR_TESS_EVAL:
+	case PIPE_SHADER_TESS_EVAL:
 		return (rscreen->debug_flags & DBG_TES) != 0;
-	case TGSI_PROCESSOR_GEOMETRY:
+	case PIPE_SHADER_GEOMETRY:
 		return (rscreen->debug_flags & DBG_GS) != 0;
-	case TGSI_PROCESSOR_FRAGMENT:
+	case PIPE_SHADER_FRAGMENT:
 		return (rscreen->debug_flags & DBG_PS) != 0;
-	case TGSI_PROCESSOR_COMPUTE:
+	case PIPE_SHADER_COMPUTE:
 		return (rscreen->debug_flags & DBG_CS) != 0;
 	default:
 		return false;
diff --git a/src/gallium/drivers/radeon/radeon_llvm_emit.c b/src/gallium/drivers/radeon/radeon_llvm_emit.c
index d3f5ae3fab6..13633d33b04 100644
--- a/src/gallium/drivers/radeon/radeon_llvm_emit.c
+++ b/src/gallium/drivers/radeon/radeon_llvm_emit.c
@@ -81,21 +81,21 @@ void radeon_llvm_shader_type(LLVMValueRef F, unsigned type)
 	enum radeon_llvm_calling_convention calling_conv;
 
 	switch (type) {
-	case TGSI_PROCESSOR_VERTEX:
-	case TGSI_PROCESSOR_TESS_CTRL:
-	case TGSI_PROCESSOR_TESS_EVAL:
+	case PIPE_SHADER_VERTEX:
+	case PIPE_SHADER_TESS_CTRL:
+	case PIPE_SHADER_TESS_EVAL:
 		llvm_type = RADEON_LLVM_SHADER_VS;
 		calling_conv = RADEON_LLVM_AMDGPU_VS;
 		break;
-	case TGSI_PROCESSOR_GEOMETRY:
+	case PIPE_SHADER_GEOMETRY:
 		llvm_type = RADEON_LLVM_SHADER_GS;
 		calling_conv = RADEON_LLVM_AMDGPU_GS;
 		break;
-	case TGSI_PROCESSOR_FRAGMENT:
+	case PIPE_SHADER_FRAGMENT:
 		llvm_type = RADEON_LLVM_SHADER_PS;
 		calling_conv = RADEON_LLVM_AMDGPU_PS;
 		break;
-	case TGSI_PROCESSOR_COMPUTE:
+	case PIPE_SHADER_COMPUTE:
 		llvm_type = RADEON_LLVM_SHADER_CS;
 		calling_conv = RADEON_LLVM_AMDGPU_CS;
 		break;
diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c
index ea183701d05..e277c2f3914 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -70,7 +70,7 @@ struct si_shader_context
 	struct si_shader *shader;
 	struct si_screen *screen;
 
-	unsigned type; /* TGSI_PROCESSOR_* specifies the type of shader. */
+	unsigned type; /* PIPE_SHADER_* specifies the type of shader. */
 	bool is_gs_copy_shader;
 
 	/* Whether to generate the optimized shader variant compiled as a whole
@@ -240,10 +240,10 @@ static LLVMValueRef unpack_param(struct si_shader_context *ctx,
 static LLVMValueRef get_rel_patch_id(struct si_shader_context *ctx)
 {
 	switch (ctx->type) {
-	case TGSI_PROCESSOR_TESS_CTRL:
+	case PIPE_SHADER_TESS_CTRL:
 		return unpack_param(ctx, SI_PARAM_REL_IDS, 0, 8);
 
-	case TGSI_PROCESSOR_TESS_EVAL:
+	case PIPE_SHADER_TESS_EVAL:
 		return LLVMGetParam(ctx->radeon_bld.main_fn,
 				    ctx->param_tes_rel_patch_id);
 
@@ -277,9 +277,9 @@ static LLVMValueRef get_rel_patch_id(struct si_shader_context *ctx)
 static LLVMValueRef
 get_tcs_in_patch_stride(struct si_shader_context *ctx)
 {
-	if (ctx->type == TGSI_PROCESSOR_VERTEX)
+	if (ctx->type == PIPE_SHADER_VERTEX)
 		return unpack_param(ctx, SI_PARAM_LS_OUT_LAYOUT, 0, 13);
-	else if (ctx->type == TGSI_PROCESSOR_TESS_CTRL)
+	else if (ctx->type == PIPE_SHADER_TESS_CTRL)
 		return unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 0, 13);
 	else {
 		assert(0);
@@ -499,16 +499,16 @@ static LLVMValueRef get_primitive_id(struct lp_build_tgsi_context *bld_base,
 		return bld_base->uint_bld.zero;
 
 	switch (ctx->type) {
-	case TGSI_PROCESSOR_VERTEX:
+	case PIPE_SHADER_VERTEX:
 		return LLVMGetParam(ctx->radeon_bld.main_fn,
 				    ctx->param_vs_prim_id);
-	case TGSI_PROCESSOR_TESS_CTRL:
+	case PIPE_SHADER_TESS_CTRL:
 		return LLVMGetParam(ctx->radeon_bld.main_fn,
 				    SI_PARAM_PATCH_ID);
-	case TGSI_PROCESSOR_TESS_EVAL:
+	case PIPE_SHADER_TESS_EVAL:
 		return LLVMGetParam(ctx->radeon_bld.main_fn,
 				    ctx->param_tes_patch_id);
-	case TGSI_PROCESSOR_GEOMETRY:
+	case PIPE_SHADER_GEOMETRY:
 		return LLVMGetParam(ctx->radeon_bld.main_fn,
 				    SI_PARAM_PRIMITIVE_ID);
 	default:
@@ -1189,9 +1189,9 @@ static void declare_system_value(
 		break;
 
 	case TGSI_SEMANTIC_INVOCATIONID:
-		if (ctx->type == TGSI_PROCESSOR_TESS_CTRL)
+		if (ctx->type == PIPE_SHADER_TESS_CTRL)
 			value = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5);
-		else if (ctx->type == TGSI_PROCESSOR_GEOMETRY)
+		else if (ctx->type == PIPE_SHADER_GEOMETRY)
 			value = LLVMGetParam(radeon_bld->main_fn,
 					     SI_PARAM_GS_INSTANCE_ID);
 		else
@@ -1490,7 +1490,7 @@ static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base,
 	/* Specify the target we are exporting */
 	args[3] = lp_build_const_int32(base->gallivm, target);
 
-	if (ctx->type == TGSI_PROCESSOR_FRAGMENT) {
+	if (ctx->type == PIPE_SHADER_FRAGMENT) {
 		const union si_shader_key *key = &ctx->shader->key;
 		unsigned col_formats = key->ps.epilog.spi_shader_col_format;
 		int cbuf = target - V_008DFC_SQ_EXP_MRT;
@@ -2374,7 +2374,7 @@ static void si_llvm_emit_vs_epilogue(struct lp_build_tgsi_context *bld_base)
 	 * an IF statement is added that clamps all colors if the constant
 	 * is true.
 	 */
-	if (ctx->type == TGSI_PROCESSOR_VERTEX) {
+	if (ctx->type == PIPE_SHADER_VERTEX) {
 		struct lp_build_if_state if_ctx;
 		LLVMValueRef cond = NULL;
 		LLVMValueRef addr, val;
@@ -4748,7 +4748,7 @@ static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
 	/* The real barrier instruction isn’t needed, because an entire patch
 	 * always fits into a single wave.
 	 */
-	if (ctx->type == TGSI_PROCESSOR_TESS_CTRL) {
+	if (ctx->type == PIPE_SHADER_TESS_CTRL) {
 		emit_optimization_barrier(ctx);
 		return;
 	}
@@ -4887,7 +4887,7 @@ static void create_function(struct si_shader_context *ctx)
 	last_array_pointer = SI_PARAM_SHADER_BUFFERS;
 
 	switch (ctx->type) {
-	case TGSI_PROCESSOR_VERTEX:
+	case PIPE_SHADER_VERTEX:
 		params[SI_PARAM_VERTEX_BUFFERS] = const_array(ctx->v16i8, SI_NUM_VERTEX_BUFFERS);
 		last_array_pointer = SI_PARAM_VERTEX_BUFFERS;
 		params[SI_PARAM_BASE_VERTEX] = ctx->i32;
@@ -4936,7 +4936,7 @@ static void create_function(struct si_shader_context *ctx)
 		}
 		break;
 
-	case TGSI_PROCESSOR_TESS_CTRL:
+	case PIPE_SHADER_TESS_CTRL:
 		params[SI_PARAM_TCS_OUT_OFFSETS] = ctx->i32;
 		params[SI_PARAM_TCS_OUT_LAYOUT] = ctx->i32;
 		params[SI_PARAM_TCS_IN_LAYOUT] = ctx->i32;
@@ -4958,7 +4958,7 @@ static void create_function(struct si_shader_context *ctx)
 		}
 		break;
 
-	case TGSI_PROCESSOR_TESS_EVAL:
+	case PIPE_SHADER_TESS_EVAL:
 		params[SI_PARAM_TCS_OUT_OFFSETS] = ctx->i32;
 		params[SI_PARAM_TCS_OUT_LAYOUT] = ctx->i32;
 		num_params = SI_PARAM_TCS_OUT_LAYOUT+1;
@@ -4983,7 +4983,7 @@ static void create_function(struct si_shader_context *ctx)
 				returns[num_returns++] = ctx->f32;
 		break;
 
-	case TGSI_PROCESSOR_GEOMETRY:
+	case PIPE_SHADER_GEOMETRY:
 		params[SI_PARAM_GS2VS_OFFSET] = ctx->i32;
 		params[SI_PARAM_GS_WAVE_ID] = ctx->i32;
 		last_sgpr = SI_PARAM_GS_WAVE_ID;
@@ -5000,7 +5000,7 @@ static void create_function(struct si_shader_context *ctx)
 		num_params = SI_PARAM_GS_INSTANCE_ID+1;
 		break;
 
-	case TGSI_PROCESSOR_FRAGMENT:
+	case PIPE_SHADER_FRAGMENT:
 		params[SI_PARAM_ALPHA_REF] = ctx->f32;
 		params[SI_PARAM_PRIM_MASK] = ctx->i32;
 		last_sgpr = SI_PARAM_PRIM_MASK;
@@ -5054,7 +5054,7 @@ static void create_function(struct si_shader_context *ctx)
 		}
 		break;
 
-	case TGSI_PROCESSOR_COMPUTE:
+	case PIPE_SHADER_COMPUTE:
 		params[SI_PARAM_GRID_SIZE] = v3i32;
 		params[SI_PARAM_BLOCK_ID] = v3i32;
 		last_sgpr = SI_PARAM_BLOCK_ID;
@@ -5073,7 +5073,7 @@ static void create_function(struct si_shader_context *ctx)
 			   num_params, last_array_pointer, last_sgpr);
 
 	/* Reserve register locations for VGPR inputs the PS prolog may need. */
-	if (ctx->type == TGSI_PROCESSOR_FRAGMENT &&
+	if (ctx->type == PIPE_SHADER_FRAGMENT &&
 	    !ctx->is_monolithic) {
 		radeon_llvm_add_attribute(ctx->radeon_bld.main_fn,
 					  "InitialPSInputAddr",
@@ -5085,7 +5085,7 @@ static void create_function(struct si_shader_context *ctx)
 					  S_0286D0_LINEAR_CENTROID_ENA(1) |
 					  S_0286D0_FRONT_FACE_ENA(1) |
 					  S_0286D0_POS_FIXED_PT_ENA(1));
-	} else if (ctx->type == TGSI_PROCESSOR_COMPUTE) {
+	} else if (ctx->type == PIPE_SHADER_COMPUTE) {
 		const unsigned *properties = shader->selector->info.properties;
 		unsigned max_work_group_size =
 		               properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] *
@@ -5108,7 +5108,7 @@ static void create_function(struct si_shader_context *ctx)
 	/* Unused fragment shader inputs are eliminated by the compiler,
 	 * so we don't know yet how many there will be.
 	 */
-	if (ctx->type != TGSI_PROCESSOR_FRAGMENT)
+	if (ctx->type != PIPE_SHADER_FRAGMENT)
 		for (; i < num_params; ++i)
 			shader->info.num_input_vgprs += llvm_get_type_size(params[i]) / 4;
 
@@ -5125,9 +5125,9 @@ static void create_function(struct si_shader_context *ctx)
 						    "ddxy_lds",
 						    LOCAL_ADDR_SPACE);
 
-	if ((ctx->type == TGSI_PROCESSOR_VERTEX && shader->key.vs.as_ls) ||
-	    ctx->type == TGSI_PROCESSOR_TESS_CTRL ||
-	    ctx->type == TGSI_PROCESSOR_TESS_EVAL)
+	if ((ctx->type == PIPE_SHADER_VERTEX && shader->key.vs.as_ls) ||
+	    ctx->type == PIPE_SHADER_TESS_CTRL ||
+	    ctx->type == PIPE_SHADER_TESS_EVAL)
 		declare_tess_lds(ctx);
 }
 
@@ -5246,10 +5246,10 @@ static void preload_streamout_buffers(struct si_shader_context *ctx)
 
 	/* Streamout can only be used if the shader is compiled as VS. */
 	if (!ctx->shader->selector->so.num_outputs ||
-	    (ctx->type == TGSI_PROCESSOR_VERTEX &&
+	    (ctx->type == PIPE_SHADER_VERTEX &&
 	     (ctx->shader->key.vs.as_es ||
 	      ctx->shader->key.vs.as_ls)) ||
-	    (ctx->type == TGSI_PROCESSOR_TESS_EVAL &&
+	    (ctx->type == PIPE_SHADER_TESS_EVAL &&
 	     ctx->shader->key.tes.as_es))
 		return;
 
@@ -5279,13 +5279,13 @@ static void preload_ring_buffers(struct si_shader_context *ctx)
 	LLVMValueRef buf_ptr = LLVMGetParam(ctx->radeon_bld.main_fn,
 					    SI_PARAM_RW_BUFFERS);
 
-	if ((ctx->type == TGSI_PROCESSOR_VERTEX &&
+	if ((ctx->type == PIPE_SHADER_VERTEX &&
 	     ctx->shader->key.vs.as_es) ||
-	    (ctx->type == TGSI_PROCESSOR_TESS_EVAL &&
+	    (ctx->type == PIPE_SHADER_TESS_EVAL &&
 	     ctx->shader->key.tes.as_es) ||
-	    ctx->type == TGSI_PROCESSOR_GEOMETRY) {
+	    ctx->type == PIPE_SHADER_GEOMETRY) {
 		unsigned ring =
-			ctx->type == TGSI_PROCESSOR_GEOMETRY ? SI_GS_RING_ESGS
+			ctx->type == PIPE_SHADER_GEOMETRY ? SI_GS_RING_ESGS
 							     : SI_ES_RING_ESGS;
 		LLVMValueRef offset = lp_build_const_int32(gallivm, ring);
 
@@ -5299,7 +5299,7 @@ static void preload_ring_buffers(struct si_shader_context *ctx)
 		ctx->gsvs_ring[0] =
 			build_indexed_load_const(ctx, buf_ptr, offset);
 	}
-	if (ctx->type == TGSI_PROCESSOR_GEOMETRY) {
+	if (ctx->type == PIPE_SHADER_GEOMETRY) {
 		int i;
 		for (i = 0; i < 4; i++) {
 			LLVMValueRef offset = lp_build_const_int32(gallivm, SI_GS_RING_GSVS0 + i);
@@ -5545,7 +5545,7 @@ static void si_shader_dump_stats(struct si_screen *sscreen,
 	unsigned max_simd_waves = 10;
 
 	/* Compute LDS usage for PS. */
-	if (processor == TGSI_PROCESSOR_FRAGMENT) {
+	if (processor == PIPE_SHADER_FRAGMENT) {
 		/* The minimum usage per wave is (num_inputs * 36). The maximum
 		 * usage is (num_inputs * 36 * 16).
 		 * We can get anything in between and it varies between waves.
@@ -5576,7 +5576,7 @@ static void si_shader_dump_stats(struct si_screen *sscreen,
 
 	if (file != stderr ||
 	    r600_can_dump_shader(&sscreen->b, processor)) {
-		if (processor == TGSI_PROCESSOR_FRAGMENT) {
+		if (processor == PIPE_SHADER_FRAGMENT) {
 			fprintf(file, "*** SHADER CONFIG ***\n"
 				"SPI_PS_INPUT_ADDR = 0x%04x\n"
 				"SPI_PS_INPUT_ENA  = 0x%04x\n",
@@ -5608,28 +5608,28 @@ static const char *si_get_shader_name(struct si_shader *shader,
 				      unsigned processor)
 {
 	switch (processor) {
-	case TGSI_PROCESSOR_VERTEX:
+	case PIPE_SHADER_VERTEX:
 		if (shader->key.vs.as_es)
 			return "Vertex Shader as ES";
 		else if (shader->key.vs.as_ls)
 			return "Vertex Shader as LS";
 		else
 			return "Vertex Shader as VS";
-	case TGSI_PROCESSOR_TESS_CTRL:
+	case PIPE_SHADER_TESS_CTRL:
 		return "Tessellation Control Shader";
-	case TGSI_PROCESSOR_TESS_EVAL:
+	case PIPE_SHADER_TESS_EVAL:
 		if (shader->key.tes.as_es)
 			return "Tessellation Evaluation Shader as ES";
 		else
 			return "Tessellation Evaluation Shader as VS";
-	case TGSI_PROCESSOR_GEOMETRY:
+	case PIPE_SHADER_GEOMETRY:
 		if (shader->gs_copy_shader == NULL)
 			return "GS Copy Shader as VS";
 		else
 			return "Geometry Shader";
-	case TGSI_PROCESSOR_FRAGMENT:
+	case PIPE_SHADER_FRAGMENT:
 		return "Pixel Shader";
-	case TGSI_PROCESSOR_COMPUTE:
+	case PIPE_SHADER_COMPUTE:
 		return "Compute Shader";
 	default:
 		return "Unknown Shader";
@@ -5718,10 +5718,10 @@ int si_compile_llvm(struct si_screen *sscreen,
 	 * concatenated.
 	 */
 	if (binary->rodata_size &&
-	    (processor == TGSI_PROCESSOR_VERTEX ||
-	     processor == TGSI_PROCESSOR_TESS_CTRL ||
-	     processor == TGSI_PROCESSOR_TESS_EVAL ||
-	     processor == TGSI_PROCESSOR_FRAGMENT)) {
+	    (processor == PIPE_SHADER_VERTEX ||
+	     processor == PIPE_SHADER_TESS_CTRL ||
+	     processor == PIPE_SHADER_TESS_EVAL ||
+	     processor == PIPE_SHADER_FRAGMENT)) {
 		fprintf(stderr, "radeonsi: The shader can't have rodata.");
 		return -EINVAL;
 	}
@@ -5746,7 +5746,7 @@ static int si_generate_gs_copy_shader(struct si_screen *sscreen,
 	outputs = MALLOC(gsinfo->num_outputs * sizeof(outputs[0]));
 
 	si_init_shader_ctx(ctx, sscreen, ctx->shader, ctx->tm);
-	ctx->type = TGSI_PROCESSOR_VERTEX;
+	ctx->type = PIPE_SHADER_VERTEX;
 	ctx->is_gs_copy_shader = true;
 
 	create_meta_data(ctx);
@@ -5794,7 +5794,7 @@ static int si_generate_gs_copy_shader(struct si_screen *sscreen,
 
 	/* Dump LLVM IR before any optimization passes */
 	if (sscreen->b.debug_flags & DBG_PREOPT_IR &&
-	    r600_can_dump_shader(&sscreen->b, TGSI_PROCESSOR_GEOMETRY))
+	    r600_can_dump_shader(&sscreen->b, PIPE_SHADER_GEOMETRY))
 		LLVMDumpModule(bld_base->base.gallivm->module);
 
 	radeon_llvm_finalize_module(&ctx->radeon_bld);
@@ -5802,13 +5802,13 @@ static int si_generate_gs_copy_shader(struct si_screen *sscreen,
 	r = si_compile_llvm(sscreen, &ctx->shader->binary,
 			    &ctx->shader->config, ctx->tm,
 			    bld_base->base.gallivm->module,
-			    debug, TGSI_PROCESSOR_GEOMETRY,
+			    debug, PIPE_SHADER_GEOMETRY,
 			    "GS Copy Shader");
 	if (!r) {
-		if (r600_can_dump_shader(&sscreen->b, TGSI_PROCESSOR_GEOMETRY))
+		if (r600_can_dump_shader(&sscreen->b, PIPE_SHADER_GEOMETRY))
 			fprintf(stderr, "GS Copy Shader:\n");
 		si_shader_dump(sscreen, ctx->shader, debug,
-			       TGSI_PROCESSOR_GEOMETRY, stderr);
+			       PIPE_SHADER_GEOMETRY, stderr);
 		r = si_shader_binary_upload(sscreen, ctx->shader);
 	}
 
@@ -5998,7 +5998,7 @@ int si_compile_tgsi_shader(struct si_screen *sscreen,
 	ctx.radeon_bld.load_system_value = declare_system_value;
 
 	switch (ctx.type) {
-	case TGSI_PROCESSOR_VERTEX:
+	case PIPE_SHADER_VERTEX:
 		ctx.radeon_bld.load_input = declare_input_vs;
 		if (shader->key.vs.as_ls)
 			bld_base->emit_epilogue = si_llvm_emit_ls_epilogue;
@@ -6007,31 +6007,31 @@ int si_compile_tgsi_shader(struct si_screen *sscreen,
 		else
 			bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
 		break;
-	case TGSI_PROCESSOR_TESS_CTRL:
+	case PIPE_SHADER_TESS_CTRL:
 		bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tcs;
 		bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = fetch_output_tcs;
 		bld_base->emit_store = store_output_tcs;
 		bld_base->emit_epilogue = si_llvm_emit_tcs_epilogue;
 		break;
-	case TGSI_PROCESSOR_TESS_EVAL:
+	case PIPE_SHADER_TESS_EVAL:
 		bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tes;
 		if (shader->key.tes.as_es)
 			bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
 		else
 			bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
 		break;
-	case TGSI_PROCESSOR_GEOMETRY:
+	case PIPE_SHADER_GEOMETRY:
 		bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
 		bld_base->emit_epilogue = si_llvm_emit_gs_epilogue;
 		break;
-	case TGSI_PROCESSOR_FRAGMENT:
+	case PIPE_SHADER_FRAGMENT:
 		ctx.radeon_bld.load_input = declare_input_fs;
 		if (is_monolithic)
 			bld_base->emit_epilogue = si_llvm_emit_fs_epilogue;
 		else
 			bld_base->emit_epilogue = si_llvm_return_fs_outputs;
 		break;
-	case TGSI_PROCESSOR_COMPUTE:
+	case PIPE_SHADER_COMPUTE:
 		ctx.radeon_bld.declare_memory_region = declare_compute_memory;
 		break;
 	default:
@@ -6056,7 +6056,7 @@ int si_compile_tgsi_shader(struct si_screen *sscreen,
 					     SI_PARAM_POS_FIXED_PT);
 	}
 
-	if (ctx.type == TGSI_PROCESSOR_GEOMETRY) {
+	if (ctx.type == PIPE_SHADER_GEOMETRY) {
 		int i;
 		for (i = 0; i < 4; i++) {
 			ctx.gs_next_vertex[i] =
@@ -6094,7 +6094,7 @@ int si_compile_tgsi_shader(struct si_screen *sscreen,
 		shader->info.num_input_sgprs += 1; /* scratch byte offset */
 
 	/* Calculate the number of fragment input VGPRs. */
-	if (ctx.type == TGSI_PROCESSOR_FRAGMENT) {
+	if (ctx.type == PIPE_SHADER_FRAGMENT) {
 		shader->info.num_input_vgprs = 0;
 		shader->info.face_vgpr_index = -1;
 
@@ -6134,7 +6134,7 @@ int si_compile_tgsi_shader(struct si_screen *sscreen,
 			shader->info.num_input_vgprs += 1;
 	}
 
-	if (ctx.type == TGSI_PROCESSOR_GEOMETRY) {
+	if (ctx.type == PIPE_SHADER_GEOMETRY) {
 		shader->gs_copy_shader = CALLOC_STRUCT(si_shader);
 		shader->gs_copy_shader->selector = shader->selector;
 		ctx.shader = shader->gs_copy_shader;
@@ -6232,7 +6232,7 @@ static bool si_compile_vs_prolog(struct si_screen *sscreen,
 	bool status = true;
 
 	si_init_shader_ctx(&ctx, sscreen, &shader, tm);
-	ctx.type = TGSI_PROCESSOR_VERTEX;
+	ctx.type = PIPE_SHADER_VERTEX;
 	ctx.param_vertex_id = key->vs_prolog.num_input_sgprs;
 	ctx.param_instance_id = key->vs_prolog.num_input_sgprs + 3;
 
@@ -6340,7 +6340,7 @@ static bool si_compile_vs_epilog(struct si_screen *sscreen,
 	bool status = true;
 
 	si_init_shader_ctx(&ctx, sscreen, NULL, tm);
-	ctx.type = TGSI_PROCESSOR_VERTEX;
+	ctx.type = PIPE_SHADER_VERTEX;
 
 	/* Declare input VGPRs. */
 	num_params = key->vs_epilog.states.export_prim_id ?
@@ -6498,7 +6498,7 @@ static bool si_compile_tcs_epilog(struct si_screen *sscreen,
 	bool status = true;
 
 	si_init_shader_ctx(&ctx, sscreen, &shader, tm);
-	ctx.type = TGSI_PROCESSOR_TESS_CTRL;
+	ctx.type = PIPE_SHADER_TESS_CTRL;
 	shader.key.tcs.epilog = key->tcs_epilog.states;
 
 	/* Declare inputs. Only RW_BUFFERS and TESS_FACTOR_OFFSET are used. */
@@ -6588,7 +6588,7 @@ static bool si_compile_ps_prolog(struct si_screen *sscreen,
 	bool status = true;
 
 	si_init_shader_ctx(&ctx, sscreen, &shader, tm);
-	ctx.type = TGSI_PROCESSOR_FRAGMENT;
+	ctx.type = PIPE_SHADER_FRAGMENT;
 	shader.key.ps.prolog = key->ps_prolog.states;
 
 	/* Number of inputs + 8 color elements. */
@@ -6750,7 +6750,7 @@ static bool si_compile_ps_epilog(struct si_screen *sscreen,
 	bool status = true;
 
 	si_init_shader_ctx(&ctx, sscreen, &shader, tm);
-	ctx.type = TGSI_PROCESSOR_FRAGMENT;
+	ctx.type = PIPE_SHADER_FRAGMENT;
 	shader.key.ps.epilog = key->ps_epilog.states;
 
 	/* Declare input SGPRs. */
diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c
index 4fc079716a7..80247f7281a 100644
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -999,20 +999,20 @@ static void si_parse_next_shader_property(const struct tgsi_shader_info *info,
 	unsigned next_shader = info->properties[TGSI_PROPERTY_NEXT_SHADER];
 
 	switch (info->processor) {
-	case TGSI_PROCESSOR_VERTEX:
+	case PIPE_SHADER_VERTEX:
 		switch (next_shader) {
-		case TGSI_PROCESSOR_GEOMETRY:
+		case PIPE_SHADER_GEOMETRY:
 			key->vs.as_es = 1;
 			break;
-		case TGSI_PROCESSOR_TESS_CTRL:
-		case TGSI_PROCESSOR_TESS_EVAL:
+		case PIPE_SHADER_TESS_CTRL:
+		case PIPE_SHADER_TESS_EVAL:
 			key->vs.as_ls = 1;
 			break;
 		}
 		break;
 
-	case TGSI_PROCESSOR_TESS_EVAL:
-		if (next_shader == TGSI_PROCESSOR_GEOMETRY)
+	case PIPE_SHADER_TESS_EVAL:
+		if (next_shader == PIPE_SHADER_GEOMETRY)
 			key->tes.as_es = 1;
 		break;
 	}
@@ -1805,7 +1805,7 @@ static void si_generate_fixed_func_tcs(struct si_context *sctx)
 {
 	struct ureg_src outer, inner;
 	struct ureg_dst tessouter, tessinner;
-	struct ureg_program *ureg = ureg_create(TGSI_PROCESSOR_TESS_CTRL);
+	struct ureg_program *ureg = ureg_create(PIPE_SHADER_TESS_CTRL);
 
 	if (!ureg)
 		return; /* if we get here, we're screwed */
diff --git a/src/gallium/drivers/svga/svga_state_fs.c b/src/gallium/drivers/svga/svga_state_fs.c
index bac91669be1..72d591bb1bb 100644
--- a/src/gallium/drivers/svga/svga_state_fs.c
+++ b/src/gallium/drivers/svga/svga_state_fs.c
@@ -63,7 +63,7 @@ get_dummy_fragment_shader(void)
    struct ureg_dst dst;
    unsigned num_tokens;
 
-   ureg = ureg_create(TGSI_PROCESSOR_FRAGMENT);
+   ureg = ureg_create(PIPE_SHADER_FRAGMENT);
    if (!ureg)
       return NULL;
 
diff --git a/src/gallium/drivers/svga/svga_state_vs.c b/src/gallium/drivers/svga/svga_state_vs.c
index a103dab25fe..f46e6b3d4da 100644
--- a/src/gallium/drivers/svga/svga_state_vs.c
+++ b/src/gallium/drivers/svga/svga_state_vs.c
@@ -54,7 +54,7 @@ get_dummy_vertex_shader(void)
    struct ureg_dst dst;
    unsigned num_tokens;
 
-   ureg = ureg_create(TGSI_PROCESSOR_VERTEX);
+   ureg = ureg_create(PIPE_SHADER_VERTEX);
    if (!ureg)
       return NULL;
 
@@ -273,7 +273,7 @@ compile_passthrough_vs(struct svga_context *svga,
 
    num_inputs = fs->base.info.num_inputs;
 
-   ureg = ureg_create(TGSI_PROCESSOR_VERTEX);
+   ureg = ureg_create(PIPE_SHADER_VERTEX);
    if (!ureg)
       return PIPE_ERROR_OUT_OF_MEMORY;