diff options
| author | Rob Clark <[email protected]> | 2013-06-21 15:01:49 -0400 |
|---|---|---|
| committer | Rob Clark <[email protected]> | 2013-06-21 15:37:05 -0400 |
| commit | d4aaa4439a0ecd665a2967e9d36d88e0aa080d6d (patch) | |
| tree | d409a329c9ca35d8462b42357df4b1627549c427 /src/gallium/drivers | |
| parent | fe4ae1163dfcba8b1ba4e9518dd1ee4d658b3e70 (diff) | |
freedreno/a3xx/compiler: add TGSI_OPCODE_ABS
Signed-off-by: Rob Clark <[email protected]>
Diffstat (limited to 'src/gallium/drivers')
| -rw-r--r-- | src/gallium/drivers/freedreno/a3xx/fd3_compiler.c | 20 |
1 files changed, 14 insertions, 6 deletions
diff --git a/src/gallium/drivers/freedreno/a3xx/fd3_compiler.c b/src/gallium/drivers/freedreno/a3xx/fd3_compiler.c index eaf0e74eff7..cf3925a84b2 100644 --- a/src/gallium/drivers/freedreno/a3xx/fd3_compiler.c +++ b/src/gallium/drivers/freedreno/a3xx/fd3_compiler.c @@ -940,12 +940,19 @@ instr_cat2(const struct instr_translater *t, { struct tgsi_dst_register *dst = get_dst(ctx, inst); struct ir3_instruction *instr; - - assert(inst->Instruction.NumSrcRegs == 2); - assert(inst->Instruction.NumDstRegs == 1); + unsigned src0_flags = 0; instr = ir3_instr_create(ctx->ir, 2, t->opc); - instr->cat2.condition = t->arg; + + switch (t->tgsi_opc) { + case TGSI_OPCODE_SLT: + case TGSI_OPCODE_SGE: + instr->cat2.condition = t->arg; + break; + case TGSI_OPCODE_ABS: + src0_flags = IR3_REG_ABS; + break; + } switch (t->opc) { case OPC_ABSNEG_F: @@ -964,11 +971,11 @@ instr_cat2(const struct instr_translater *t, case OPC_CBITS_B: /* these only have one src reg */ vectorize(ctx, instr, dst, 1, - &inst->Src[0].Register, 0); + &inst->Src[0].Register, src0_flags); break; default: vectorize(ctx, instr, dst, 2, - &inst->Src[0].Register, 0, + &inst->Src[0].Register, src0_flags, &inst->Src[1].Register, 0); break; } @@ -1053,6 +1060,7 @@ static const struct instr_translater translaters[TGSI_OPCODE_LAST] = { INSTR(EX2, instr_cat4, .opc = OPC_EXP2), INSTR(LG2, instr_cat4, .opc = OPC_LOG2), INSTR(POW, trans_pow), + INSTR(ABS, instr_cat2, .opc = OPC_ABSNEG_F), INSTR(COS, instr_cat4, .opc = OPC_SIN), INSTR(SIN, instr_cat4, .opc = OPC_COS), INSTR(TEX, trans_samp, .opc = OPC_SAM, .arg = TGSI_OPCODE_TEX), |