radeon/llvm: Fix some coding style issues

14 files changed, 135 insertions, 82 deletions

diff --git a/src/gallium/drivers/radeon/AMDGPUAsmPrinter.cpp b/src/gallium/drivers/radeon/AMDGPUAsmPrinter.cpp
index e751ea57de2..1f36105b251 100644
--- a/src/gallium/drivers/radeon/AMDGPUAsmPrinter.cpp
+++ b/src/gallium/drivers/radeon/AMDGPUAsmPrinter.cpp
@@ -1,3 +1,19 @@
+//===-- AMDGPUAsmPrinter.cpp - AMDGPU Assebly printer  --------------------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// The AMDGPUAsmPrinter is used to print both assembly string and also binary
+// code.  When passed an MCAsmStreamer it prints assembly and when passed
+// an MCObjectStreamer it outputs binary code.
+//
+//===----------------------------------------------------------------------===//
+//
+
 
 #include "AMDGPUAsmPrinter.h"
 #include "AMDGPU.h"
diff --git a/src/gallium/drivers/radeon/AMDGPUAsmPrinter.h b/src/gallium/drivers/radeon/AMDGPUAsmPrinter.h
index 7d2b294e588..b35d2e9b2ca 100644
--- a/src/gallium/drivers/radeon/AMDGPUAsmPrinter.h
+++ b/src/gallium/drivers/radeon/AMDGPUAsmPrinter.h
@@ -1,3 +1,15 @@
+//===-- AMDGPUAsmPrinter.h - Print AMDGPU assembly code -------------------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// AMDGPU Assembly printer class.
+//
+//===----------------------------------------------------------------------===//
 
 #ifndef AMDGPU_ASMPRINTER_H
 #define AMDGPU_ASMPRINTER_H
diff --git a/src/gallium/drivers/radeon/AMDGPUMCInstLower.cpp b/src/gallium/drivers/radeon/AMDGPUMCInstLower.cpp
index 65738c2f96d..f3d80a39c3c 100644
--- a/src/gallium/drivers/radeon/AMDGPUMCInstLower.cpp
+++ b/src/gallium/drivers/radeon/AMDGPUMCInstLower.cpp
@@ -1,3 +1,17 @@
+//===- AMDGPUMCInstLower.cpp - Lower AMDGPU MachineInstr to an MCInst -----===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains code to lower AMDGPU MachineInstrs to their corresponding
+// MCInst.
+//
+//===----------------------------------------------------------------------===//
+//
 
 #include "AMDGPUMCInstLower.h"
 #include "AMDGPUAsmPrinter.h"
@@ -13,7 +27,7 @@ using namespace llvm;
 
 AMDGPUMCInstLower::AMDGPUMCInstLower() { }
 
-void AMDGPUMCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
+void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const {
   OutMI.setOpcode(MI->getOpcode());
 
   for (unsigned i = 0, e = MI->getNumExplicitOperands(); i != e; ++i) {
@@ -56,13 +70,13 @@ void AMDGPUAsmPrinter::EmitInstruction(const MachineInstr *MI) {
     while (I != MBB->end() && I->isInsideBundle()) {
       MCInst MCBundleInst;
       const MachineInstr *BundledInst = I;
-      MCInstLowering.Lower(BundledInst, MCBundleInst);
+      MCInstLowering.lower(BundledInst, MCBundleInst);
       OutStreamer.EmitInstruction(MCBundleInst);
       ++I;
     }
   } else {
     MCInst TmpInst;
-    MCInstLowering.Lower(MI, TmpInst);
+    MCInstLowering.lower(MI, TmpInst);
     OutStreamer.EmitInstruction(TmpInst);
   }
 }
diff --git a/src/gallium/drivers/radeon/AMDGPUMCInstLower.h b/src/gallium/drivers/radeon/AMDGPUMCInstLower.h
index 2ea5b0205eb..3f68ff0874e 100644
--- a/src/gallium/drivers/radeon/AMDGPUMCInstLower.h
+++ b/src/gallium/drivers/radeon/AMDGPUMCInstLower.h
@@ -1,3 +1,11 @@
+//===- AMDGPUMCInstLower.h MachineInstr Lowering Interface ------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
 
 #ifndef AMDGPU_MCINSTLOWER_H
 #define AMDGPU_MCINSTLOWER_H
@@ -12,8 +20,8 @@ class AMDGPUMCInstLower {
 public:
   AMDGPUMCInstLower();
 
-  /// Lower - Lower a MachineInstr to an MCInst
-  void Lower(const MachineInstr *MI, MCInst &OutMI) const;
+  /// lower - Lower a MachineInstr to an MCInst
+  void lower(const MachineInstr *MI, MCInst &OutMI) const;
 
 };
 
diff --git a/src/gallium/drivers/radeon/AMDGPUSubtarget.cpp b/src/gallium/drivers/radeon/AMDGPUSubtarget.cpp
index d1b1d6cfa2a..d4a70b6c62f 100644
--- a/src/gallium/drivers/radeon/AMDGPUSubtarget.cpp
+++ b/src/gallium/drivers/radeon/AMDGPUSubtarget.cpp
@@ -1,3 +1,15 @@
+//===-- AMDGPUSubtarget.cpp - AMDGPU Subtarget Information ----------------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements the AMDGPU specific subclass of TargetSubtarget.
+//
+//===----------------------------------------------------------------------===//
 
 #include "AMDGPUSubtarget.h"
 
diff --git a/src/gallium/drivers/radeon/MCTargetDesc/AMDGPUMCAsmInfo.cpp b/src/gallium/drivers/radeon/MCTargetDesc/AMDGPUMCAsmInfo.cpp
index 4fdd4835ed7..ccd5a3bfaa9 100644
--- a/src/gallium/drivers/radeon/MCTargetDesc/AMDGPUMCAsmInfo.cpp
+++ b/src/gallium/drivers/radeon/MCTargetDesc/AMDGPUMCAsmInfo.cpp
@@ -1,4 +1,4 @@
-//===-- MCTargetDesc/AMDGPUMCAsmInfo.cpp - TODO: Add brief description -------===//
+//===-- MCTargetDesc/AMDGPUMCAsmInfo.cpp - Assembly Info ------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -6,21 +6,14 @@
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
-//
-// TODO: Add full description
-//
-//===----------------------------------------------------------------------===//
 
 #include "AMDGPUMCAsmInfo.h"
-#ifndef NULL
-#define NULL 0
-#endif
 
 using namespace llvm;
 AMDGPUMCAsmInfo::AMDGPUMCAsmInfo(const Target &T, StringRef &TT) : MCAsmInfo()
 {
   HasSingleParameterDotFile = false;
-  WeakDefDirective = NULL;
+  WeakDefDirective = 0;
   //===------------------------------------------------------------------===//
   HasSubsectionsViaSymbols = true;
   HasMachoZeroFillDirective = false;
@@ -51,7 +44,7 @@ AMDGPUMCAsmInfo::AMDGPUMCAsmInfo(const Target &T, StringRef &TT) : MCAsmInfo()
   Data16bitsDirective = ".short\t";
   Data32bitsDirective = ".long\t";
   Data64bitsDirective = ".quad\t";
-  GPRel32Directive = NULL;
+  GPRel32Directive = 0;
   SunStyleELFSectionSwitchSyntax = true;
   UsesELFSectionDirectiveForBSS = true;
   HasMicrosoftFastStdCallMangling = false;
@@ -72,7 +65,7 @@ AMDGPUMCAsmInfo::AMDGPUMCAsmInfo(const Target &T, StringRef &TT) : MCAsmInfo()
   HasNoDeadStrip = true;
   HasSymbolResolver = false;
   WeakRefDirective = ".weakref\t";
-  LinkOnceDirective = NULL;
+  LinkOnceDirective = 0;
   //===--- Dwarf Emission Directives -----------------------------------===//
   HasLEB128 = true;
   SupportsDebugInformation = true;
@@ -82,22 +75,22 @@ AMDGPUMCAsmInfo::AMDGPUMCAsmInfo(const Target &T, StringRef &TT) : MCAsmInfo()
   DwarfUsesLabelOffsetForRanges = true;
 
   //===--- CBE Asm Translation Table -----------------------------------===//
-  AsmTransCBE = NULL;
+  AsmTransCBE = 0;
 }
 const char*
 AMDGPUMCAsmInfo::getDataASDirective(unsigned int Size, unsigned int AS) const
 {
   switch (AS) {
     default:
-      return NULL;
+      return 0;
     case 0:
-      return NULL;
+      return 0;
   };
-  return NULL;
+  return 0;
 }
 
 const MCSection*
 AMDGPUMCAsmInfo::getNonexecutableStackSection(MCContext &CTX) const
 {
-  return NULL;
+  return 0;
 }
diff --git a/src/gallium/drivers/radeon/MCTargetDesc/AMDGPUMCTargetDesc.cpp b/src/gallium/drivers/radeon/MCTargetDesc/AMDGPUMCTargetDesc.cpp
index 523b4da506a..6de20fceda6 100644
--- a/src/gallium/drivers/radeon/MCTargetDesc/AMDGPUMCTargetDesc.cpp
+++ b/src/gallium/drivers/radeon/MCTargetDesc/AMDGPUMCTargetDesc.cpp
@@ -1,3 +1,16 @@
+//===-- AMDGPUMCTargetDesc.cpp - AMDGPU Target Descriptions ---------------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file provides AMDGPU specific target descriptions.
+//
+//===----------------------------------------------------------------------===//
+
 #include "AMDGPUMCTargetDesc.h"
 #include "AMDGPUMCAsmInfo.h"
 #include "InstPrinter/AMDGPUInstPrinter.h"
diff --git a/src/gallium/drivers/radeon/MCTargetDesc/R600MCCodeEmitter.cpp b/src/gallium/drivers/radeon/MCTargetDesc/R600MCCodeEmitter.cpp
index 46360e3ccbd..29f1291aea4 100644
--- a/src/gallium/drivers/radeon/MCTargetDesc/R600MCCodeEmitter.cpp
+++ b/src/gallium/drivers/radeon/MCTargetDesc/R600MCCodeEmitter.cpp
@@ -149,12 +149,6 @@ MCCodeEmitter *llvm::createR600MCCodeEmitter(const MCInstrInfo &MCII,
 
 void R600MCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostream &OS,
                                        SmallVectorImpl<MCFixup> &Fixups) const {
-/*
-  if (MI.getNumOperands() > 1 && MI.getOperand(0).isReg() &&
-      MI.getOperand(0).isDead()) {
-    return;
-  }
-*/
   if (isTexOp(MI.getOpcode())) {
     EmitTexInstr(MI, Fixups, OS);
   } else if (isFCOp(MI.getOpcode())){
@@ -209,12 +203,6 @@ void R600MCCodeEmitter::EmitALUInstr(const MCInst &MI,
   if (GET_FLAG_OPERAND_IDX(MCDesc.TSFlags) != 0)
     NumOperands--;
 
-   // Some instructions are just place holder instructions that represent
-   // operations that the GPU does automatically.  They should be ignored.
-//  if (TII->isPlaceHolderOpcode(MI.getOpcode())) {
-//    return;
-//  }
-
   if(MI.getOpcode() == AMDGPU::PRED_X)
     NumOperands = 2;
 
diff --git a/src/gallium/drivers/radeon/MCTargetDesc/SIMCCodeEmitter.cpp b/src/gallium/drivers/radeon/MCTargetDesc/SIMCCodeEmitter.cpp
index 481e65bf7af..bc0b968bee0 100644
--- a/src/gallium/drivers/radeon/MCTargetDesc/SIMCCodeEmitter.cpp
+++ b/src/gallium/drivers/radeon/MCTargetDesc/SIMCCodeEmitter.cpp
@@ -70,11 +70,6 @@ public:
 
   ~SIMCCodeEmitter() { }
 
-  /// getBinaryCodeForInstr - Function generated by tablegen for encoding
-  /// instructions based on the *.td files.
-//  virtual uint64_t getBinaryCodeForInstr(const MCInst &MI,
-//                                 SmallVectorImpl<MCFixup> &Fixups) const;
-
   /// EncodeInstruction - Encode the instruction and write it to the OS.
   virtual void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
                          SmallVectorImpl<MCFixup> &Fixups) const;
diff --git a/src/gallium/drivers/radeon/R600ExpandSpecialInstrs.cpp b/src/gallium/drivers/radeon/R600ExpandSpecialInstrs.cpp
index 437d5daf309..69ab0ffee8c 100644
--- a/src/gallium/drivers/radeon/R600ExpandSpecialInstrs.cpp
+++ b/src/gallium/drivers/radeon/R600ExpandSpecialInstrs.cpp
@@ -154,7 +154,7 @@ bool R600ExpandSpecialInstrsPass::runOnMachineFunction(MachineFunction &MF) {
                   .addImm(0); // Flag
 
         NewMI->setIsInsideBundle(Chan != 0);
-        TII->AddFlag(NewMI, 0, Flags);
+        TII->addFlag(NewMI, 0, Flags);
       }
       MI.eraseFromParent();
     }
diff --git a/src/gallium/drivers/radeon/R600ISelLowering.cpp b/src/gallium/drivers/radeon/R600ISelLowering.cpp
index f96887c0edb..afa80c5c4dc 100644
--- a/src/gallium/drivers/radeon/R600ISelLowering.cpp
+++ b/src/gallium/drivers/radeon/R600ISelLowering.cpp
@@ -67,7 +67,7 @@ MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter(
                .addOperand(MI->getOperand(1))
                .addImm(0) // Flags
                .addReg(AMDGPU::PRED_SEL_OFF);
-      TII->AddFlag(NewMI, 0, MO_FLAG_CLAMP);
+      TII->addFlag(NewMI, 0, MO_FLAG_CLAMP);
       break;
     }
   case AMDGPU::FABS_R600:
@@ -78,7 +78,7 @@ MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter(
                .addOperand(MI->getOperand(1))
                .addImm(0) // Flags
                .addReg(AMDGPU::PRED_SEL_OFF);
-      TII->AddFlag(NewMI, 1, MO_FLAG_ABS);
+      TII->addFlag(NewMI, 1, MO_FLAG_ABS);
       break;
     }
 
@@ -90,7 +90,7 @@ MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter(
                 .addOperand(MI->getOperand(1))
                 .addImm(0) // Flags
                 .addReg(AMDGPU::PRED_SEL_OFF);
-      TII->AddFlag(NewMI, 1, MO_FLAG_NEG);
+      TII->addFlag(NewMI, 1, MO_FLAG_NEG);
     break;
     }
 
@@ -109,7 +109,7 @@ MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter(
       unsigned maskedRegister = MI->getOperand(0).getReg();
       assert(TargetRegisterInfo::isVirtualRegister(maskedRegister));
       MachineInstr * defInstr = MRI.getVRegDef(maskedRegister);
-      TII->AddFlag(defInstr, 0, MO_FLAG_MASK);
+      TII->addFlag(defInstr, 0, MO_FLAG_MASK);
       // Return early so the instruction is not erased
       return BB;
     }
@@ -206,7 +206,7 @@ MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter(
                 .addOperand(MI->getOperand(1))
                 .addImm(OPCODE_IS_ZERO)
                 .addImm(0); // Flags
-      TII->AddFlag(NewMI, 1, MO_FLAG_PUSH);
+      TII->addFlag(NewMI, 1, MO_FLAG_PUSH);
       BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP))
               .addOperand(MI->getOperand(0))
               .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
@@ -220,7 +220,7 @@ MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter(
               .addOperand(MI->getOperand(1))
               .addImm(OPCODE_IS_ZERO_INT)
               .addImm(0); // Flags
-      TII->AddFlag(NewMI, 1, MO_FLAG_PUSH);
+      TII->addFlag(NewMI, 1, MO_FLAG_PUSH);
       BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP))
              .addOperand(MI->getOperand(0))
               .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
diff --git a/src/gallium/drivers/radeon/R600InstrInfo.cpp b/src/gallium/drivers/radeon/R600InstrInfo.cpp
index 2ef262ddb09..14b42044436 100644
--- a/src/gallium/drivers/radeon/R600InstrInfo.cpp
+++ b/src/gallium/drivers/radeon/R600InstrInfo.cpp
@@ -53,8 +53,8 @@ R600InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
 {
   if (AMDGPU::R600_Reg128RegClass.contains(DestReg)
       && AMDGPU::R600_Reg128RegClass.contains(SrcReg)) {
-    for (unsigned i = 0; i < 4; i++) {
-      unsigned SubRegIndex = RI.getSubRegFromChannel(i);
+    for (unsigned I = 0; I < 4; I++) {
+      unsigned SubRegIndex = RI.getSubRegFromChannel(I);
       BuildMI(MBB, MI, DL, get(AMDGPU::MOV))
               .addReg(RI.getSubReg(DestReg, SubRegIndex), RegState::Define)
               .addReg(RI.getSubReg(SrcReg, SubRegIndex))
@@ -108,9 +108,9 @@ bool R600InstrInfo::isMov(unsigned Opcode) const
 // Some instructions act as place holders to emulate operations that the GPU
 // hardware does automatically. This function can be used to check if
 // an opcode falls into this category.
-bool R600InstrInfo::isPlaceHolderOpcode(unsigned opcode) const
+bool R600InstrInfo::isPlaceHolderOpcode(unsigned Opcode) const
 {
-  switch (opcode) {
+  switch (Opcode) {
   default: return false;
   case AMDGPU::RETURN:
   case AMDGPU::LAST:
@@ -120,9 +120,9 @@ bool R600InstrInfo::isPlaceHolderOpcode(unsigned opcode) const
   }
 }
 
-bool R600InstrInfo::isReductionOp(unsigned opcode) const
+bool R600InstrInfo::isReductionOp(unsigned Opcode) const
 {
-  switch(opcode) {
+  switch(Opcode) {
     default: return false;
     case AMDGPU::DOT4_r600:
     case AMDGPU::DOT4_eg:
@@ -130,9 +130,9 @@ bool R600InstrInfo::isReductionOp(unsigned opcode) const
   }
 }
 
-bool R600InstrInfo::isCubeOp(unsigned opcode) const
+bool R600InstrInfo::isCubeOp(unsigned Opcode) const
 {
-  switch(opcode) {
+  switch(Opcode) {
     default: return false;
     case AMDGPU::CUBE_r600_pseudo:
     case AMDGPU::CUBE_r600_real:
@@ -150,9 +150,9 @@ DFAPacketizer *R600InstrInfo::CreateTargetScheduleState(const TargetMachine *TM,
 }
 
 static bool
-isPredicateSetter(unsigned opcode)
+isPredicateSetter(unsigned Opcode)
 {
-  switch (opcode) {
+  switch (Opcode) {
   case AMDGPU::PRED_X:
     return true;
   default:
@@ -274,7 +274,7 @@ R600InstrInfo::InsertBranch(MachineBasicBlock &MBB,
     } else {
       MachineInstr *PredSet = findFirstPredicateSetterFrom(MBB, MBB.end());
       assert(PredSet && "No previous predicate !");
-      AddFlag(PredSet, 1, MO_FLAG_PUSH);
+      addFlag(PredSet, 1, MO_FLAG_PUSH);
       PredSet->getOperand(2).setImm(Cond[1].getImm());
 
       BuildMI(&MBB, DL, get(AMDGPU::JUMP))
@@ -285,7 +285,7 @@ R600InstrInfo::InsertBranch(MachineBasicBlock &MBB,
   } else {
     MachineInstr *PredSet = findFirstPredicateSetterFrom(MBB, MBB.end());
     assert(PredSet && "No previous predicate !");
-    AddFlag(PredSet, 1, MO_FLAG_PUSH);
+    addFlag(PredSet, 1, MO_FLAG_PUSH);
     PredSet->getOperand(2).setImm(Cond[1].getImm());
     BuildMI(&MBB, DL, get(AMDGPU::JUMP))
             .addMBB(TBB)
@@ -314,7 +314,7 @@ R600InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const
   case AMDGPU::JUMP:
     if (isPredicated(I)) {
       MachineInstr *predSet = findFirstPredicateSetterFrom(MBB, I);
-      ClearFlag(predSet, 1, MO_FLAG_PUSH);
+      clearFlag(predSet, 1, MO_FLAG_PUSH);
     }
     I->eraseFromParent();
     break;
@@ -332,7 +332,7 @@ R600InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const
   case AMDGPU::JUMP:
     if (isPredicated(I)) {
       MachineInstr *predSet = findFirstPredicateSetterFrom(MBB, I);
-      ClearFlag(predSet, 1, MO_FLAG_PUSH);
+      clearFlag(predSet, 1, MO_FLAG_PUSH);
     }
     I->eraseFromParent();
     break;
@@ -481,12 +481,12 @@ int R600InstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
 // Instruction flag getters/setters
 //===----------------------------------------------------------------------===//
 
-bool R600InstrInfo::HasFlagOperand(const MachineInstr &MI) const
+bool R600InstrInfo::hasFlagOperand(const MachineInstr &MI) const
 {
   return GET_FLAG_OPERAND_IDX(get(MI.getOpcode()).TSFlags) != 0;
 }
 
-MachineOperand &R600InstrInfo::GetFlagOp(MachineInstr *MI) const
+MachineOperand &R600InstrInfo::getFlagOp(MachineInstr *MI) const
 {
   unsigned FlagIndex = GET_FLAG_OPERAND_IDX(get(MI->getOpcode()).TSFlags);
   assert(FlagIndex != 0 &&
@@ -496,17 +496,17 @@ MachineOperand &R600InstrInfo::GetFlagOp(MachineInstr *MI) const
   return FlagOp;
 }
 
-void R600InstrInfo::AddFlag(MachineInstr *MI, unsigned Operand,
+void R600InstrInfo::addFlag(MachineInstr *MI, unsigned Operand,
                             unsigned Flag) const
 {
-  MachineOperand &FlagOp = GetFlagOp(MI);
+  MachineOperand &FlagOp = getFlagOp(MI);
   FlagOp.setImm(FlagOp.getImm() | (Flag << (NUM_MO_FLAGS * Operand)));
 }
 
-void R600InstrInfo::ClearFlag(MachineInstr *MI, unsigned Operand,
+void R600InstrInfo::clearFlag(MachineInstr *MI, unsigned Operand,
                               unsigned Flag) const
 {
-  MachineOperand &FlagOp = GetFlagOp(MI);
+  MachineOperand &FlagOp = getFlagOp(MI);
   unsigned InstFlags = FlagOp.getImm();
   InstFlags &= ~(Flag << (NUM_MO_FLAGS * Operand));
   FlagOp.setImm(InstFlags);
diff --git a/src/gallium/drivers/radeon/R600InstrInfo.h b/src/gallium/drivers/radeon/R600InstrInfo.h
index 08228b6f42a..bfe8d034e35 100644
--- a/src/gallium/drivers/radeon/R600InstrInfo.h
+++ b/src/gallium/drivers/radeon/R600InstrInfo.h
@@ -110,19 +110,21 @@ namespace llvm {
   virtual int getInstrLatency(const InstrItineraryData *ItinData,
                               SDNode *Node) const { return 1;}
 
-  bool HasFlagOperand(const MachineInstr &MI) const;
+  ///hasFlagOperand - Returns true if this instruction has an operand for
+  /// storing target flags.
+  bool hasFlagOperand(const MachineInstr &MI) const;
 
-  ///AddFlag - Add one of the MO_FLAG* flags to the specified Operand.
-  void AddFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const;
+  ///addFlag - Add one of the MO_FLAG* flags to the specified Operand.
+  void addFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const;
 
-  ///IsFlagSet - Determine if the specified flag is set on this Operand.
-  bool IsFlagSet(const MachineInstr &MI, unsigned Operand, unsigned Flag) const;
+  ///isFlagSet - Determine if the specified flag is set on this Operand.
+  bool isFlagSet(const MachineInstr &MI, unsigned Operand, unsigned Flag) const;
 
-  ///GetFlagOp - Return the operand containing the flags for this instruction.
-  MachineOperand &GetFlagOp(MachineInstr *MI) const;
+  ///getFlagOp - Return the operand containing the flags for this instruction.
+  MachineOperand &getFlagOp(MachineInstr *MI) const;
 
-  ///ClearFlag - Clear the specified flag on the instruction.
-  void ClearFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const;
+  ///clearFlag - Clear the specified flag on the instruction.
+  void clearFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const;
 };
 
 } // End llvm namespace
diff --git a/src/gallium/drivers/radeon/R600KernelParameters.cpp b/src/gallium/drivers/radeon/R600KernelParameters.cpp
index 87adbe400f3..ef0fc458480 100644
--- a/src/gallium/drivers/radeon/R600KernelParameters.cpp
+++ b/src/gallium/drivers/radeon/R600KernelParameters.cpp
@@ -97,12 +97,12 @@ bool R600KernelParameters::IsOpenCLKernel(const Function* Fun) {
   Module *Mod = const_cast<Function*>(Fun)->getParent();
   NamedMDNode * MD = Mod->getOrInsertNamedMetadata("opencl.kernels");
 
-  if (!MD or !MD->getNumOperands()) {
+  if (!MD || !MD->getNumOperands()) {
     return false;
   }
 
   for (int i = 0; i < int(MD->getNumOperands()); i++) {
-    if (!MD->getOperand(i) or !MD->getOperand(i)->getOperand(0)) {
+    if (!MD->getOperand(i) || !MD->getOperand(i)->getOperand(0)) {
       continue;
     }
 
@@ -145,7 +145,7 @@ bool R600KernelParameters::IsIndirect(Value *Val, std::set<Value*> &Visited) {
   }
 
   if (isa<IntegerType>(Val->getType())) {
-    assert(0 and "Internal error");
+    assert(0 && "Internal error");
     return false;
   }
 
@@ -187,7 +187,7 @@ void R600KernelParameters::AddParam(Argument *Arg) {
   P.OffsetInDW = getListSize();
   P.SizeInDW = CalculateArgumentSize(Arg);
 
-  if (isa<PointerType>(Arg->getType()) and Arg->hasByValAttr()) {
+  if (isa<PointerType>(Arg->getType()) && Arg->hasByValAttr()) {
     std::set<Value*> Visited;
     P.IsIndirect = IsIndirect(P.Val, Visited);
   }
@@ -198,7 +198,7 @@ void R600KernelParameters::AddParam(Argument *Arg) {
 int R600KernelParameters::CalculateArgumentSize(Argument *Arg) {
   Type* T = Arg->getType();
 
-  if (Arg->hasByValAttr() and dyn_cast<PointerType>(T)) {
+  if (Arg->hasByValAttr() && dyn_cast<PointerType>(T)) {
     T = dyn_cast<PointerType>(T)->getElementType();
   }
 
@@ -254,7 +254,7 @@ void R600KernelParameters::Propagate(Value* V, const Twine& Name, bool IsIndirec
     Addrspace = AMDGPUAS::PARAM_D_ADDRESS;
   }
 
-  if (GEP and GEP->getType()->getAddressSpace() != Addrspace) {
+  if (GEP && GEP->getType()->getAddressSpace() != Addrspace) {
     Value *Op = GEP->getPointerOperand();
 
     if (dyn_cast<PointerType>(Op->getType())->getAddressSpace() != Addrspace) {
@@ -330,7 +330,7 @@ Value* R600KernelParameters::ConstantRead(Function *Fun, Param &P) {
   Type * ArgType = P.Val->getType();
   PointerType * ArgPtrType = dyn_cast<PointerType>(P.Val->getType());
 
-  if (ArgPtrType and Arg->hasByValAttr()) {
+  if (ArgPtrType && Arg->hasByValAttr()) {
     Value* ParamAddrSpacePtr = ConstantPointerNull::get(
                                     PointerType::get(Type::getInt32Ty(*Context),
                                     Addrspace));
@@ -364,7 +364,7 @@ Value* R600KernelParameters::handleSpecial(Function* Fun, Param& P) {
 
   assert(!Name.empty());
 
-  if (Name == "image2d_t" or Name == "image3d_t") {
+  if (Name == "image2d_t" || Name == "image3d_t") {
     int LastID = std::max(getLastSpecialID("image2d_t"),
                      getLastSpecialID("image3d_t"));