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authorJerome Glisse <jglisse@redhat.com>2010-09-01 21:57:43 -0400
committerJerome Glisse <jglisse@redhat.com>2010-09-01 21:59:28 -0400
commit31b84acbd2ae2dc7555844c5a2eead932b8759a7 (patch)
treecb54fc0922fa12f05ca688869e3cd21e77cabf66 /src/gallium/drivers
parent39605587951aed546c14febcc26e5a479bf8d807 (diff)
r600g: fix binding of same texture to several target slot
One can bind same texture or sampler to different slot, each slot needs it own state. The solution implemented here is not exactly beautifull or optimal need to think to somethings better. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Diffstat (limited to 'src/gallium/drivers')
-rw-r--r--src/gallium/drivers/r600/r600_context.h13
-rw-r--r--src/gallium/drivers/r600/r600_state.c72
2 files changed, 62 insertions, 23 deletions
diff --git a/src/gallium/drivers/r600/r600_context.h b/src/gallium/drivers/r600/r600_context.h
index eb7a64bfbd5..d4e3baa69d2 100644
--- a/src/gallium/drivers/r600/r600_context.h
+++ b/src/gallium/drivers/r600/r600_context.h
@@ -95,13 +95,16 @@ enum pipe_state_type {
pipe_type_count
};
+#define R600_MAX_RSTATE 16
+
struct r600_context_state {
union pipe_states state;
unsigned refcount;
unsigned type;
- struct radeon_state rstate[16];
+ struct radeon_state rstate[R600_MAX_RSTATE];
struct r600_shader shader;
struct radeon_bo *bo;
+ unsigned nrstate;
};
struct r600_vertex_element
@@ -153,10 +156,10 @@ struct r600_context {
struct r600_context_state *stencil_ref;
struct r600_context_state *viewport;
struct r600_context_state *framebuffer;
- struct r600_context_state *ps_sampler[PIPE_MAX_ATTRIBS];
- struct r600_context_state *vs_sampler[PIPE_MAX_ATTRIBS];
- struct r600_context_state *ps_sampler_view[PIPE_MAX_ATTRIBS];
- struct r600_context_state *vs_sampler_view[PIPE_MAX_ATTRIBS];
+ struct radeon_state *ps_sampler[PIPE_MAX_ATTRIBS];
+ struct radeon_state *vs_sampler[PIPE_MAX_ATTRIBS];
+ struct radeon_state *ps_sampler_view[PIPE_MAX_ATTRIBS];
+ struct radeon_state *vs_sampler_view[PIPE_MAX_ATTRIBS];
struct r600_vertex_element *vertex_elements;
struct pipe_vertex_buffer vertex_buffer[PIPE_MAX_ATTRIBS];
struct pipe_index_buffer index_buffer;
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index 888507747b3..95611d17394 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -235,14 +235,23 @@ static void r600_bind_ps_sampler(struct pipe_context *ctx,
struct r600_context_state *rstate;
unsigned i;
- for (i = 0; i < rctx->ps_nsampler; i++) {
- rctx->ps_sampler[i] = r600_context_state_decref(rctx->ps_sampler[i]);
+ for (i = 0; i < count; i++) {
+ rstate = (struct r600_context_state *)states[i];
+ if (rstate) {
+ rstate->nrstate = 0;
+ }
}
for (i = 0; i < count; i++) {
rstate = (struct r600_context_state *)states[i];
- rctx->ps_sampler[i] = r600_context_state_incref(rstate);
if (rstate) {
- radeon_state_convert(&rstate->rstate[0], R600_STATE_SAMPLER, i, R600_SHADER_PS);
+ if (rstate->nrstate >= R600_MAX_RSTATE)
+ continue;
+ if (rstate->nrstate) {
+ memcpy(&rstate->rstate[rstate->nrstate], &rstate->rstate[0], sizeof(struct radeon_state));
+ }
+ radeon_state_convert(&rstate->rstate[rstate->nrstate], R600_STATE_SAMPLER, i, R600_SHADER_PS);
+ rctx->ps_sampler[i] = &rstate->rstate[rstate->nrstate];
+ rstate->nrstate++;
}
}
rctx->ps_nsampler = count;
@@ -255,14 +264,23 @@ static void r600_bind_vs_sampler(struct pipe_context *ctx,
struct r600_context_state *rstate;
unsigned i;
- for (i = 0; i < rctx->vs_nsampler; i++) {
- rctx->vs_sampler[i] = r600_context_state_decref(rctx->vs_sampler[i]);
+ for (i = 0; i < count; i++) {
+ rstate = (struct r600_context_state *)states[i];
+ if (rstate) {
+ rstate->nrstate = 0;
+ }
}
for (i = 0; i < count; i++) {
rstate = (struct r600_context_state *)states[i];
- rctx->vs_sampler[i] = r600_context_state_incref(rstate);
if (rstate) {
- radeon_state_convert(&rstate->rstate[0], R600_STATE_SAMPLER, i, R600_SHADER_VS);
+ if (rstate->nrstate >= R600_MAX_RSTATE)
+ continue;
+ if (rstate->nrstate) {
+ memcpy(&rstate->rstate[rstate->nrstate], &rstate->rstate[0], sizeof(struct radeon_state));
+ }
+ radeon_state_convert(&rstate->rstate[rstate->nrstate], R600_STATE_SAMPLER, i, R600_SHADER_VS);
+ rctx->vs_sampler[i] = &rstate->rstate[rstate->nrstate];
+ rstate->nrstate++;
}
}
rctx->vs_nsampler = count;
@@ -349,14 +367,23 @@ static void r600_set_ps_sampler_view(struct pipe_context *ctx,
struct r600_context_state *rstate;
unsigned i;
- for (i = 0; i < rctx->ps_nsampler_view; i++) {
- rctx->ps_sampler_view[i] = r600_context_state_decref(rctx->ps_sampler_view[i]);
+ for (i = 0; i < count; i++) {
+ rstate = (struct r600_context_state *)views[i];
+ if (rstate) {
+ rstate->nrstate = 0;
+ }
}
for (i = 0; i < count; i++) {
rstate = (struct r600_context_state *)views[i];
- rctx->ps_sampler_view[i] = r600_context_state_incref(rstate);
if (rstate) {
- radeon_state_convert(&rstate->rstate[0], R600_STATE_RESOURCE, i, R600_SHADER_PS);
+ if (rstate->nrstate >= R600_MAX_RSTATE)
+ continue;
+ if (rstate->nrstate) {
+ memcpy(&rstate->rstate[rstate->nrstate], &rstate->rstate[0], sizeof(struct radeon_state));
+ }
+ radeon_state_convert(&rstate->rstate[rstate->nrstate], R600_STATE_RESOURCE, i, R600_SHADER_PS);
+ rctx->ps_sampler_view[i] = &rstate->rstate[rstate->nrstate];
+ rstate->nrstate++;
}
}
rctx->ps_nsampler_view = count;
@@ -370,14 +397,23 @@ static void r600_set_vs_sampler_view(struct pipe_context *ctx,
struct r600_context_state *rstate;
unsigned i;
- for (i = 0; i < rctx->vs_nsampler_view; i++) {
- rctx->vs_sampler_view[i] = r600_context_state_decref(rctx->vs_sampler_view[i]);
+ for (i = 0; i < count; i++) {
+ rstate = (struct r600_context_state *)views[i];
+ if (rstate) {
+ rstate->nrstate = 0;
+ }
}
for (i = 0; i < count; i++) {
rstate = (struct r600_context_state *)views[i];
- rctx->vs_sampler_view[i] = r600_context_state_incref(rstate);
if (rstate) {
- radeon_state_convert(&rstate->rstate[0], R600_STATE_RESOURCE, i, R600_SHADER_VS);
+ if (rstate->nrstate >= R600_MAX_RSTATE)
+ continue;
+ if (rstate->nrstate) {
+ memcpy(&rstate->rstate[rstate->nrstate], &rstate->rstate[0], sizeof(struct radeon_state));
+ }
+ radeon_state_convert(&rstate->rstate[rstate->nrstate], R600_STATE_RESOURCE, i, R600_SHADER_VS);
+ rctx->vs_sampler_view[i] = &rstate->rstate[rstate->nrstate];
+ rstate->nrstate++;
}
}
rctx->vs_nsampler_view = count;
@@ -1354,12 +1390,12 @@ int r600_context_hw_states(struct pipe_context *ctx)
}
for (i = 0; i < rctx->ps_nsampler; i++) {
if (rctx->ps_sampler[i]) {
- radeon_draw_bind(&rctx->draw, &rctx->ps_sampler[i]->rstate[0]);
+ radeon_draw_bind(&rctx->draw, rctx->ps_sampler[i]);
}
}
for (i = 0; i < rctx->ps_nsampler_view; i++) {
if (rctx->ps_sampler_view[i]) {
- radeon_draw_bind(&rctx->draw, &rctx->ps_sampler_view[i]->rstate[0]);
+ radeon_draw_bind(&rctx->draw, rctx->ps_sampler_view[i]);
}
}
return 0;