diff options
| author | Marek Olšák <[email protected]> | 2017-04-03 00:22:16 +0200 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2017-04-04 11:14:43 +0200 |
| commit | 0fb5a505fac7be0a1831b565019f0f04369e56bd (patch) | |
| tree | a2c875d2607ebf9b1cc7c0aeb9afa7aab1600645 /src/gallium/drivers | |
| parent | 1bcdf74cdddf713c7067b700a2c6b5c19823dbe7 (diff) | |
radeonsi: fix broken texture filtering on SI-CIK since GFX9 changes
Don't clear state[7] on SI-CIK, and only do the meta stuff on VI+.
Fixes: 5abf60076ce4 ("radeonsi/gfx9: image descriptor changes in mutable fields")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100531
Reviewed-by: Nicolai Hähnle <[email protected]>
Diffstat (limited to 'src/gallium/drivers')
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_descriptors.c | 32 |
1 files changed, 17 insertions, 15 deletions
diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c index 2b911585a69..8f5a16ba47a 100644 --- a/src/gallium/drivers/radeonsi/si_descriptors.c +++ b/src/gallium/drivers/radeonsi/si_descriptors.c @@ -404,26 +404,28 @@ void si_set_mutable_tex_desc_fields(struct si_screen *sscreen, va += base_level_info->offset; } - if (vi_dcc_enabled(tex, first_level)) { - meta_va = (!tex->dcc_separate_buffer ? tex->resource.gpu_address : 0) + - tex->dcc_offset; - - if (sscreen->b.chip_class <= VI) - meta_va += base_level_info->dcc_offset; - } else if (tex->tc_compatible_htile && !is_stencil) { - meta_va = tex->htile_buffer->gpu_address; - } - state[0] = va >> 8; state[1] &= C_008F14_BASE_ADDRESS_HI; state[1] |= S_008F14_BASE_ADDRESS_HI(va >> 40); - state[6] &= C_008F28_COMPRESSION_EN; - state[7] = 0; + if (sscreen->b.chip_class >= VI) { + state[6] &= C_008F28_COMPRESSION_EN; + state[7] = 0; - if (meta_va) { - state[6] |= S_008F28_COMPRESSION_EN(1); - state[7] = meta_va >> 8; + if (vi_dcc_enabled(tex, first_level)) { + meta_va = (!tex->dcc_separate_buffer ? tex->resource.gpu_address : 0) + + tex->dcc_offset; + + if (sscreen->b.chip_class <= VI) + meta_va += base_level_info->dcc_offset; + } else if (tex->tc_compatible_htile && !is_stencil) { + meta_va = tex->htile_buffer->gpu_address; + } + + if (meta_va) { + state[6] |= S_008F28_COMPRESSION_EN(1); + state[7] = meta_va >> 8; + } } if (sscreen->b.chip_class >= GFX9) { |