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authorMarek Olšák <[email protected]>2018-06-20 18:15:36 -0500
committerMarek Olšák <[email protected]>2018-06-21 14:42:14 -0400
commit9c21002f6ed0621fbd68f413eceb58a89ace7275 (patch)
tree0128b2a04c3545902a214c5f568d1cb862fdef32 /src/gallium/drivers
parent587e712eda95c31d88ea9d20e59ad0ae59afef4f (diff)
radeonsi: handle non-clearable DCC buffers as MSAA resolve dst
This is reproducible on Stoney, but other chips may be affected too. Cc 18.1 <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Diffstat (limited to 'src/gallium/drivers')
-rw-r--r--src/gallium/drivers/radeonsi/si_blit.c5
-rw-r--r--src/gallium/drivers/radeonsi/si_clear.c2
2 files changed, 6 insertions, 1 deletions
diff --git a/src/gallium/drivers/radeonsi/si_blit.c b/src/gallium/drivers/radeonsi/si_blit.c
index 194e181adfc..9024717791c 100644
--- a/src/gallium/drivers/radeonsi/si_blit.c
+++ b/src/gallium/drivers/radeonsi/si_blit.c
@@ -1161,6 +1161,11 @@ static bool do_hardware_msaa_resolve(struct pipe_context *ctx,
info->dst.resource->last_level != 0)
goto resolve_to_temp;
+ /* This can happen with mipmapping. */
+ if (sctx->chip_class == VI &&
+ !dst->surface.u.legacy.level[info->dst.level].dcc_fast_clear_size)
+ goto resolve_to_temp;
+
vi_dcc_clear_level(sctx, dst, info->dst.level,
0xFFFFFFFF);
dst->dirty_level_mask &= ~(1 << info->dst.level);
diff --git a/src/gallium/drivers/radeonsi/si_clear.c b/src/gallium/drivers/radeonsi/si_clear.c
index 72319b3eca2..53c255c5808 100644
--- a/src/gallium/drivers/radeonsi/si_clear.c
+++ b/src/gallium/drivers/radeonsi/si_clear.c
@@ -479,7 +479,7 @@ static void si_do_fast_color_clear(struct si_context *sctx,
if (sctx->screen->debug_flags & DBG(NO_DCC_CLEAR))
continue;
- /* This can only occur with MSAA. */
+ /* This can happen with mipmapping or MSAA. */
if (sctx->chip_class == VI &&
!tex->surface.u.legacy.level[level].dcc_fast_clear_size)
continue;