freedreno: switch to layout helper

The slices table and most of the other layout fields in the
freedreno_resource moves into fdl_layout.

v2: Changes by anholt to not have duplicate fields, which was introducing
    a surprising behavior change in resource layout (using the
    level_linear helper before the setup of the shadowed fields)

Reviewed-by: Eric Anholt <[email protected]>
Acked-by: Rob Clark <[email protected]>

27 files changed, 190 insertions, 199 deletions

diff --git a/src/gallium/drivers/freedreno/a2xx/fd2_gmem.c b/src/gallium/drivers/freedreno/a2xx/fd2_gmem.c
index 23188af9386..6ebcd0035c1 100644
--- a/src/gallium/drivers/freedreno/a2xx/fd2_gmem.c
+++ b/src/gallium/drivers/freedreno/a2xx/fd2_gmem.c
@@ -112,7 +112,7 @@ emit_gmem2mem_surf(struct fd_batch *batch, uint32_t base,
 	OUT_RING(ring, slice->pitch >> 5); /* RB_COPY_DEST_PITCH */
 	OUT_RING(ring,                          /* RB_COPY_DEST_INFO */
 			A2XX_RB_COPY_DEST_INFO_FORMAT(fd2_pipe2color(format)) |
-			COND(!rsc->tile_mode, A2XX_RB_COPY_DEST_INFO_LINEAR) |
+			COND(!rsc->layout.tile_mode, A2XX_RB_COPY_DEST_INFO_LINEAR) |
 			A2XX_RB_COPY_DEST_INFO_WRITE_RED |
 			A2XX_RB_COPY_DEST_INFO_WRITE_GREEN |
 			A2XX_RB_COPY_DEST_INFO_WRITE_BLUE |
@@ -451,7 +451,7 @@ fd2_emit_sysmem_prep(struct fd_batch *batch)
 	OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 	OUT_RING(ring, CP_REG(REG_A2XX_RB_COLOR_INFO));
 	OUT_RELOCW(ring, rsc->bo, offset,
-		COND(!rsc->tile_mode, A2XX_RB_COLOR_INFO_LINEAR) |
+		COND(!rsc->layout.tile_mode, A2XX_RB_COLOR_INFO_LINEAR) |
 		A2XX_RB_COLOR_INFO_SWAP(fmt2swap(psurf->format)) |
 		A2XX_RB_COLOR_INFO_FORMAT(fd2_pipe2color(psurf->format)), 0);
 
diff --git a/src/gallium/drivers/freedreno/a2xx/fd2_resource.c b/src/gallium/drivers/freedreno/a2xx/fd2_resource.c
index cccbccf5bd1..bccce004a71 100644
--- a/src/gallium/drivers/freedreno/a2xx/fd2_resource.c
+++ b/src/gallium/drivers/freedreno/a2xx/fd2_resource.c
@@ -67,7 +67,7 @@ fd2_setup_slices(struct fd_resource *rsc)
 		blocks = util_format_get_nblocks(format, width, height);
 
 		/* 4k aligned size */
-		slice->size0 = align(blocks * rsc->cpp, 4096);
+		slice->size0 = align(blocks * rsc->layout.cpp, 4096);
 
 		size += slice->size0 * depth * prsc->array_size;
 
diff --git a/src/gallium/drivers/freedreno/a2xx/fd2_texture.c b/src/gallium/drivers/freedreno/a2xx/fd2_texture.c
index a2bd72e9efe..7e25fc368d4 100644
--- a/src/gallium/drivers/freedreno/a2xx/fd2_texture.c
+++ b/src/gallium/drivers/freedreno/a2xx/fd2_texture.c
@@ -188,7 +188,7 @@ fd2_sampler_view_create(struct pipe_context *pctx, struct pipe_resource *prsc,
 		A2XX_SQ_TEX_0_SIGN_Z(fmt.sign) |
 		A2XX_SQ_TEX_0_SIGN_W(fmt.sign) |
 		A2XX_SQ_TEX_0_PITCH(slice0->pitch) |
-		COND(rsc->tile_mode, A2XX_SQ_TEX_0_TILED);
+		COND(rsc->layout.tile_mode, A2XX_SQ_TEX_0_TILED);
 	so->tex1 =
 		A2XX_SQ_TEX_1_FORMAT(fmt.format) |
 		A2XX_SQ_TEX_1_CLAMP_POLICY(SQ_TEX_CLAMP_POLICY_OGL);
diff --git a/src/gallium/drivers/freedreno/a3xx/fd3_emit.c b/src/gallium/drivers/freedreno/a3xx/fd3_emit.c
index 715b4374618..af147859942 100644
--- a/src/gallium/drivers/freedreno/a3xx/fd3_emit.c
+++ b/src/gallium/drivers/freedreno/a3xx/fd3_emit.c
@@ -314,7 +314,7 @@ fd3_emit_gmem_restore_tex(struct fd_ringbuffer *ring,
 
 		debug_assert(psurf[i]->u.tex.first_layer == psurf[i]->u.tex.last_layer);
 
-		OUT_RING(ring, A3XX_TEX_CONST_0_TILE_MODE(rsc->tile_mode) |
+		OUT_RING(ring, A3XX_TEX_CONST_0_TILE_MODE(rsc->layout.tile_mode) |
 				 A3XX_TEX_CONST_0_FMT(fd3_pipe2tex(format)) |
 				 A3XX_TEX_CONST_0_TYPE(A3XX_TEX_2D) |
 				 fd3_tex_swiz(format,  PIPE_SWIZZLE_X, PIPE_SWIZZLE_Y,
@@ -322,7 +322,7 @@ fd3_emit_gmem_restore_tex(struct fd_ringbuffer *ring,
 		OUT_RING(ring, A3XX_TEX_CONST_1_FETCHSIZE(TFETCH_DISABLE) |
 				 A3XX_TEX_CONST_1_WIDTH(psurf[i]->width) |
 				 A3XX_TEX_CONST_1_HEIGHT(psurf[i]->height));
-		OUT_RING(ring, A3XX_TEX_CONST_2_PITCH(slice->pitch * rsc->cpp) |
+		OUT_RING(ring, A3XX_TEX_CONST_2_PITCH(slice->pitch * rsc->layout.cpp) |
 				 A3XX_TEX_CONST_2_INDX(BASETABLE_SZ * i));
 		OUT_RING(ring, 0x00000000);
 	}
diff --git a/src/gallium/drivers/freedreno/a3xx/fd3_gmem.c b/src/gallium/drivers/freedreno/a3xx/fd3_gmem.c
index d30915bdc70..44691062707 100644
--- a/src/gallium/drivers/freedreno/a3xx/fd3_gmem.c
+++ b/src/gallium/drivers/freedreno/a3xx/fd3_gmem.c
@@ -91,17 +91,17 @@ emit_mrt(struct fd_ringbuffer *ring, unsigned nr_bufs,
 
 			offset = fd_resource_offset(rsc, psurf->u.tex.level,
 					psurf->u.tex.first_layer);
-			swap = rsc->tile_mode ? WZYX : fd3_pipe2swap(pformat);
+			swap = rsc->layout.tile_mode ? WZYX : fd3_pipe2swap(pformat);
 
 			if (bin_w) {
-				stride = bin_w * rsc->cpp;
+				stride = bin_w * rsc->layout.cpp;
 
 				if (bases) {
 					base = bases[i];
 				}
 			} else {
-				stride = slice->pitch * rsc->cpp;
-				tile_mode = rsc->tile_mode;
+				stride = slice->pitch * rsc->layout.cpp;
+				tile_mode = rsc->layout.tile_mode;
 			}
 		} else if (i < nr_bufs && bases) {
 			base = bases[i];
@@ -345,8 +345,8 @@ emit_gmem2mem_surf(struct fd_batch *batch,
 				 A3XX_RB_COPY_CONTROL_DEPTH32_RESOLVE));
 
 	OUT_RELOCW(ring, rsc->bo, offset, 0, -1);    /* RB_COPY_DEST_BASE */
-	OUT_RING(ring, A3XX_RB_COPY_DEST_PITCH_PITCH(slice->pitch * rsc->cpp));
-	OUT_RING(ring, A3XX_RB_COPY_DEST_INFO_TILE(rsc->tile_mode) |
+	OUT_RING(ring, A3XX_RB_COPY_DEST_PITCH_PITCH(slice->pitch * rsc->layout.cpp));
+	OUT_RING(ring, A3XX_RB_COPY_DEST_INFO_TILE(rsc->layout.tile_mode) |
 			A3XX_RB_COPY_DEST_INFO_FORMAT(fd3_pipe2color(format)) |
 			A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(0xf) |
 			A3XX_RB_COPY_DEST_INFO_ENDIAN(ENDIAN_NONE) |
@@ -1007,11 +1007,11 @@ fd3_emit_tile_renderprep(struct fd_batch *batch, struct fd_tile *tile)
 	OUT_RING(ring, reg);
 	if (pfb->zsbuf) {
 		struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
-		OUT_RING(ring, A3XX_RB_DEPTH_PITCH(rsc->cpp * gmem->bin_w));
+		OUT_RING(ring, A3XX_RB_DEPTH_PITCH(rsc->layout.cpp * gmem->bin_w));
 		if (rsc->stencil) {
 			OUT_PKT0(ring, REG_A3XX_RB_STENCIL_INFO, 2);
 			OUT_RING(ring, A3XX_RB_STENCIL_INFO_STENCIL_BASE(gmem->zsbuf_base[1]));
-			OUT_RING(ring, A3XX_RB_STENCIL_PITCH(rsc->stencil->cpp * gmem->bin_w));
+			OUT_RING(ring, A3XX_RB_STENCIL_PITCH(rsc->stencil->layout.cpp * gmem->bin_w));
 		}
 	} else {
 		OUT_RING(ring, 0x00000000);
diff --git a/src/gallium/drivers/freedreno/a3xx/fd3_resource.c b/src/gallium/drivers/freedreno/a3xx/fd3_resource.c
index b29c846e3b0..6089ca01e40 100644
--- a/src/gallium/drivers/freedreno/a3xx/fd3_resource.c
+++ b/src/gallium/drivers/freedreno/a3xx/fd3_resource.c
@@ -40,7 +40,7 @@ setup_slices(struct fd_resource *rsc, uint32_t alignment, enum pipe_format forma
 		struct fdl_slice *slice = fd_resource_slice(rsc, level);
 		uint32_t blocks;
 
-		if (rsc->tile_mode) {
+		if (rsc->layout.tile_mode) {
 			if (prsc->target != PIPE_TEXTURE_CUBE) {
 				if (level == 0) {
 					width = util_next_power_of_two(width);
@@ -74,9 +74,9 @@ setup_slices(struct fd_resource *rsc, uint32_t alignment, enum pipe_format forma
 		if (prsc->target == PIPE_TEXTURE_3D && (
 					level == 1 ||
 					(level > 1 && fd_resource_slice(rsc, level - 1)->size0 > 0xf000)))
-			slice->size0 = align(blocks * rsc->cpp, alignment);
+			slice->size0 = align(blocks * rsc->layout.cpp, alignment);
 		else if (level == 0 || alignment == 1)
-			slice->size0 = align(blocks * rsc->cpp, alignment);
+			slice->size0 = align(blocks * rsc->layout.cpp, alignment);
 		else
 			slice->size0 = fd_resource_slice(rsc, level - 1)->size0;
 
diff --git a/src/gallium/drivers/freedreno/a3xx/fd3_texture.c b/src/gallium/drivers/freedreno/a3xx/fd3_texture.c
index e65adba3c59..50664f1c280 100644
--- a/src/gallium/drivers/freedreno/a3xx/fd3_texture.c
+++ b/src/gallium/drivers/freedreno/a3xx/fd3_texture.c
@@ -233,7 +233,7 @@ fd3_sampler_view_create(struct pipe_context *pctx, struct pipe_resource *prsc,
 	so->base.context = pctx;
 
 	so->texconst0 =
-	 		A3XX_TEX_CONST_0_TILE_MODE(rsc->tile_mode) |
+			A3XX_TEX_CONST_0_TILE_MODE(rsc->layout.tile_mode) |
 			A3XX_TEX_CONST_0_TYPE(tex_type(prsc->target)) |
 			A3XX_TEX_CONST_0_FMT(fd3_pipe2tex(cso->format)) |
 			fd3_tex_swiz(cso->format, cso->swizzle_r, cso->swizzle_g,
@@ -265,7 +265,7 @@ fd3_sampler_view_create(struct pipe_context *pctx, struct pipe_resource *prsc,
 	/* when emitted, A3XX_TEX_CONST_2_INDX() must be OR'd in: */
 	struct fdl_slice *slice = fd_resource_slice(rsc, lvl);
 	so->texconst2 =
-			A3XX_TEX_CONST_2_PITCH(fd3_pipe2nblocksx(cso->format, slice->pitch) * rsc->cpp);
+			A3XX_TEX_CONST_2_PITCH(fd3_pipe2nblocksx(cso->format, slice->pitch) * rsc->layout.cpp);
 	switch (prsc->target) {
 	case PIPE_TEXTURE_1D_ARRAY:
 	case PIPE_TEXTURE_2D_ARRAY:
diff --git a/src/gallium/drivers/freedreno/a4xx/fd4_emit.c b/src/gallium/drivers/freedreno/a4xx/fd4_emit.c
index 0422ceaee69..7a188c68afc 100644
--- a/src/gallium/drivers/freedreno/a4xx/fd4_emit.c
+++ b/src/gallium/drivers/freedreno/a4xx/fd4_emit.c
@@ -323,7 +323,7 @@ fd4_emit_gmem_restore_tex(struct fd_ringbuffer *ring, unsigned nr_bufs,
 							PIPE_SWIZZLE_Z, PIPE_SWIZZLE_W));
 			OUT_RING(ring, A4XX_TEX_CONST_1_WIDTH(bufs[i]->width) |
 					A4XX_TEX_CONST_1_HEIGHT(bufs[i]->height));
-			OUT_RING(ring, A4XX_TEX_CONST_2_PITCH(slice->pitch * rsc->cpp) |
+			OUT_RING(ring, A4XX_TEX_CONST_2_PITCH(slice->pitch * rsc->layout.cpp) |
 					A4XX_TEX_CONST_2_FETCHSIZE(fd4_pipe2fetchsize(format)));
 			OUT_RING(ring, 0x00000000);
 			OUT_RELOC(ring, rsc->bo, offset, 0, 0);
diff --git a/src/gallium/drivers/freedreno/a4xx/fd4_gmem.c b/src/gallium/drivers/freedreno/a4xx/fd4_gmem.c
index 510ebb89044..9649edd37d1 100644
--- a/src/gallium/drivers/freedreno/a4xx/fd4_gmem.c
+++ b/src/gallium/drivers/freedreno/a4xx/fd4_gmem.c
@@ -97,13 +97,13 @@ emit_mrt(struct fd_ringbuffer *ring, unsigned nr_bufs,
 					psurf->u.tex.first_layer);
 
 			if (bin_w) {
-				stride = bin_w * rsc->cpp;
+				stride = bin_w * rsc->layout.cpp;
 
 				if (bases) {
 					base = bases[i];
 				}
 			} else {
-				stride = slice->pitch * rsc->cpp;
+				stride = slice->pitch * rsc->layout.cpp;
 			}
 		} else if ((i < nr_bufs) && bases) {
 			base = bases[i];
@@ -175,7 +175,7 @@ emit_gmem2mem_surf(struct fd_batch *batch, bool stencil,
 			A4XX_RB_COPY_CONTROL_MODE(RB_COPY_RESOLVE) |
 			A4XX_RB_COPY_CONTROL_GMEM_BASE(base));
 	OUT_RELOCW(ring, rsc->bo, offset, 0, 0);   /* RB_COPY_DEST_BASE */
-	OUT_RING(ring, A4XX_RB_COPY_DEST_PITCH_PITCH(slice->pitch * rsc->cpp));
+	OUT_RING(ring, A4XX_RB_COPY_DEST_PITCH_PITCH(slice->pitch * rsc->layout.cpp));
 	OUT_RING(ring, A4XX_RB_COPY_DEST_INFO_TILE(TILE4_LINEAR) |
 			A4XX_RB_COPY_DEST_INFO_FORMAT(fd4_pipe2color(pformat)) |
 			A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(0xf) |
@@ -715,7 +715,7 @@ fd4_emit_tile_prep(struct fd_batch *batch, struct fd_tile *tile)
 
 	if (pfb->zsbuf) {
 		struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
-		uint32_t cpp = rsc->cpp;
+		uint32_t cpp = rsc->layout.cpp;
 
 		OUT_PKT0(ring, REG_A4XX_RB_DEPTH_INFO, 3);
 		OUT_RING(ring, A4XX_RB_DEPTH_INFO_DEPTH_BASE(gmem->zsbuf_base[0]) |
@@ -727,7 +727,7 @@ fd4_emit_tile_prep(struct fd_batch *batch, struct fd_tile *tile)
 		if (rsc->stencil) {
 			OUT_RING(ring, A4XX_RB_STENCIL_INFO_SEPARATE_STENCIL |
 					A4XX_RB_STENCIL_INFO_STENCIL_BASE(gmem->zsbuf_base[1]));
-			OUT_RING(ring, A4XX_RB_STENCIL_PITCH(rsc->stencil->cpp * gmem->bin_w));
+			OUT_RING(ring, A4XX_RB_STENCIL_PITCH(rsc->stencil->layout.cpp * gmem->bin_w));
 		} else {
 			OUT_RING(ring, 0x00000000);
 			OUT_RING(ring, 0x00000000);
diff --git a/src/gallium/drivers/freedreno/a4xx/fd4_texture.c b/src/gallium/drivers/freedreno/a4xx/fd4_texture.c
index 69f4d45a181..de4e2d27144 100644
--- a/src/gallium/drivers/freedreno/a4xx/fd4_texture.c
+++ b/src/gallium/drivers/freedreno/a4xx/fd4_texture.c
@@ -261,7 +261,7 @@ fd4_sampler_view_create(struct pipe_context *pctx, struct pipe_resource *prsc,
 			A4XX_TEX_CONST_1_HEIGHT(1);
 		so->texconst2 =
 			A4XX_TEX_CONST_2_FETCHSIZE(fd4_pipe2fetchsize(format)) |
-			A4XX_TEX_CONST_2_PITCH(elements * rsc->cpp);
+			A4XX_TEX_CONST_2_PITCH(elements * rsc->layout.cpp);
 		so->offset = cso->u.buf.offset;
 	} else {
 		unsigned miplevels;
@@ -278,7 +278,7 @@ fd4_sampler_view_create(struct pipe_context *pctx, struct pipe_resource *prsc,
 		so->texconst2 =
 			A4XX_TEX_CONST_2_FETCHSIZE(fd4_pipe2fetchsize(format)) |
 			A4XX_TEX_CONST_2_PITCH(
-				util_format_get_nblocksx(format, slice->pitch) * rsc->cpp);
+				util_format_get_nblocksx(format, slice->pitch) * rsc->layout.cpp);
 		so->offset = fd_resource_offset(rsc, lvl, cso->u.tex.first_layer);
 	}
 
@@ -299,13 +299,13 @@ fd4_sampler_view_create(struct pipe_context *pctx, struct pipe_resource *prsc,
 	case PIPE_TEXTURE_2D_ARRAY:
 		so->texconst3 =
 			A4XX_TEX_CONST_3_DEPTH(layers) |
-			A4XX_TEX_CONST_3_LAYERSZ(rsc->layer_size);
+			A4XX_TEX_CONST_3_LAYERSZ(rsc->layout.layer_size);
 		break;
 	case PIPE_TEXTURE_CUBE:
 	case PIPE_TEXTURE_CUBE_ARRAY:
 		so->texconst3 =
 			A4XX_TEX_CONST_3_DEPTH(layers / 6) |
-			A4XX_TEX_CONST_3_LAYERSZ(rsc->layer_size);
+			A4XX_TEX_CONST_3_LAYERSZ(rsc->layout.layer_size);
 		break;
 	case PIPE_TEXTURE_3D:
 		so->texconst3 =
diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_blitter.c b/src/gallium/drivers/freedreno/a5xx/fd5_blitter.c
index bb02079b1d4..b5765263ce5 100644
--- a/src/gallium/drivers/freedreno/a5xx/fd5_blitter.c
+++ b/src/gallium/drivers/freedreno/a5xx/fd5_blitter.c
@@ -98,8 +98,8 @@ can_do_blit(const struct pipe_blit_info *info)
 	 * untiling by setting both src and dst COLOR_SWAP=WZYX, but that
 	 * means the formats must match:
 	 */
-	if ((fd_resource(info->dst.resource)->tile_mode ||
-				fd_resource(info->src.resource)->tile_mode) &&
+	if ((fd_resource(info->dst.resource)->layout.tile_mode ||
+				fd_resource(info->src.resource)->layout.tile_mode) &&
 			info->dst.format != info->src.format)
 		return false;
 
@@ -215,8 +215,8 @@ emit_blit_buffer(struct fd_ringbuffer *ring, const struct pipe_blit_info *info)
 	src = fd_resource(info->src.resource);
 	dst = fd_resource(info->dst.resource);
 
-	debug_assert(src->cpp == 1);
-	debug_assert(dst->cpp == 1);
+	debug_assert(src->layout.cpp == 1);
+	debug_assert(dst->layout.cpp == 1);
 	debug_assert(info->src.resource->format == info->dst.resource->format);
 	debug_assert((sbox->y == 0) && (sbox->height == 1));
 	debug_assert((dbox->y == 0) && (dbox->height == 1));
@@ -348,8 +348,8 @@ emit_blit(struct fd_ringbuffer *ring, const struct pipe_blit_info *info)
 	sswap = fd5_pipe2swap(info->src.format);
 	dswap = fd5_pipe2swap(info->dst.format);
 
-	spitch = sslice->pitch * src->cpp;
-	dpitch = dslice->pitch * dst->cpp;
+	spitch = sslice->pitch * src->layout.cpp;
+	dpitch = dslice->pitch * dst->layout.cpp;
 
 	/* if dtile, then dswap ignored by hw, and likewise if stile then sswap
 	 * ignored by hw.. but in this case we have already rejected the blit
@@ -374,12 +374,12 @@ emit_blit(struct fd_ringbuffer *ring, const struct pipe_blit_info *info)
 	if (info->src.resource->target == PIPE_TEXTURE_3D)
 		ssize = sslice->size0;
 	else
-		ssize = src->layer_size;
+		ssize = src->layout.layer_size;
 
 	if (info->dst.resource->target == PIPE_TEXTURE_3D)
 		dsize = dslice->size0;
 	else
-		dsize = dst->layer_size;
+		dsize = dst->layout.layer_size;
 
 	for (unsigned i = 0; i < info->dst.box.depth; i++) {
 		unsigned soff = fd_resource_offset(src, info->src.level, sbox->z + i);
@@ -466,8 +466,8 @@ fd5_blitter_blit(struct fd_context *ctx, const struct pipe_blit_info *info)
 
 	if ((info->src.resource->target == PIPE_BUFFER) &&
 			(info->dst.resource->target == PIPE_BUFFER)) {
-		assert(fd_resource(info->src.resource)->tile_mode == TILE5_LINEAR);
-		assert(fd_resource(info->dst.resource)->tile_mode == TILE5_LINEAR);
+		assert(fd_resource(info->src.resource)->layout.tile_mode == TILE5_LINEAR);
+		assert(fd_resource(info->dst.resource)->layout.tile_mode == TILE5_LINEAR);
 		emit_blit_buffer(batch->draw, info);
 	} else {
 		/* I don't *think* we need to handle blits between buffer <-> !buffer */
diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_emit.c b/src/gallium/drivers/freedreno/a5xx/fd5_emit.c
index 4de5d0aa62d..486657d92f4 100644
--- a/src/gallium/drivers/freedreno/a5xx/fd5_emit.c
+++ b/src/gallium/drivers/freedreno/a5xx/fd5_emit.c
@@ -365,7 +365,7 @@ emit_textures(struct fd_context *ctx, struct fd_ringbuffer *ring,
 			enum a5xx_tile_mode tile_mode = TILE5_LINEAR;
 
 			if (view->base.texture)
-				tile_mode = fd_resource(view->base.texture)->tile_mode;
+				tile_mode = fd_resource(view->base.texture)->layout.tile_mode;
 
 			OUT_RING(ring, view->texconst0 |
 					A5XX_TEX_CONST_0_TILE_MODE(tile_mode));
diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_gmem.c b/src/gallium/drivers/freedreno/a5xx/fd5_gmem.c
index 5b8bfb650c7..3380f8f6381 100644
--- a/src/gallium/drivers/freedreno/a5xx/fd5_gmem.c
+++ b/src/gallium/drivers/freedreno/a5xx/fd5_gmem.c
@@ -89,7 +89,7 @@ emit_mrt(struct fd_ringbuffer *ring, unsigned nr_bufs,
 				size = stride * gmem->bin_h;
 				base = gmem->cbuf_base[i];
 			} else {
-				stride = slice->pitch * rsc->cpp;
+				stride = slice->pitch * rsc->layout.cpp;
 				size = slice->size0;
 
 				tile_mode = fd_resource_tile_mode(psurf->texture, psurf->u.tex.level);
@@ -136,7 +136,7 @@ emit_zs(struct fd_ringbuffer *ring, struct pipe_surface *zsbuf,
 	if (zsbuf) {
 		struct fd_resource *rsc = fd_resource(zsbuf->texture);
 		enum a5xx_depth_format fmt = fd5_pipe2depth(zsbuf->format);
-		uint32_t cpp = rsc->cpp;
+		uint32_t cpp = rsc->layout.cpp;
 		uint32_t stride = 0;
 		uint32_t size = 0;
 
@@ -145,7 +145,7 @@ emit_zs(struct fd_ringbuffer *ring, struct pipe_surface *zsbuf,
 			size = stride * gmem->bin_h;
 		} else {
 			struct fdl_slice *slice = fd_resource_slice(rsc, 0);
-			stride = slice->pitch * rsc->cpp;
+			stride = slice->pitch * rsc->layout.cpp;
 			size = slice->size0;
 		}
 
@@ -192,7 +192,7 @@ emit_zs(struct fd_ringbuffer *ring, struct pipe_surface *zsbuf,
 				size = stride * gmem->bin_h;
 			} else {
 				struct fdl_slice *slice = fd_resource_slice(rsc->stencil, 0);
-				stride = slice->pitch * rsc->cpp;
+				stride = slice->pitch * rsc->layout.cpp;
 				size = slice->size0;
 			}
 
@@ -490,16 +490,16 @@ emit_mem2gmem_surf(struct fd_batch *batch, uint32_t base,
 
 		OUT_PKT4(ring, REG_A5XX_RB_MRT_BUF_INFO(0), 5);
 		OUT_RING(ring, A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT(format) |
-				A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(rsc->tile_mode) |
+				A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(rsc->layout.tile_mode) |
 				A5XX_RB_MRT_BUF_INFO_COLOR_SWAP(WZYX));
-		OUT_RING(ring, A5XX_RB_MRT_PITCH(slice->pitch * rsc->cpp));
+		OUT_RING(ring, A5XX_RB_MRT_PITCH(slice->pitch * rsc->layout.cpp));
 		OUT_RING(ring, A5XX_RB_MRT_ARRAY_PITCH(slice->size0));
 		OUT_RELOC(ring, rsc->bo, 0, 0, 0);  /* BASE_LO/HI */
 
 		buf = BLIT_MRT0;
 	}
 
-	stride = gmem->bin_w * rsc->cpp;
+	stride = gmem->bin_w * rsc->layout.cpp;
 	size = stride * gmem->bin_h;
 
 	OUT_PKT4(ring, REG_A5XX_RB_BLIT_FLAG_DST_LO, 4);
@@ -637,7 +637,7 @@ emit_gmem2mem_surf(struct fd_batch *batch, uint32_t base,
 	OUT_RING(ring, 0x00000004 |   /* XXX RB_RESOLVE_CNTL_3 */
 			COND(tiled, A5XX_RB_RESOLVE_CNTL_3_TILED));
 	OUT_RELOCW(ring, rsc->bo, offset, 0, 0);     /* RB_BLIT_DST_LO/HI */
-	OUT_RING(ring, A5XX_RB_BLIT_DST_PITCH(slice->pitch * rsc->cpp));
+	OUT_RING(ring, A5XX_RB_BLIT_DST_PITCH(slice->pitch * rsc->layout.cpp));
 	OUT_RING(ring, A5XX_RB_BLIT_DST_ARRAY_PITCH(slice->size0));
 
 	OUT_PKT4(ring, REG_A5XX_RB_BLIT_CNTL, 1);
diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_image.c b/src/gallium/drivers/freedreno/a5xx/fd5_image.c
index 4e1f77a63ad..e46a21c4523 100644
--- a/src/gallium/drivers/freedreno/a5xx/fd5_image.c
+++ b/src/gallium/drivers/freedreno/a5xx/fd5_image.c
@@ -75,7 +75,7 @@ static void translate_image(struct fd5_image *img, struct pipe_image_view *pimg)
 	img->fetchsize = fd5_pipe2fetchsize(format);
 	img->type      = fd5_tex_type(prsc->target);
 	img->srgb      = util_format_is_srgb(format);
-	img->cpp       = rsc->cpp;
+	img->cpp       = rsc->layout.cpp;
 	img->bo        = rsc->bo;
 
 	if (prsc->target == PIPE_BUFFER) {
@@ -86,7 +86,7 @@ static void translate_image(struct fd5_image *img, struct pipe_image_view *pimg)
 		lvl = pimg->u.tex.level;
 		slice = fd_resource_slice(rsc, lvl);
 		img->offset = fd_resource_offset(rsc, lvl, pimg->u.tex.first_layer);
-		img->pitch  = slice->pitch * rsc->cpp;
+		img->pitch  = slice->pitch * rsc->layout.cpp;
 	}
 
 	img->width     = u_minify(prsc->width0, lvl);
@@ -98,17 +98,17 @@ static void translate_image(struct fd5_image *img, struct pipe_image_view *pimg)
 	case PIPE_TEXTURE_RECT:
 	case PIPE_TEXTURE_1D:
 	case PIPE_TEXTURE_2D:
-		img->array_pitch = rsc->layer_size;
+		img->array_pitch = rsc->layout.layer_size;
 		img->depth = 1;
 		break;
 	case PIPE_TEXTURE_1D_ARRAY:
 	case PIPE_TEXTURE_2D_ARRAY:
-		img->array_pitch = rsc->layer_size;
+		img->array_pitch = rsc->layout.layer_size;
 		img->depth = layers;
 		break;
 	case PIPE_TEXTURE_CUBE:
 	case PIPE_TEXTURE_CUBE_ARRAY:
-		img->array_pitch = rsc->layer_size;
+		img->array_pitch = rsc->layout.layer_size;
 		img->depth = layers;
 		break;
 	case PIPE_TEXTURE_3D:
diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_resource.c b/src/gallium/drivers/freedreno/a5xx/fd5_resource.c
index 00174b9afe1..7e1497630b0 100644
--- a/src/gallium/drivers/freedreno/a5xx/fd5_resource.c
+++ b/src/gallium/drivers/freedreno/a5xx/fd5_resource.c
@@ -58,9 +58,9 @@ setup_slices(struct fd_resource *rsc, uint32_t alignment, enum pipe_format forma
 	/* in layer_first layout, the level (slice) contains just one
 	 * layer (since in fact the layer contains the slices)
 	 */
-	uint32_t layers_in_level = rsc->layer_first ? 1 : prsc->array_size;
+	uint32_t layers_in_level = rsc->layout.layer_first ? 1 : prsc->array_size;
 
-	heightalign = tile_alignment[rsc->cpp].heightalign;
+	heightalign = tile_alignment[rsc->layout.cpp].heightalign;
 
 	for (level = 0; level <= prsc->last_level; level++) {
 		struct fdl_slice *slice = fd_resource_slice(rsc, level);
@@ -68,7 +68,7 @@ setup_slices(struct fd_resource *rsc, uint32_t alignment, enum pipe_format forma
 		uint32_t blocks;
 
 		if (fd_resource_tile_mode(prsc, level)) {
-			pitchalign = tile_alignment[rsc->cpp].pitchalign;
+			pitchalign = tile_alignment[rsc->layout.cpp].pitchalign;
 			aligned_height = align(aligned_height, heightalign);
 		} else {
 			pitchalign = 64;
@@ -102,17 +102,17 @@ setup_slices(struct fd_resource *rsc, uint32_t alignment, enum pipe_format forma
 		if (prsc->target == PIPE_TEXTURE_3D && (
 					level == 1 ||
 					(level > 1 && fd_resource_slice(rsc, level - 1)->size0 > 0xf000)))
-			slice->size0 = align(blocks * rsc->cpp, alignment);
-		else if (level == 0 || rsc->layer_first || alignment == 1)
-			slice->size0 = align(blocks * rsc->cpp, alignment);
+			slice->size0 = align(blocks * rsc->layout.cpp, alignment);
+		else if (level == 0 || rsc->layout.layer_first || alignment == 1)
+			slice->size0 = align(blocks * rsc->layout.cpp, alignment);
 		else
 			slice->size0 = fd_resource_slice(rsc, level - 1)->size0;
 
 #if 0
 		debug_printf("%s: %ux%ux%u@%u: %2u: stride=%4u, size=%7u, aligned_height=%3u\n",
 				util_format_name(prsc->format),
-				prsc->width0, prsc->height0, prsc->depth0, rsc->cpp,
-				level, slice->pitch * rsc->cpp,
+				prsc->width0, prsc->height0, prsc->depth0, rsc->layout.cpp,
+				level, slice->pitch * rsc->layout.cpp,
 				slice->size0 * depth * layers_in_level,
 				aligned_height);
 #endif
@@ -134,11 +134,11 @@ fd5_setup_slices(struct fd_resource *rsc)
 
 	switch (rsc->base.target) {
 	case PIPE_TEXTURE_3D:
-		rsc->layer_first = false;
+		rsc->layout.layer_first = false;
 		alignment = 4096;
 		break;
 	default:
-		rsc->layer_first = true;
+		rsc->layout.layer_first = true;
 		alignment = 1;
 		break;
 	}
diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_texture.c b/src/gallium/drivers/freedreno/a5xx/fd5_texture.c
index 0a3f2ec68af..5da1a3022e9 100644
--- a/src/gallium/drivers/freedreno/a5xx/fd5_texture.c
+++ b/src/gallium/drivers/freedreno/a5xx/fd5_texture.c
@@ -250,7 +250,7 @@ fd5_sampler_view_create(struct pipe_context *pctx, struct pipe_resource *prsc,
 			A5XX_TEX_CONST_1_HEIGHT(1);
 		so->texconst2 =
 			A5XX_TEX_CONST_2_FETCHSIZE(fd5_pipe2fetchsize(format)) |
-			A5XX_TEX_CONST_2_PITCH(elements * rsc->cpp);
+			A5XX_TEX_CONST_2_PITCH(elements * rsc->layout.cpp);
 		so->offset = cso->u.buf.offset;
 	} else {
 		unsigned miplevels;
@@ -267,7 +267,7 @@ fd5_sampler_view_create(struct pipe_context *pctx, struct pipe_resource *prsc,
 		so->texconst2 =
 			A5XX_TEX_CONST_2_FETCHSIZE(fd5_pipe2fetchsize(format)) |
 			A5XX_TEX_CONST_2_PITCH(
-				util_format_get_nblocksx(format, slice->pitch) * rsc->cpp);
+				util_format_get_nblocksx(format, slice->pitch) * rsc->layout.cpp);
 		so->offset = fd_resource_offset(rsc, lvl, cso->u.tex.first_layer);
 	}
 
@@ -278,21 +278,21 @@ fd5_sampler_view_create(struct pipe_context *pctx, struct pipe_resource *prsc,
 	case PIPE_TEXTURE_1D:
 	case PIPE_TEXTURE_2D:
 		so->texconst3 =
-			A5XX_TEX_CONST_3_ARRAY_PITCH(rsc->layer_size);
+			A5XX_TEX_CONST_3_ARRAY_PITCH(rsc->layout.layer_size);
 		so->texconst5 =
 			A5XX_TEX_CONST_5_DEPTH(1);
 		break;
 	case PIPE_TEXTURE_1D_ARRAY:
 	case PIPE_TEXTURE_2D_ARRAY:
 		so->texconst3 =
-			A5XX_TEX_CONST_3_ARRAY_PITCH(rsc->layer_size);
+			A5XX_TEX_CONST_3_ARRAY_PITCH(rsc->layout.layer_size);
 		so->texconst5 =
 			A5XX_TEX_CONST_5_DEPTH(layers);
 		break;
 	case PIPE_TEXTURE_CUBE:
 	case PIPE_TEXTURE_CUBE_ARRAY:
 		so->texconst3 =
-			A5XX_TEX_CONST_3_ARRAY_PITCH(rsc->layer_size);
+			A5XX_TEX_CONST_3_ARRAY_PITCH(rsc->layout.layer_size);
 		so->texconst5 =
 			A5XX_TEX_CONST_5_DEPTH(layers / 6);
 		break;
diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_blitter.c b/src/gallium/drivers/freedreno/a6xx/fd6_blitter.c
index 9d601d07c95..6dd482ca2f3 100644
--- a/src/gallium/drivers/freedreno/a6xx/fd6_blitter.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_blitter.c
@@ -217,8 +217,8 @@ emit_blit_buffer(struct fd_context *ctx, struct fd_ringbuffer *ring,
 	src = fd_resource(info->src.resource);
 	dst = fd_resource(info->dst.resource);
 
-	debug_assert(src->cpp == 1);
-	debug_assert(dst->cpp == 1);
+	debug_assert(src->layout.cpp == 1);
+	debug_assert(dst->layout.cpp == 1);
 	debug_assert(info->src.resource->format == info->dst.resource->format);
 	debug_assert((sbox->y == 0) && (sbox->height == 1));
 	debug_assert((dbox->y == 0) && (dbox->height == 1));
@@ -395,8 +395,8 @@ emit_blit_or_clear_texture(struct fd_context *ctx, struct fd_ringbuffer *ring,
 		nelements = (dst->base.nr_samples ? dst->base.nr_samples : 1);
 	}
 
-	spitch = DIV_ROUND_UP(sslice->pitch, blockwidth) * src->cpp;
-	dpitch = DIV_ROUND_UP(dslice->pitch, blockwidth) * dst->cpp;
+	spitch = DIV_ROUND_UP(sslice->pitch, blockwidth) * src->layout.cpp;
+	dpitch = DIV_ROUND_UP(dslice->pitch, blockwidth) * dst->layout.cpp;
 
 	sx1 = sbox->x / blockwidth * nelements;
 	sy1 = sbox->y / blockheight;
@@ -537,8 +537,8 @@ emit_blit_or_clear_texture(struct fd_context *ctx, struct fd_ringbuffer *ring,
 		if (subwc_enabled) {
 			OUT_PKT4(ring, REG_A6XX_SP_PS_2D_SRC_FLAGS_LO, 6);
 			OUT_RELOC(ring, src->bo, subwcoff, 0, 0);
-			OUT_RING(ring, A6XX_SP_PS_2D_SRC_FLAGS_PITCH_PITCH(src->ubwc_pitch) |
-					 A6XX_SP_PS_2D_SRC_FLAGS_PITCH_ARRAY_PITCH(src->ubwc_size));
+			OUT_RING(ring, A6XX_SP_PS_2D_SRC_FLAGS_PITCH_PITCH(src->layout.ubwc_pitch) |
+					 A6XX_SP_PS_2D_SRC_FLAGS_PITCH_ARRAY_PITCH(src->layout.ubwc_size));
 			OUT_RING(ring, 0x00000000);
 			OUT_RING(ring, 0x00000000);
 			OUT_RING(ring, 0x00000000);
@@ -563,8 +563,8 @@ emit_blit_or_clear_texture(struct fd_context *ctx, struct fd_ringbuffer *ring,
 		if (dubwc_enabled) {
 			OUT_PKT4(ring, REG_A6XX_RB_2D_DST_FLAGS_LO, 6);
 			OUT_RELOCW(ring, dst->bo, dubwcoff, 0, 0);
-			OUT_RING(ring, A6XX_RB_2D_DST_FLAGS_PITCH_PITCH(dst->ubwc_pitch) |
-					 A6XX_RB_2D_DST_FLAGS_PITCH_ARRAY_PITCH(dst->ubwc_size));
+			OUT_RING(ring, A6XX_RB_2D_DST_FLAGS_PITCH_PITCH(dst->layout.ubwc_pitch) |
+					 A6XX_RB_2D_DST_FLAGS_PITCH_ARRAY_PITCH(dst->layout.ubwc_size));
 			OUT_RING(ring, 0x00000000);
 			OUT_RING(ring, 0x00000000);
 			OUT_RING(ring, 0x00000000);
@@ -767,8 +767,8 @@ handle_rgba_blit(struct fd_context *ctx, const struct pipe_blit_info *info)
 
 	if ((info->src.resource->target == PIPE_BUFFER) &&
 			(info->dst.resource->target == PIPE_BUFFER)) {
-		assert(fd_resource(info->src.resource)->tile_mode == TILE6_LINEAR);
-		assert(fd_resource(info->dst.resource)->tile_mode == TILE6_LINEAR);
+		assert(fd_resource(info->src.resource)->layout.tile_mode == TILE6_LINEAR);
+		assert(fd_resource(info->dst.resource)->layout.tile_mode == TILE6_LINEAR);
 		emit_blit_buffer(ctx, batch->draw, info);
 	} else {
 		/* I don't *think* we need to handle blits between buffer <-> !buffer */
diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_emit.c b/src/gallium/drivers/freedreno/a6xx/fd6_emit.c
index d77ed112fca..f5612b6a32d 100644
--- a/src/gallium/drivers/freedreno/a6xx/fd6_emit.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_emit.c
@@ -344,7 +344,7 @@ fd6_emit_fb_tex(struct fd_ringbuffer *state, struct fd_context *ctx)
 	OUT_RINGP(state, A6XX_TEX_CONST_2_TYPE(A6XX_TEX_2D) |
 			A6XX_TEX_CONST_2_FETCHSIZE(TFETCH6_2_BYTE),
 			&ctx->batch->fb_read_patches);
-	OUT_RING(state, A6XX_TEX_CONST_3_ARRAY_PITCH(rsc->layer_size));
+	OUT_RING(state, A6XX_TEX_CONST_3_ARRAY_PITCH(rsc->layout.layer_size));
 
 	OUT_RING(state, A6XX_TEX_CONST_4_BASE_LO(ctx->screen->gmem_base));
 	OUT_RING(state, A6XX_TEX_CONST_5_BASE_HI(ctx->screen->gmem_base >> 32) |
diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_format.c b/src/gallium/drivers/freedreno/a6xx/fd6_format.c
index 448f104f124..6e9b26b5726 100644
--- a/src/gallium/drivers/freedreno/a6xx/fd6_format.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_format.c
@@ -485,8 +485,8 @@ fd6_tex_const_0(struct pipe_resource *prsc,
 		texconst0 |= A6XX_TEX_CONST_0_SRGB;
 	}
 
-	if (rsc->tile_mode && !fd_resource_level_linear(prsc, level)) {
-		texconst0 |= A6XX_TEX_CONST_0_TILE_MODE(rsc->tile_mode);
+	if (rsc->layout.tile_mode && !fd_resource_level_linear(prsc, level)) {
+		texconst0 |= A6XX_TEX_CONST_0_TILE_MODE(rsc->layout.tile_mode);
 		swap = WZYX;
 	} else {
 		swap = fd6_pipe2swap(format);
diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c b/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c
index 34b5643deae..75c901f7507 100644
--- a/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c
@@ -97,8 +97,8 @@ emit_mrt(struct fd_ringbuffer *ring, struct pipe_framebuffer_state *pfb,
 				psurf->u.tex.first_layer);
 		ubwc_enabled = fd_resource_ubwc_enabled(rsc, psurf->u.tex.level);
 
-		stride = slice->pitch * rsc->cpp * pfb->samples;
-		swap = rsc->tile_mode ? WZYX : fd6_pipe2swap(pformat);
+		stride = slice->pitch * rsc->layout.cpp * pfb->samples;
+		swap = rsc->layout.tile_mode ? WZYX : fd6_pipe2swap(pformat);
 
 		tile_mode = fd_resource_tile_mode(psurf->texture, psurf->u.tex.level);
 
@@ -134,8 +134,8 @@ emit_mrt(struct fd_ringbuffer *ring, struct pipe_framebuffer_state *pfb,
 		OUT_PKT4(ring, REG_A6XX_RB_MRT_FLAG_BUFFER(i), 3);
 		if (ubwc_enabled) {
 			OUT_RELOCW(ring, rsc->bo, ubwc_offset, 0, 0);	/* BASE_LO/HI */
-			OUT_RING(ring, A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH(rsc->ubwc_pitch) |
-				A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH(rsc->ubwc_size));
+			OUT_RING(ring, A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH(rsc->layout.ubwc_pitch) |
+				A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH(rsc->layout.ubwc_size));
 		} else {
 			OUT_RING(ring, 0x00000000);    /* RB_MRT_FLAG_BUFFER[i].ADDR_LO */
 			OUT_RING(ring, 0x00000000);    /* RB_MRT_FLAG_BUFFER[i].ADDR_HI */
@@ -183,7 +183,7 @@ emit_zs(struct fd_ringbuffer *ring, struct pipe_surface *zsbuf,
 		struct fd_resource *rsc = fd_resource(zsbuf->texture);
 		enum a6xx_depth_format fmt = fd6_pipe2depth(zsbuf->format);
 		struct fdl_slice *slice = fd_resource_slice(rsc, 0);
-		uint32_t stride = slice->pitch * rsc->cpp;
+		uint32_t stride = slice->pitch * rsc->layout.cpp;
 		uint32_t size = slice->size0;
 		uint32_t base = gmem ? gmem->zsbuf_base[0] : 0;
 		uint32_t offset = fd_resource_offset(rsc, zsbuf->u.tex.level,
@@ -206,8 +206,8 @@ emit_zs(struct fd_ringbuffer *ring, struct pipe_surface *zsbuf,
 		OUT_PKT4(ring, REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_LO, 3);
 		if (ubwc_enabled) {
 			OUT_RELOCW(ring, rsc->bo, ubwc_offset, 0, 0);	/* BASE_LO/HI */
-			OUT_RING(ring, A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH(rsc->ubwc_pitch) |
-				A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH(rsc->ubwc_size));
+			OUT_RING(ring, A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH(rsc->layout.ubwc_pitch) |
+				A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH(rsc->layout.ubwc_size));
 		} else {
 			OUT_RING(ring, 0x00000000);    /* RB_DEPTH_FLAG_BUFFER_BASE_LO */
 			OUT_RING(ring, 0x00000000);    /* RB_DEPTH_FLAG_BUFFER_BASE_HI */
@@ -239,7 +239,7 @@ emit_zs(struct fd_ringbuffer *ring, struct pipe_surface *zsbuf,
 
 		if (rsc->stencil) {
 			struct fdl_slice *slice = fd_resource_slice(rsc->stencil, 0);
-			stride = slice->pitch * rsc->stencil->cpp;
+			stride = slice->pitch * rsc->stencil->layout.cpp;
 			size = slice->size0;
 			uint32_t base = gmem ? gmem->zsbuf_base[1] : 0;
 
@@ -990,9 +990,9 @@ emit_blit(struct fd_batch *batch,
 	debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
 
 	enum a6xx_color_fmt format = fd6_pipe2color(pfmt);
-	uint32_t stride = slice->pitch * rsc->cpp;
+	uint32_t stride = slice->pitch * rsc->layout.cpp;
 	uint32_t size = slice->size0;
-	enum a3xx_color_swap swap = rsc->tile_mode ? WZYX : fd6_pipe2swap(pfmt);
+	enum a3xx_color_swap swap = rsc->layout.tile_mode ? WZYX : fd6_pipe2swap(pfmt);
 	enum a3xx_msaa_samples samples =
 			fd_msaa_samples(rsc->base.nr_samples);
 	uint32_t tile_mode = fd_resource_tile_mode(&rsc->base, psurf->u.tex.level);
@@ -1014,8 +1014,8 @@ emit_blit(struct fd_batch *batch,
 	if (ubwc_enabled) {
 		OUT_PKT4(ring, REG_A6XX_RB_BLIT_FLAG_DST_LO, 3);
 		OUT_RELOCW(ring, rsc->bo, ubwc_offset, 0, 0);
-		OUT_RING(ring, A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH(rsc->ubwc_pitch) |
-				 A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH(rsc->ubwc_size));
+		OUT_RING(ring, A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH(rsc->layout.ubwc_pitch) |
+				 A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH(rsc->layout.ubwc_size));
 	}
 
 	fd6_emit_blit(batch, ring);
diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_image.c b/src/gallium/drivers/freedreno/a6xx/fd6_image.c
index 8ec50c063a0..62ce378653d 100644
--- a/src/gallium/drivers/freedreno/a6xx/fd6_image.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_image.c
@@ -72,7 +72,7 @@ static void translate_image(struct fd6_image *img, const struct pipe_image_view
 	img->fetchsize = fd6_pipe2fetchsize(format);
 	img->type      = fd6_tex_type(prsc->target);
 	img->srgb      = util_format_is_srgb(format);
-	img->cpp       = rsc->cpp;
+	img->cpp       = rsc->layout.cpp;
 	img->bo        = rsc->bo;
 
 	/* Treat cube textures as 2d-array: */
@@ -102,20 +102,20 @@ static void translate_image(struct fd6_image *img, const struct pipe_image_view
 
 		img->ubwc_offset = fd_resource_ubwc_offset(rsc, lvl, pimg->u.tex.first_layer);
 		img->offset = fd_resource_offset(rsc, lvl, pimg->u.tex.first_layer);
-		img->pitch  = slice->pitch * rsc->cpp;
+		img->pitch  = slice->pitch * rsc->layout.cpp;
 
 		switch (prsc->target) {
 		case PIPE_TEXTURE_RECT:
 		case PIPE_TEXTURE_1D:
 		case PIPE_TEXTURE_2D:
-			img->array_pitch = rsc->layer_size;
+			img->array_pitch = rsc->layout.layer_size;
 			img->depth = 1;
 			break;
 		case PIPE_TEXTURE_1D_ARRAY:
 		case PIPE_TEXTURE_2D_ARRAY:
 		case PIPE_TEXTURE_CUBE:
 		case PIPE_TEXTURE_CUBE_ARRAY:
-			img->array_pitch = rsc->layer_size;
+			img->array_pitch = rsc->layout.layer_size;
 			// TODO the CUBE/CUBE_ARRAY might need to be layers/6 for tex state,
 			// but empirically for ibo state it shouldn't be divided.
 			img->depth = layers;
@@ -151,7 +151,7 @@ static void translate_buf(struct fd6_image *img, const struct pipe_shader_buffer
 	img->fetchsize = fd6_pipe2fetchsize(format);
 	img->type      = fd6_tex_type(prsc->target);
 	img->srgb      = util_format_is_srgb(format);
-	img->cpp       = rsc->cpp;
+	img->cpp       = rsc->layout.cpp;
 	img->bo        = rsc->bo;
 	img->buffer    = true;
 
@@ -197,8 +197,8 @@ static void emit_image_tex(struct fd_ringbuffer *ring, struct fd6_image *img)
 
 	if (ubwc_enabled) {
 		OUT_RELOC(ring, rsc->bo, img->ubwc_offset, 0, 0);
-		OUT_RING(ring, A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH(rsc->ubwc_size));
-		OUT_RING(ring, A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH(rsc->ubwc_pitch));
+		OUT_RING(ring, A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH(rsc->layout.ubwc_size));
+		OUT_RING(ring, A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH(rsc->layout.ubwc_pitch));
 	} else {
 		OUT_RING(ring, 0x00000000);   /* texconst7 */
 		OUT_RING(ring, 0x00000000);   /* texconst8 */
@@ -255,8 +255,8 @@ static void emit_image_ssbo(struct fd_ringbuffer *ring, struct fd6_image *img)
 
 	if (ubwc_enabled) {
 		OUT_RELOCW(ring, rsc->bo, img->ubwc_offset, 0, 0);
-		OUT_RING(ring, A6XX_IBO_9_FLAG_BUFFER_ARRAY_PITCH(rsc->ubwc_size));
-		OUT_RING(ring, A6XX_IBO_10_FLAG_BUFFER_PITCH(rsc->ubwc_pitch));
+		OUT_RING(ring, A6XX_IBO_9_FLAG_BUFFER_ARRAY_PITCH(rsc->layout.ubwc_size));
+		OUT_RING(ring, A6XX_IBO_10_FLAG_BUFFER_PITCH(rsc->layout.ubwc_pitch));
 	} else {
 		OUT_RING(ring, 0x00000000);
 		OUT_RING(ring, 0x00000000);
diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_resource.c b/src/gallium/drivers/freedreno/a6xx/fd6_resource.c
index d246e27b5b1..430044aebbb 100644
--- a/src/gallium/drivers/freedreno/a6xx/fd6_resource.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_resource.c
@@ -73,11 +73,11 @@ setup_slices(struct fd_resource *rsc, uint32_t alignment, enum pipe_format forma
 	/* in layer_first layout, the level (slice) contains just one
 	 * layer (since in fact the layer contains the slices)
 	 */
-	uint32_t layers_in_level = rsc->layer_first ? 1 : prsc->array_size;
-	int ta = rsc->cpp;
+	uint32_t layers_in_level = rsc->layout.layer_first ? 1 : prsc->array_size;
+	int ta = rsc->layout.cpp;
 
 	/* The z16/r16 formats seem to not play by the normal tiling rules: */
-	if ((rsc->cpp == 2) && (util_format_get_nr_components(format) == 1))
+	if ((rsc->layout.cpp == 2) && (util_format_get_nr_components(format) == 1))
 		ta = 0;
 
 	debug_assert(ta < ARRAY_SIZE(tile_alignment));
@@ -134,12 +134,12 @@ setup_slices(struct fd_resource *rsc, uint32_t alignment, enum pipe_format forma
 		 */
 		if (prsc->target == PIPE_TEXTURE_3D) {
 			if (level < 1 || fd_resource_slice(rsc, level - 1)->size0 > 0xf000) {
-				slice->size0 = align(blocks * rsc->cpp, alignment);
+				slice->size0 = align(blocks * rsc->layout.cpp, alignment);
 			} else {
 				slice->size0 = fd_resource_slice(rsc, level - 1)->size0;
 			}
 		} else {
-			slice->size0 = align(blocks * rsc->cpp, alignment);
+			slice->size0 = align(blocks * rsc->layout.cpp, alignment);
 		}
 
 		size += slice->size0 * depth * layers_in_level;
@@ -147,8 +147,8 @@ setup_slices(struct fd_resource *rsc, uint32_t alignment, enum pipe_format forma
 #if 0
 		fprintf(stderr, "%s: %ux%ux%u@%u:\t%2u: stride=%4u, size=%6u,%7u, aligned_height=%3u, blocks=%u, offset=0x%x tiling=%d\n",
 				util_format_name(prsc->format),
-				width, height, depth, rsc->cpp,
-				level, slice->pitch * rsc->cpp,
+				width, height, depth, rsc->layout.cpp,
+				level, slice->pitch * rsc->layout.cpp,
 				slice->size0, size, aligned_height, blocks,
 				slice->offset, fd_resource_tile_mode(prsc, level));
 #endif
@@ -233,7 +233,7 @@ fd6_fill_ubwc_buffer_sizes(struct fd_resource *rsc)
 		return 0;
 
 	uint32_t block_width, block_height;
-	switch (rsc->cpp) {
+	switch (rsc->layout.cpp) {
 	case 2:
 	case 4:
 		block_width = 16;
@@ -262,11 +262,11 @@ fd6_fill_ubwc_buffer_sizes(struct fd_resource *rsc)
 	 * because it is what the kernel expects for scanout.  For non-2D we
 	 * could just use a separate UBWC buffer..
 	 */
-	rsc->ubwc_offset = 0;
-	rsc->offset = meta_size;
-	rsc->ubwc_pitch = meta_stride;
-	rsc->ubwc_size = meta_size >> 2;   /* in dwords??? */
-	rsc->tile_mode = TILE6_3;
+	rsc->layout.ubwc_offset = 0;
+	rsc->layout.offset = meta_size;
+	rsc->layout.ubwc_pitch = meta_stride;
+	rsc->layout.ubwc_size = meta_size >> 2;   /* in dwords??? */
+	rsc->layout.tile_mode = TILE6_3;
 
 	return meta_size;
 }
@@ -280,7 +280,7 @@ void
 fd6_validate_format(struct fd_context *ctx, struct fd_resource *rsc,
 		enum pipe_format format)
 {
-	if (!rsc->ubwc_size)
+	if (!rsc->layout.ubwc_size)
 		return;
 
 	if (ok_ubwc_format(format))
@@ -296,11 +296,11 @@ fd6_setup_slices(struct fd_resource *rsc)
 
 	switch (rsc->base.target) {
 	case PIPE_TEXTURE_3D:
-		rsc->layer_first = false;
+		rsc->layout.layer_first = false;
 		alignment = 4096;
 		break;
 	default:
-		rsc->layer_first = true;
+		rsc->layout.layer_first = true;
 		alignment = 1;
 		break;
 	}
diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_texture.c b/src/gallium/drivers/freedreno/a6xx/fd6_texture.c
index 5bde6abc1e5..585d3eb81e8 100644
--- a/src/gallium/drivers/freedreno/a6xx/fd6_texture.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_texture.c
@@ -267,7 +267,7 @@ fd6_sampler_view_create(struct pipe_context *pctx, struct pipe_resource *prsc,
 		so->texconst2 =
 			A6XX_TEX_CONST_2_FETCHSIZE(fd6_pipe2fetchsize(format)) |
 			A6XX_TEX_CONST_2_PITCH(
-				util_format_get_nblocksx(format, slice->pitch) * rsc->cpp);
+				util_format_get_nblocksx(format, slice->pitch) * rsc->layout.cpp);
 		so->offset = fd_resource_offset(rsc, lvl, cso->u.tex.first_layer);
 		so->ubwc_offset = fd_resource_ubwc_offset(rsc, lvl, cso->u.tex.first_layer);
 		so->ubwc_enabled = fd_resource_ubwc_enabled(rsc, lvl);
@@ -278,8 +278,8 @@ fd6_sampler_view_create(struct pipe_context *pctx, struct pipe_resource *prsc,
 				cso->swizzle_b, cso->swizzle_a);
 
 	if (so->ubwc_enabled) {
-		so->texconst9 |= A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH(rsc->ubwc_size);
-		so->texconst10 |= A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH(rsc->ubwc_pitch);
+		so->texconst9 |= A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH(rsc->layout.ubwc_size);
+		so->texconst10 |= A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH(rsc->layout.ubwc_pitch);
 	}
 
 	so->texconst2 |= A6XX_TEX_CONST_2_TYPE(fd6_tex_type(cso->target));
@@ -289,21 +289,21 @@ fd6_sampler_view_create(struct pipe_context *pctx, struct pipe_resource *prsc,
 	case PIPE_TEXTURE_1D:
 	case PIPE_TEXTURE_2D:
 		so->texconst3 =
-			A6XX_TEX_CONST_3_ARRAY_PITCH(rsc->layer_size);
+			A6XX_TEX_CONST_3_ARRAY_PITCH(rsc->layout.layer_size);
 		so->texconst5 =
 			A6XX_TEX_CONST_5_DEPTH(1);
 		break;
 	case PIPE_TEXTURE_1D_ARRAY:
 	case PIPE_TEXTURE_2D_ARRAY:
 		so->texconst3 =
-			A6XX_TEX_CONST_3_ARRAY_PITCH(rsc->layer_size);
+			A6XX_TEX_CONST_3_ARRAY_PITCH(rsc->layout.layer_size);
 		so->texconst5 =
 			A6XX_TEX_CONST_5_DEPTH(layers);
 		break;
 	case PIPE_TEXTURE_CUBE:
 	case PIPE_TEXTURE_CUBE_ARRAY:
 		so->texconst3 =
-			A6XX_TEX_CONST_3_ARRAY_PITCH(rsc->layer_size);
+			A6XX_TEX_CONST_3_ARRAY_PITCH(rsc->layout.layer_size);
 		so->texconst5 =
 			A6XX_TEX_CONST_5_DEPTH(layers / 6);
 		break;
diff --git a/src/gallium/drivers/freedreno/freedreno_gmem.c b/src/gallium/drivers/freedreno/freedreno_gmem.c
index a8568a1ef93..4688b16c868 100644
--- a/src/gallium/drivers/freedreno/freedreno_gmem.c
+++ b/src/gallium/drivers/freedreno/freedreno_gmem.c
@@ -130,9 +130,9 @@ calculate_tiles(struct fd_batch *batch)
 
 	if (has_zs) {
 		struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
-		zsbuf_cpp[0] = rsc->cpp;
+		zsbuf_cpp[0] = rsc->layout.cpp;
 		if (rsc->stencil)
-			zsbuf_cpp[1] = rsc->stencil->cpp;
+			zsbuf_cpp[1] = rsc->stencil->layout.cpp;
 	} else {
 		/* we might have a zsbuf, but it isn't used */
 		batch->restore &= ~(FD_BUFFER_DEPTH | FD_BUFFER_STENCIL);
diff --git a/src/gallium/drivers/freedreno/freedreno_resource.c b/src/gallium/drivers/freedreno/freedreno_resource.c
index 0044b9804b3..b998bac36eb 100644
--- a/src/gallium/drivers/freedreno/freedreno_resource.c
+++ b/src/gallium/drivers/freedreno/freedreno_resource.c
@@ -132,7 +132,7 @@ realloc_bo(struct fd_resource *rsc, uint32_t size)
 		fd_bo_del(rsc->bo);
 
 	rsc->bo = fd_bo_new(screen->dev, size, flags, "%ux%ux%u@%u:%x",
-			prsc->width0, prsc->height0, prsc->depth0, rsc->cpp, prsc->bind);
+			prsc->width0, prsc->height0, prsc->depth0, rsc->layout.cpp, prsc->bind);
 	rsc->seqno = p_atomic_inc_return(&screen->rsc_seqno);
 	util_range_set_empty(&rsc->valid_buffer_range);
 	fd_bc_invalidate_resource(rsc, true);
@@ -223,10 +223,10 @@ fd_try_shadow_resource(struct fd_context *ctx, struct fd_resource *rsc,
 	/* TODO valid_buffer_range?? */
 	swap(rsc->bo,        shadow->bo);
 	swap(rsc->write_batch,   shadow->write_batch);
-	swap(rsc->offset, shadow->offset);
-	swap(rsc->ubwc_offset, shadow->ubwc_offset);
-	swap(rsc->ubwc_pitch, shadow->ubwc_pitch);
-	swap(rsc->ubwc_size, shadow->ubwc_size);
+	swap(rsc->layout.offset, shadow->layout.offset);
+	swap(rsc->layout.ubwc_offset, shadow->layout.ubwc_offset);
+	swap(rsc->layout.ubwc_pitch, shadow->layout.ubwc_pitch);
+	swap(rsc->layout.ubwc_size, shadow->layout.ubwc_size);
 	rsc->seqno = p_atomic_inc_return(&ctx->screen->rsc_seqno);
 
 	/* at this point, the newly created shadow buffer is not referenced
@@ -530,7 +530,7 @@ fd_resource_transfer_map(struct pipe_context *pctx,
 	ptrans->level = level;
 	ptrans->usage = usage;
 	ptrans->box = *box;
-	ptrans->stride = util_format_get_nblocksx(format, slice->pitch) * rsc->cpp;
+	ptrans->stride = util_format_get_nblocksx(format, slice->pitch) * rsc->layout.cpp;
 	ptrans->layer_stride = fd_resource_layer_stride(rsc, level);
 
 	/* we always need a staging texture for tiled buffers:
@@ -539,7 +539,7 @@ fd_resource_transfer_map(struct pipe_context *pctx,
 	 * splitting a batch.. for ex, mid-frame texture uploads to a tiled
 	 * texture.
 	 */
-	if (rsc->tile_mode) {
+	if (rsc->layout.tile_mode) {
 		struct fd_resource *staging_rsc;
 
 		staging_rsc = fd_alloc_staging(ctx, rsc, level, box);
@@ -549,7 +549,7 @@ fd_resource_transfer_map(struct pipe_context *pctx,
 			// TODO for PIPE_TRANSFER_READ, need to do untiling blit..
 			trans->staging_prsc = &staging_rsc->base;
 			trans->base.stride = util_format_get_nblocksx(format,
-				staging_slice->pitch) * staging_rsc->cpp;
+				staging_slice->pitch) * staging_rsc->layout.cpp;
 			trans->base.layer_stride = fd_resource_layer_stride(staging_rsc, 0);
 			trans->staging_box = *box;
 			trans->staging_box.x = 0;
@@ -665,7 +665,7 @@ fd_resource_transfer_map(struct pipe_context *pctx,
 						fd_resource_slice(staging_rsc, 0);
 					trans->staging_prsc = &staging_rsc->base;
 					trans->base.stride = util_format_get_nblocksx(format,
-						staging_slice->pitch) * staging_rsc->cpp;
+						staging_slice->pitch) * staging_rsc->layout.cpp;
 					trans->base.layer_stride =
 						fd_resource_layer_stride(staging_rsc, 0);
 					trans->staging_box = *box;
@@ -707,7 +707,7 @@ fd_resource_transfer_map(struct pipe_context *pctx,
 	buf = fd_bo_map(rsc->bo);
 	offset =
 		box->y / util_format_get_blockheight(format) * ptrans->stride +
-		box->x / util_format_get_blockwidth(format) * rsc->cpp +
+		box->x / util_format_get_blockwidth(format) * rsc->layout.cpp +
 		fd_resource_offset(rsc, level, box->z);
 
 	if (usage & PIPE_TRANSFER_WRITE)
@@ -740,10 +740,10 @@ fd_resource_destroy(struct pipe_screen *pscreen,
 static uint64_t
 fd_resource_modifier(struct fd_resource *rsc)
 {
-	if (!rsc->tile_mode)
+	if (!rsc->layout.tile_mode)
 		return DRM_FORMAT_MOD_LINEAR;
 
-	if (rsc->ubwc_size)
+	if (rsc->layout.ubwc_size)
 		return DRM_FORMAT_MOD_QCOM_COMPRESSED;
 
 	/* TODO invent a modifier for tiled but not UBWC buffers: */
@@ -762,7 +762,7 @@ fd_resource_get_handle(struct pipe_screen *pscreen,
 	handle->modifier = fd_resource_modifier(rsc);
 
 	return fd_screen_bo_get_handle(pscreen, rsc->bo, rsc->scanout,
-			fd_resource_slice(rsc, 0)->pitch * rsc->cpp, handle);
+			fd_resource_slice(rsc, 0)->pitch * rsc->layout.cpp, handle);
 }
 
 static uint32_t
@@ -779,7 +779,7 @@ setup_slices(struct fd_resource *rsc, uint32_t alignment, enum pipe_format forma
 	/* in layer_first layout, the level (slice) contains just one
 	 * layer (since in fact the layer contains the slices)
 	 */
-	uint32_t layers_in_level = rsc->layer_first ? 1 : prsc->array_size;
+	uint32_t layers_in_level = rsc->layout.layer_first ? 1 : prsc->array_size;
 
 	for (level = 0; level <= prsc->last_level; level++) {
 		struct fdl_slice *slice = fd_resource_slice(rsc, level);
@@ -801,9 +801,9 @@ setup_slices(struct fd_resource *rsc, uint32_t alignment, enum pipe_format forma
 		if (prsc->target == PIPE_TEXTURE_3D && (
 					level == 1 ||
 					(level > 1 && fd_resource_slice(rsc, level - 1)->size0 > 0xf000)))
-			slice->size0 = align(blocks * rsc->cpp, alignment);
-		else if (level == 0 || rsc->layer_first || alignment == 1)
-			slice->size0 = align(blocks * rsc->cpp, alignment);
+			slice->size0 = align(blocks * rsc->layout.cpp, alignment);
+		else if (level == 0 || rsc->layout.layer_first || alignment == 1)
+			slice->size0 = align(blocks * rsc->layout.cpp, alignment);
 		else
 			slice->size0 = fd_resource_slice(rsc, level - 1)->size0;
 
@@ -851,10 +851,10 @@ fd_setup_slices(struct fd_resource *rsc)
 	if (is_a4xx(screen)) {
 		switch (rsc->base.target) {
 		case PIPE_TEXTURE_3D:
-			rsc->layer_first = false;
+			rsc->layout.layer_first = false;
 			break;
 		default:
-			rsc->layer_first = true;
+			rsc->layout.layer_first = true;
 			alignment = 1;
 			break;
 		}
@@ -896,6 +896,20 @@ has_depth(enum pipe_format format)
 	}
 }
 
+static void
+fd_resource_layout_init(struct pipe_resource *prsc)
+{
+	struct fd_resource *rsc = fd_resource(prsc);
+	struct fdl_layout *layout = &rsc->layout;
+
+	layout->width0 = prsc->width0;
+	layout->height0 = prsc->height0;
+	layout->depth0 = prsc->depth0;
+
+	layout->cpp = util_format_get_blocksize(prsc->format);
+	layout->cpp *= fd_resource_nr_samples(prsc);
+}
+
 /**
  * Create a new texture object, using the given template info.
  */
@@ -956,6 +970,7 @@ fd_resource_create_with_modifiers(struct pipe_screen *pscreen,
 		return NULL;
 
 	*prsc = *tmpl;
+	fd_resource_layout_init(prsc);
 
 #define LINEAR \
 	(PIPE_BIND_SCANOUT | \
@@ -987,16 +1002,12 @@ fd_resource_create_with_modifiers(struct pipe_screen *pscreen,
 	if (screen->tile_mode &&
 			(tmpl->target != PIPE_BUFFER) &&
 			!linear) {
-		rsc->tile_mode = screen->tile_mode(prsc);
+		rsc->layout.tile_mode = screen->tile_mode(prsc);
 	}
 
 	util_range_init(&rsc->valid_buffer_range);
 
 	rsc->internal_format = format;
-	rsc->cpp = util_format_get_blocksize(format);
-	rsc->cpp *= fd_resource_nr_samples(prsc);
-
-	assert(rsc->cpp);
 
 	// XXX probably need some extra work if we hit rsc shadowing path w/ lrz..
 	if ((is_a5xx(screen) || is_a6xx(screen)) &&
@@ -1026,7 +1037,7 @@ fd_resource_create_with_modifiers(struct pipe_screen *pscreen,
 
 	size = screen->setup_slices(rsc);
 
-	if (allow_ubwc && screen->fill_ubwc_buffer_sizes && rsc->tile_mode)
+	if (allow_ubwc && screen->fill_ubwc_buffer_sizes && rsc->layout.tile_mode)
 		size += screen->fill_ubwc_buffer_sizes(rsc);
 
 	/* special case for hw-query buffer, which we need to allocate before we
@@ -1038,9 +1049,9 @@ fd_resource_create_with_modifiers(struct pipe_screen *pscreen,
 		return prsc;
 	}
 
-	if (rsc->layer_first) {
-		rsc->layer_size = align(size, 4096);
-		size = rsc->layer_size * prsc->array_size;
+	if (rsc->layout.layer_first) {
+		rsc->layout.layer_size = align(size, 4096);
+		size = rsc->layout.layer_size * prsc->array_size;
 	}
 
 	realloc_bo(rsc, size);
@@ -1108,6 +1119,7 @@ fd_resource_from_handle(struct pipe_screen *pscreen,
 		return NULL;
 
 	*prsc = *tmpl;
+	fd_resource_layout_init(prsc);
 
 	pipe_reference_init(&prsc->reference, 1);
 
@@ -1120,9 +1132,7 @@ fd_resource_from_handle(struct pipe_screen *pscreen,
 		goto fail;
 
 	rsc->internal_format = tmpl->format;
-	rsc->cpp = util_format_get_blocksize(tmpl->format);
-	rsc->cpp *= fd_resource_nr_samples(prsc);
-	slice->pitch = handle->stride / rsc->cpp;
+	slice->pitch = handle->stride / rsc->layout.cpp;
 	slice->offset = handle->offset;
 	slice->size0 = handle->stride * prsc->height0;
 
@@ -1143,7 +1153,7 @@ fd_resource_from_handle(struct pipe_screen *pscreen,
 		goto fail;
 	}
 
-	assert(rsc->cpp);
+	assert(rsc->layout.cpp);
 
 	if (screen->ro) {
 		rsc->scanout =
diff --git a/src/gallium/drivers/freedreno/freedreno_resource.h b/src/gallium/drivers/freedreno/freedreno_resource.h
index d019727bf31..bc972297a35 100644
--- a/src/gallium/drivers/freedreno/freedreno_resource.h
+++ b/src/gallium/drivers/freedreno/freedreno_resource.h
@@ -38,11 +38,9 @@
 struct fd_resource {
 	struct pipe_resource base;
 	struct fd_bo *bo;
-	uint32_t cpp;
 	enum pipe_format internal_format;
-	bool layer_first;        /* see above description */
-	uint32_t layer_size;
-	struct fdl_slice slices[MAX_MIP_LEVELS];
+	struct fdl_layout layout;
+
 	/* buffer range that has been initialized */
 	struct util_range valid_buffer_range;
 	bool valid;
@@ -52,11 +50,6 @@ struct fd_resource {
 	/* TODO rename to secondary or auxiliary? */
 	struct fd_resource *stencil;
 
-	uint32_t offset;
-	uint32_t ubwc_offset;
-	uint32_t ubwc_pitch;
-	uint32_t ubwc_size;
-
 	/* bitmask of in-flight batches which reference this resource.  Note
 	 * that the batch doesn't hold reference to resources (but instead
 	 * the fd_ringbuffer holds refs to the underlying fd_bo), but in case
@@ -78,10 +71,11 @@ struct fd_resource {
 	/* Sequence # incremented each time bo changes: */
 	uint16_t seqno;
 
-	unsigned tile_mode : 2;
-
 	/*
 	 * LRZ
+	 *
+	 * TODO lrz width/height/pitch should probably also move to
+	 * fdl_layout
 	 */
 	bool lrz_valid : 1;
 	uint16_t lrz_width;  // for lrz clear, does this differ from lrz_pitch?
@@ -96,6 +90,12 @@ fd_resource(struct pipe_resource *ptex)
 	return (struct fd_resource *)ptex;
 }
 
+static inline const struct fd_resource *
+fd_resource_const(const struct pipe_resource *ptex)
+{
+	return (const struct fd_resource *)ptex;
+}
+
 static inline bool
 pending(struct fd_resource *rsc, bool write)
 {
@@ -129,40 +129,28 @@ static inline struct fdl_slice *
 fd_resource_slice(struct fd_resource *rsc, unsigned level)
 {
 	assert(level <= rsc->base.last_level);
-	return &rsc->slices[level];
+	return &rsc->layout.slices[level];
 }
 
 static inline uint32_t
 fd_resource_layer_stride(struct fd_resource *rsc, unsigned level)
 {
-	if (rsc->layer_first)
-		return rsc->layer_size;
-	else
-		return fd_resource_slice(rsc, level)->size0;
+	return fdl_layer_stride(&rsc->layout, level);
 }
 
 /* get offset for specified mipmap level and texture/array layer */
 static inline uint32_t
 fd_resource_offset(struct fd_resource *rsc, unsigned level, unsigned layer)
 {
-	struct fdl_slice *slice = fd_resource_slice(rsc, level);
-	unsigned offset = slice->offset;
-	offset += fd_resource_layer_stride(rsc, level) * layer;
+	uint32_t offset = fdl_surface_offset(&rsc->layout, level, layer);
 	debug_assert(offset < fd_bo_size(rsc->bo));
-	return offset + rsc->offset;
+	return offset;
 }
 
 static inline uint32_t
 fd_resource_ubwc_offset(struct fd_resource *rsc, unsigned level, unsigned layer)
 {
-	/* for now this doesn't do anything clever, but when UBWC is enabled
-	 * for multi layer/level images, it will.
-	 */
-	if (rsc->ubwc_size) {
-		debug_assert(level == 0);
-		debug_assert(layer == 0);
-	}
-	return rsc->ubwc_offset;
+	return fdl_ubwc_offset(&rsc->layout, level, layer);
 }
 
 /* This might be a5xx specific, but higher mipmap levels are always linear: */
@@ -172,26 +160,19 @@ fd_resource_level_linear(const struct pipe_resource *prsc, int level)
 	struct fd_screen *screen = fd_screen(prsc->screen);
 	debug_assert(!is_a3xx(screen));
 
-	unsigned w = u_minify(prsc->width0, level);
-	if (w < 16)
-		return true;
-	return false;
+	return fdl_level_linear(&fd_resource_const(prsc)->layout, level);
 }
 
 static inline uint32_t
 fd_resource_tile_mode(struct pipe_resource *prsc, int level)
 {
-	struct fd_resource *rsc = fd_resource(prsc);
-	if (rsc->tile_mode && fd_resource_level_linear(&rsc->base, level))
-		return 0; /* linear */
-	else
-		return rsc->tile_mode;
+	return fdl_tile_mode(&fd_resource(prsc)->layout, level);
 }
 
 static inline bool
 fd_resource_ubwc_enabled(struct fd_resource *rsc, int level)
 {
-	return rsc->ubwc_size && fd_resource_tile_mode(&rsc->base, level);
+	return fdl_ubwc_enabled(&rsc->layout, level);
 }
 
 /* access # of samples, with 0 normalized to 1 (which is what we care about
diff --git a/src/gallium/drivers/freedreno/ir3/ir3_gallium.c b/src/gallium/drivers/freedreno/ir3/ir3_gallium.c
index a9eb189d1f2..6ba01c62a53 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3_gallium.c
+++ b/src/gallium/drivers/freedreno/ir3/ir3_gallium.c
@@ -350,10 +350,10 @@ ir3_emit_image_dims(struct fd_screen *screen, const struct ir3_shader_variant *v
 				 * be the same, so use original dimensions for y and z
 				 * stride:
 				 */
-				dims[off + 1] = slice->pitch * rsc->cpp;
+				dims[off + 1] = slice->pitch * rsc->layout.cpp;
 				/* see corresponding logic in fd_resource_offset(): */
-				if (rsc->layer_first) {
-					dims[off + 2] = rsc->layer_size;
+				if (rsc->layout.layer_first) {
+					dims[off + 2] = rsc->layout.layer_size;
 				} else {
 					dims[off + 2] = slice->size0;
 				}