diff options
| author | Jerome Glisse <[email protected]> | 2013-02-06 13:54:02 -0500 |
|---|---|---|
| committer | Jerome Glisse <[email protected]> | 2013-02-07 10:42:22 -0500 |
| commit | 681707abf2121e9d02c6fd13e312fd103f26949c (patch) | |
| tree | f840c6b803914c76c05c9f7a5ee24c5373643503 /src/gallium/drivers | |
| parent | 9ba1e23647c09290c98cc7133fb73dd1df1da8ab (diff) | |
r600g: fix slice tile max for compressed texture and async dma
Was using the pixel size instead of the number of block for the slice
tile max computation which resulted in dma writing at wrong address.
Signed-off-by: Jerome Glisse <[email protected]>
Diffstat (limited to 'src/gallium/drivers')
| -rw-r--r-- | src/gallium/drivers/r600/evergreen_state.c | 6 | ||||
| -rw-r--r-- | src/gallium/drivers/r600/r600_state.c | 6 |
2 files changed, 8 insertions, 4 deletions
diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c index f076fcaa156..211c2183bff 100644 --- a/src/gallium/drivers/r600/evergreen_state.c +++ b/src/gallium/drivers/r600/evergreen_state.c @@ -3532,7 +3532,8 @@ static void evergreen_dma_copy_tile(struct r600_context *rctx, if (dst_mode == RADEON_SURF_MODE_LINEAR) { /* T2L */ array_mode = evergreen_array_mode(src_mode); - slice_tile_max = (((pitch * rsrc->surface.level[src_level].npix_y) >> 6) / bpp) - 1; + slice_tile_max = (rsrc->surface.level[src_level].nblk_x * rsrc->surface.level[src_level].nblk_y) >> 6; + slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0; /* linear height must be the same as the slice tile max height, it's ok even * if the linear destination/source have smaller heigh as the size of the * dma packet will be using the copy_height which is always smaller or equal @@ -3556,7 +3557,8 @@ static void evergreen_dma_copy_tile(struct r600_context *rctx, } else { /* L2T */ array_mode = evergreen_array_mode(dst_mode); - slice_tile_max = (((pitch * rdst->surface.level[dst_level].npix_y) >> 6) / bpp) - 1; + slice_tile_max = (rdst->surface.level[dst_level].nblk_x * rdst->surface.level[dst_level].nblk_y) >> 6; + slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0; /* linear height must be the same as the slice tile max height, it's ok even * if the linear destination/source have smaller heigh as the size of the * dma packet will be using the copy_height which is always smaller or equal diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c index 1e2f2dd6a73..67c4d99f213 100644 --- a/src/gallium/drivers/r600/r600_state.c +++ b/src/gallium/drivers/r600/r600_state.c @@ -3027,7 +3027,8 @@ static boolean r600_dma_copy_tile(struct r600_context *rctx, if (dst_mode == RADEON_SURF_MODE_LINEAR) { /* T2L */ array_mode = r600_array_mode(src_mode); - slice_tile_max = (((pitch * rsrc->surface.level[src_level].npix_y) >> 6) / bpp) - 1; + slice_tile_max = (rsrc->surface.level[src_level].nblk_x * rsrc->surface.level[src_level].nblk_y) >> 6; + slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0; /* linear height must be the same as the slice tile max height, it's ok even * if the linear destination/source have smaller heigh as the size of the * dma packet will be using the copy_height which is always smaller or equal @@ -3045,7 +3046,8 @@ static boolean r600_dma_copy_tile(struct r600_context *rctx, } else { /* L2T */ array_mode = r600_array_mode(dst_mode); - slice_tile_max = (((pitch * rdst->surface.level[dst_level].npix_y) >> 6) / bpp) - 1; + slice_tile_max = (rdst->surface.level[dst_level].nblk_x * rdst->surface.level[dst_level].nblk_y) >> 6; + slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0; /* linear height must be the same as the slice tile max height, it's ok even * if the linear destination/source have smaller heigh as the size of the * dma packet will be using the copy_height which is always smaller or equal |