diff options
| author | Rob Clark <[email protected]> | 2014-05-17 13:49:52 -0400 |
|---|---|---|
| committer | Rob Clark <[email protected]> | 2014-05-18 15:23:53 -0400 |
| commit | 88ba9de917dfe92040f4e0508f18f6817987e538 (patch) | |
| tree | 7bf819393271fa131c394261be0fcd1e8c78c785 /src/gallium/drivers | |
| parent | 6f84f64643ffb9af58b0ccddccbec9135f2756bd (diff) | |
freedreno/a3xx/compiler: 1D textures
Gallium already gives us height==1 for these, so the texture state is
already setup correctly to emulate 1D textures as a Nx1 2D texture. We
just need to supply the .y coord.
Signed-off-by: Rob Clark <[email protected]>
Diffstat (limited to 'src/gallium/drivers')
| -rw-r--r-- | src/gallium/drivers/freedreno/a3xx/fd3_compiler.c | 29 |
1 files changed, 25 insertions, 4 deletions
diff --git a/src/gallium/drivers/freedreno/a3xx/fd3_compiler.c b/src/gallium/drivers/freedreno/a3xx/fd3_compiler.c index bb20416fc32..30f033606fb 100644 --- a/src/gallium/drivers/freedreno/a3xx/fd3_compiler.c +++ b/src/gallium/drivers/freedreno/a3xx/fd3_compiler.c @@ -1091,14 +1091,18 @@ trans_samp(const struct instr_translater *t, switch (t->arg) { case TGSI_OPCODE_TEX: switch (tex) { + case TGSI_TEXTURE_1D: + order = (int8_t[4]){ 0, -1, -1, -1 }; /* coord.x */ + src_wrmask = TGSI_WRITEMASK_XY; + break; case TGSI_TEXTURE_2D: case TGSI_TEXTURE_RECT: - order = (int8_t[4]){ 0, 1, -1, -1 }; + order = (int8_t[4]){ 0, 1, -1, -1 }; /* coord.xy */ src_wrmask = TGSI_WRITEMASK_XY; break; case TGSI_TEXTURE_3D: case TGSI_TEXTURE_CUBE: - order = (int8_t[4]){ 0, 1, 2, -1 }; + order = (int8_t[4]){ 0, 1, 2, -1 }; /* coord.xyz */ src_wrmask = TGSI_WRITEMASK_XYZ; flags |= IR3_INSTR_3D; break; @@ -1110,14 +1114,18 @@ trans_samp(const struct instr_translater *t, break; case TGSI_OPCODE_TXP: switch (tex) { + case TGSI_TEXTURE_1D: + order = (int8_t[4]){ 0, -1, 3, -1 }; /* coord.xw */ + src_wrmask = TGSI_WRITEMASK_XYZ; + break; case TGSI_TEXTURE_2D: case TGSI_TEXTURE_RECT: - order = (int8_t[4]){ 0, 1, 3, -1 }; + order = (int8_t[4]){ 0, 1, 3, -1 }; /* coord.xyw */ src_wrmask = TGSI_WRITEMASK_XYZ; break; case TGSI_TEXTURE_3D: case TGSI_TEXTURE_CUBE: - order = (int8_t[4]){ 0, 1, 2, 3 }; + order = (int8_t[4]){ 0, 1, 2, 3 }; /* coord.xyzw */ src_wrmask = TGSI_WRITEMASK_XYZW; flags |= IR3_INSTR_3D; break; @@ -1137,6 +1145,10 @@ trans_samp(const struct instr_translater *t, if (is_rel_or_const(coord)) needs_mov = true; + /* 1D textures we fix up w/ 0.0 as 2nd coord: */ + if (tex == TGSI_TEXTURE_1D) + needs_mov = true; + /* The texture sample instructions need to coord in successive * registers/components (ie. src.xy but not src.yx). And TXP * needs the .w component in .z for 2D.. so in some cases we @@ -1166,6 +1178,15 @@ trans_samp(const struct instr_translater *t, src_swiz(coord, order[j])); } + /* fix up .y coord: */ + if (tex == TGSI_TEXTURE_1D) { + instr = instr_create(ctx, 1, 0); + instr->cat1.src_type = type_mov; + instr->cat1.dst_type = type_mov; + add_dst_reg(ctx, instr, &tmp_dst, 1); /* .y */ + ir3_reg_create(instr, 0, IR3_REG_IMMED)->fim_val = 0.5; + } + coord = tmp_src; } |