radeonsi: remove old state handling

Signed-off-by: Christian König <[email protected]>

8 files changed, 1 insertions, 690 deletions

diff --git a/src/gallium/drivers/radeonsi/evergreen_hw_context.c b/src/gallium/drivers/radeonsi/evergreen_hw_context.c
index 299ead8c5a3..c27221ca675 100644
--- a/src/gallium/drivers/radeonsi/evergreen_hw_context.c
+++ b/src/gallium/drivers/radeonsi/evergreen_hw_context.c
@@ -30,208 +30,17 @@
 #include "util/u_memory.h"
 #include <errno.h>
 
-#define GROUP_FORCE_NEW_BLOCK	0
-
-static const struct r600_reg si_config_reg_list[] = {
-	{R_0088B0_VGT_VTX_VECT_EJECT_REG, REG_FLAG_FLUSH_CHANGE},
-	{R_0088C8_VGT_ESGS_RING_SIZE, REG_FLAG_FLUSH_CHANGE},
-	{R_0088CC_VGT_GSVS_RING_SIZE, REG_FLAG_FLUSH_CHANGE},
-	{R_008A14_PA_CL_ENHANCE, REG_FLAG_FLUSH_CHANGE},
-	{R_009100_SPI_CONFIG_CNTL, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE},
-	{R_00913C_SPI_CONFIG_CNTL_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE},
-};
-
-static const struct r600_reg si_context_reg_list[] = {
-	{R_028004_DB_COUNT_CONTROL, 0},
-	{R_028010_DB_RENDER_OVERRIDE2, 0},
-	{GROUP_FORCE_NEW_BLOCK, 0},
-	{R_028014_DB_HTILE_DATA_BASE, REG_FLAG_NEED_BO},
-	{GROUP_FORCE_NEW_BLOCK, 0},
-	{R_028080_TA_BC_BASE_ADDR, REG_FLAG_NEED_BO},
-	{GROUP_FORCE_NEW_BLOCK, 0},
-	{R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0},
-	{GROUP_FORCE_NEW_BLOCK, 0},
-	{R_0286C4_SPI_VS_OUT_CONFIG, 0},
-	{R_0286CC_SPI_PS_INPUT_ENA, 0},
-	{R_0286D0_SPI_PS_INPUT_ADDR, 0},
-	{R_0286D8_SPI_PS_IN_CONTROL, 0},
-	{R_0286E0_SPI_BARYC_CNTL, 0},
-	{R_02870C_SPI_SHADER_POS_FORMAT, 0},
-	{R_028710_SPI_SHADER_Z_FORMAT, 0},
-	{R_028714_SPI_SHADER_COL_FORMAT, 0},
-	{R_0287D4_PA_CL_POINT_X_RAD, 0},
-	{R_0287D8_PA_CL_POINT_Y_RAD, 0},
-	{R_0287DC_PA_CL_POINT_SIZE, 0},
-	{R_0287E0_PA_CL_POINT_CULL_RAD, 0},
-	{R_028804_DB_EQAA, 0},
-	{R_02880C_DB_SHADER_CONTROL, 0},
-	{R_028824_PA_SU_LINE_STIPPLE_CNTL, 0},
-	{R_028828_PA_SU_LINE_STIPPLE_SCALE, 0},
-	{R_02882C_PA_SU_PRIM_FILTER_CNTL, 0},
-	{R_028A10_VGT_OUTPUT_PATH_CNTL, 0},
-	{R_028A14_VGT_HOS_CNTL, 0},
-	{R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0},
-	{R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0},
-	{R_028A20_VGT_HOS_REUSE_DEPTH, 0},
-	{R_028A24_VGT_GROUP_PRIM_TYPE, 0},
-	{R_028A28_VGT_GROUP_FIRST_DECR, 0},
-	{R_028A2C_VGT_GROUP_DECR, 0},
-	{R_028A30_VGT_GROUP_VECT_0_CNTL, 0},
-	{R_028A34_VGT_GROUP_VECT_1_CNTL, 0},
-	{R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0},
-	{R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0},
-	{R_028A40_VGT_GS_MODE, 0},
-	{R_028A4C_PA_SC_MODE_CNTL_1, 0},
-	{R_028A50_VGT_ENHANCE, 0},
-	{R_028A54_VGT_GS_PER_ES, 0},
-	{R_028A58_VGT_ES_PER_GS, 0},
-	{R_028A5C_VGT_GS_PER_VS, 0},
-	{R_028A60_VGT_GSVS_RING_OFFSET_1, 0},
-	{R_028A64_VGT_GSVS_RING_OFFSET_2, 0},
-	{R_028A68_VGT_GSVS_RING_OFFSET_3, 0},
-	{R_028A6C_VGT_GS_OUT_PRIM_TYPE, 0},
-	{R_028A70_IA_ENHANCE, 0},
-	{R_028A84_VGT_PRIMITIVEID_EN, 0},
-	{R_028A8C_VGT_PRIMITIVEID_RESET, 0},
-	{R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0},
-	{R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0},
-	{R_028AA8_IA_MULTI_VGT_PARAM, 0},
-	{R_028AAC_VGT_ESGS_RING_ITEMSIZE, 0},
-	{R_028AB0_VGT_GSVS_RING_ITEMSIZE, 0},
-	{R_028AB4_VGT_REUSE_OFF, 0},
-	{R_028AB8_VGT_VTX_CNT_EN, 0},
-	{R_028ABC_DB_HTILE_SURFACE, 0},
-	{R_028B54_VGT_SHADER_STAGES_EN, 0},
-	{R_028B94_VGT_STRMOUT_CONFIG, 0},
-	{R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0},
-	{R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0},
-	{R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0},
-	{R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 0},
-	{R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, 0},
-	{R_028C00_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2, 0},
-	{R_028C04_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3, 0},
-	{R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, 0},
-	{R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, 0},
-	{R_028C10_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2, 0},
-	{R_028C14_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3, 0},
-	{R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, 0},
-	{R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, 0},
-	{R_028C20_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2, 0},
-	{R_028C24_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3, 0},
-	{R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, 0},
-	{R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, 0},
-	{R_028C30_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2, 0},
-	{R_028C34_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3, 0},
-};
-
-static const struct r600_reg si_sh_reg_list[] = {
-	{R_00B020_SPI_SHADER_PGM_LO_PS, REG_FLAG_NEED_BO},
-	{R_00B024_SPI_SHADER_PGM_HI_PS, REG_FLAG_NEED_BO},
-	{R_00B028_SPI_SHADER_PGM_RSRC1_PS, 0},
-	{R_00B02C_SPI_SHADER_PGM_RSRC2_PS, 0},
-	{GROUP_FORCE_NEW_BLOCK, 0},
-	{R_00B030_SPI_SHADER_USER_DATA_PS_0, REG_FLAG_NEED_BO},
-	{R_00B034_SPI_SHADER_USER_DATA_PS_1, 0},
-	{GROUP_FORCE_NEW_BLOCK, 0},
-	{R_00B038_SPI_SHADER_USER_DATA_PS_2, REG_FLAG_NEED_BO},
-	{R_00B03C_SPI_SHADER_USER_DATA_PS_3, 0},
-	{GROUP_FORCE_NEW_BLOCK, 0},
-	{R_00B040_SPI_SHADER_USER_DATA_PS_4, REG_FLAG_NEED_BO},
-	{R_00B044_SPI_SHADER_USER_DATA_PS_5, 0},
-	{GROUP_FORCE_NEW_BLOCK, 0},
-	{R_00B048_SPI_SHADER_USER_DATA_PS_6, REG_FLAG_NEED_BO},
-	{R_00B04C_SPI_SHADER_USER_DATA_PS_7, 0},
-	{GROUP_FORCE_NEW_BLOCK, 0},
-	{R_00B050_SPI_SHADER_USER_DATA_PS_8, REG_FLAG_NEED_BO},
-	{R_00B054_SPI_SHADER_USER_DATA_PS_9, 0},
-	{GROUP_FORCE_NEW_BLOCK, 0},
-	{R_00B058_SPI_SHADER_USER_DATA_PS_10, REG_FLAG_NEED_BO},
-	{R_00B05C_SPI_SHADER_USER_DATA_PS_11, 0},
-	{GROUP_FORCE_NEW_BLOCK, 0},
-	{R_00B060_SPI_SHADER_USER_DATA_PS_12, REG_FLAG_NEED_BO},
-	{R_00B064_SPI_SHADER_USER_DATA_PS_13, 0},
-	{GROUP_FORCE_NEW_BLOCK, 0},
-	{R_00B068_SPI_SHADER_USER_DATA_PS_14, REG_FLAG_NEED_BO},
-	{R_00B06C_SPI_SHADER_USER_DATA_PS_15, 0},
-	{GROUP_FORCE_NEW_BLOCK, 0},
-	{R_00B120_SPI_SHADER_PGM_LO_VS, REG_FLAG_NEED_BO},
-	{R_00B124_SPI_SHADER_PGM_HI_VS, REG_FLAG_NEED_BO},
-	{R_00B128_SPI_SHADER_PGM_RSRC1_VS, 0},
-	{R_00B12C_SPI_SHADER_PGM_RSRC2_VS, 0},
-	{GROUP_FORCE_NEW_BLOCK, 0},
-	{R_00B130_SPI_SHADER_USER_DATA_VS_0, REG_FLAG_NEED_BO},
-	{R_00B134_SPI_SHADER_USER_DATA_VS_1, 0},
-	{GROUP_FORCE_NEW_BLOCK, 0},
-	{R_00B138_SPI_SHADER_USER_DATA_VS_2, REG_FLAG_NEED_BO},
-	{R_00B13C_SPI_SHADER_USER_DATA_VS_3, 0},
-	{GROUP_FORCE_NEW_BLOCK, 0},
-	{R_00B140_SPI_SHADER_USER_DATA_VS_4, REG_FLAG_NEED_BO},
-	{R_00B144_SPI_SHADER_USER_DATA_VS_5, 0},
-	{GROUP_FORCE_NEW_BLOCK, 0},
-	{R_00B148_SPI_SHADER_USER_DATA_VS_6, REG_FLAG_NEED_BO},
-	{R_00B14C_SPI_SHADER_USER_DATA_VS_7, 0},
-	{GROUP_FORCE_NEW_BLOCK, 0},
-	{R_00B150_SPI_SHADER_USER_DATA_VS_8, REG_FLAG_NEED_BO},
-	{R_00B154_SPI_SHADER_USER_DATA_VS_9, 0},
-	{GROUP_FORCE_NEW_BLOCK, 0},
-	{R_00B158_SPI_SHADER_USER_DATA_VS_10, REG_FLAG_NEED_BO},
-	{R_00B15C_SPI_SHADER_USER_DATA_VS_11, 0},
-	{GROUP_FORCE_NEW_BLOCK, 0},
-	{R_00B160_SPI_SHADER_USER_DATA_VS_12, REG_FLAG_NEED_BO},
-	{R_00B164_SPI_SHADER_USER_DATA_VS_13, 0},
-	{GROUP_FORCE_NEW_BLOCK, 0},
-	{R_00B168_SPI_SHADER_USER_DATA_VS_14, REG_FLAG_NEED_BO},
-	{R_00B16C_SPI_SHADER_USER_DATA_VS_15, 0},
-};
-
 int si_context_init(struct r600_context *ctx)
 {
 	int r;
 
 	LIST_INITHEAD(&ctx->active_query_list);
 
-	/* init dirty list */
-	LIST_INITHEAD(&ctx->dirty);
-	LIST_INITHEAD(&ctx->enable_list);
-
-	ctx->range = calloc(NUM_RANGES, sizeof(struct r600_range));
-	if (!ctx->range) {
-		r = -ENOMEM;
-		goto out_err;
-	}
-
-	/* add blocks */
-	r = r600_context_add_block(ctx, si_config_reg_list,
-				   Elements(si_config_reg_list), PKT3_SET_CONFIG_REG, SI_CONFIG_REG_OFFSET);
-	if (r)
-		goto out_err;
-	r = r600_context_add_block(ctx, si_context_reg_list,
-				   Elements(si_context_reg_list), PKT3_SET_CONTEXT_REG, SI_CONTEXT_REG_OFFSET);
-	if (r)
-		goto out_err;
-	r = r600_context_add_block(ctx, si_sh_reg_list,
-				   Elements(si_sh_reg_list), PKT3_SET_SH_REG, SI_SH_REG_OFFSET);
-	if (r)
-		goto out_err;
-
-
-	/* PS SAMPLER */
-	/* VS SAMPLER */
-
-	/* PS SAMPLER BORDER */
-	/* VS SAMPLER BORDER */
-
-	/* PS RESOURCES */
-	/* VS RESOURCES */
-
 	ctx->cs = ctx->ws->cs_create(ctx->ws);
 
 	r600_init_cs(ctx);
 	ctx->max_db = 8;
 	return 0;
-out_err:
-	r600_context_fini(ctx);
-	return r;
 }
 
 static inline void evergreen_context_ps_partial_flush(struct r600_context *ctx)
diff --git a/src/gallium/drivers/radeonsi/r600.h b/src/gallium/drivers/radeonsi/r600.h
index f72701e7b56..6ff0bf82cfb 100644
--- a/src/gallium/drivers/radeonsi/r600.h
+++ b/src/gallium/drivers/radeonsi/r600.h
@@ -67,64 +67,6 @@ struct r600_resource {
 };
 
 /* R600/R700 STATES */
-#define R600_GROUP_MAX			16
-#define R600_BLOCK_MAX_BO		32
-#define R600_BLOCK_MAX_REG		128
-
-/* each range covers 9 bits of dword space = 512 dwords = 2k bytes */
-/* there is a block entry for each register so 512 blocks */
-/* we have no registers to read/write below 0x8000 (0x2000 in dw space) */
-/* we use some fake offsets at 0x40000 to do evergreen sampler borders so take 0x42000 as a max bound*/
-#define RANGE_OFFSET_START 0x8000
-#define HASH_SHIFT 9
-#define NUM_RANGES (0x42000 - RANGE_OFFSET_START) / (4 << HASH_SHIFT) /* 128 << 9 = 64k */
-
-#define CTX_RANGE_ID(offset) ((((offset - RANGE_OFFSET_START) >> 2) >> HASH_SHIFT) & 255)
-#define CTX_BLOCK_ID(offset) (((offset - RANGE_OFFSET_START) >> 2) & ((1 << HASH_SHIFT) - 1))
-
-struct r600_pipe_reg {
-	uint32_t			value;
-	struct r600_block 		*block;
-	struct r600_resource		*bo;
-	enum radeon_bo_usage		bo_usage;
-	uint32_t			id;
-};
-
-struct r600_pipe_state {
-	unsigned			id;
-	unsigned			nregs;
-	struct r600_pipe_reg		regs[R600_BLOCK_MAX_REG];
-};
-
-#define R600_BLOCK_STATUS_ENABLED	(1 << 0)
-#define R600_BLOCK_STATUS_DIRTY		(1 << 1)
-
-struct r600_block_reloc {
-	struct r600_resource	*bo;
-	enum radeon_bo_usage	bo_usage;
-	unsigned		bo_pm4_index;
-};
-
-struct r600_block {
-	struct list_head	list;
-	struct list_head	enable_list;
-	unsigned		status;
-	unsigned                flags;
-	unsigned		start_offset;
-	unsigned		pm4_ndwords;
-	unsigned		nbo;
-	uint16_t 		nreg;
-	uint16_t                nreg_dirty;
-	uint32_t		*reg;
-	uint32_t		pm4[R600_BLOCK_MAX_REG];
-	unsigned		pm4_bo_index[R600_BLOCK_MAX_REG];
-	struct r600_block_reloc	reloc[R600_BLOCK_MAX_BO];
-};
-
-struct r600_range {
-	struct r600_block	**blocks;
-};
-
 struct r600_query {
 	union {
 		uint64_t			u64;
@@ -178,8 +120,6 @@ struct r600_context;
 struct r600_screen;
 
 void r600_get_backend_mask(struct r600_context *ctx);
-void r600_context_fini(struct r600_context *ctx);
-void r600_context_pipe_state_set(struct r600_context *ctx, struct r600_pipe_state *state);
 void r600_context_flush(struct r600_context *ctx, unsigned flags);
 
 struct r600_query *r600_context_query_create(struct r600_context *ctx, unsigned query_type);
@@ -195,50 +135,13 @@ void r600_query_predication(struct r600_context *ctx, struct r600_query *query,
 			    int flag_wait);
 void r600_context_emit_fence(struct r600_context *ctx, struct r600_resource *fence,
                              unsigned offset, unsigned value);
-void r600_inval_shader_cache(struct r600_context *ctx);
-void r600_inval_texture_cache(struct r600_context *ctx);
-void r600_inval_vertex_cache(struct r600_context *ctx);
-void r600_flush_framebuffer(struct r600_context *ctx, bool flush_now);
 
 void r600_context_streamout_begin(struct r600_context *ctx);
 void r600_context_streamout_end(struct r600_context *ctx);
 void r600_context_draw_opaque_count(struct r600_context *ctx, struct r600_so_target *t);
 void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw, boolean count_draw_in);
-void r600_context_block_emit_dirty(struct r600_context *ctx, struct r600_block *block);
-void r600_context_block_resource_emit_dirty(struct r600_context *ctx, struct r600_block *block);
 
 int si_context_init(struct r600_context *ctx);
 void si_context_draw(struct r600_context *ctx, const struct r600_draw *draw);
 
-void _r600_pipe_state_add_reg(struct r600_context *ctx,
-			      struct r600_pipe_state *state,
-			      uint32_t offset, uint32_t value,
-			      uint32_t range_id, uint32_t block_id,
-			      struct r600_resource *bo,
-			      enum radeon_bo_usage usage);
-
-void r600_pipe_state_add_reg_noblock(struct r600_pipe_state *state,
-				     uint32_t offset, uint32_t value,
-				     struct r600_resource *bo,
-				     enum radeon_bo_usage usage);
-
-#define r600_pipe_state_add_reg(state, offset, value, bo, usage) _r600_pipe_state_add_reg(rctx, state, offset, value, CTX_RANGE_ID(offset), CTX_BLOCK_ID(offset), bo, usage)
-
-static inline void r600_pipe_state_mod_reg(struct r600_pipe_state *state,
-					   uint32_t value)
-{
-	state->regs[state->nregs].value = value;
-	state->nregs++;
-}
-
-static inline void r600_pipe_state_mod_reg_bo(struct r600_pipe_state *state,
-					      uint32_t value, struct r600_resource *bo,
-					      enum radeon_bo_usage usage)
-{
-	state->regs[state->nregs].value = value;
-	state->regs[state->nregs].bo = bo;
-	state->regs[state->nregs].bo_usage = usage;
-	state->nregs++;
-}
-
 #endif
diff --git a/src/gallium/drivers/radeonsi/r600_hw_context.c b/src/gallium/drivers/radeonsi/r600_hw_context.c
index 858bd16fdda..664a6d08c21 100644
--- a/src/gallium/drivers/radeonsi/r600_hw_context.c
+++ b/src/gallium/drivers/radeonsi/r600_hw_context.c
@@ -140,167 +140,7 @@ void r600_init_cs(struct r600_context *ctx)
 	ctx->init_dwords = cs->cdw;
 }
 
-static void r600_init_block(struct r600_context *ctx,
-			    struct r600_block *block,
-			    const struct r600_reg *reg, int index, int nreg,
-			    unsigned opcode, unsigned offset_base)
-{
-	int i = index;
-	int j, n = nreg;
-
-	/* initialize block */
-	block->flags = 0;
-	block->status |= R600_BLOCK_STATUS_DIRTY; /* dirty all blocks at start */
-	block->start_offset = reg[i].offset;
-	block->pm4[block->pm4_ndwords++] = PKT3(opcode, n, 0);
-	block->pm4[block->pm4_ndwords++] = (block->start_offset - offset_base) >> 2;
-	block->reg = &block->pm4[block->pm4_ndwords];
-	block->pm4_ndwords += n;
-	block->nreg = n;
-	block->nreg_dirty = n;
-	LIST_INITHEAD(&block->list);
-	LIST_INITHEAD(&block->enable_list);
-
-	for (j = 0; j < n; j++) {
-		if (reg[i+j].flags & REG_FLAG_DIRTY_ALWAYS) {
-			block->flags |= REG_FLAG_DIRTY_ALWAYS;
-		}
-		if (reg[i+j].flags & REG_FLAG_ENABLE_ALWAYS) {
-			if (!(block->status & R600_BLOCK_STATUS_ENABLED)) {
-				block->status |= R600_BLOCK_STATUS_ENABLED;
-				LIST_ADDTAIL(&block->enable_list, &ctx->enable_list);
-				LIST_ADDTAIL(&block->list,&ctx->dirty);
-			}
-		}
-		if (reg[i+j].flags & REG_FLAG_FLUSH_CHANGE) {
-			block->flags |= REG_FLAG_FLUSH_CHANGE;
-		}
-
-		if (reg[i+j].flags & REG_FLAG_NEED_BO) {
-			block->nbo++;
-			assert(block->nbo < R600_BLOCK_MAX_BO);
-			block->pm4_bo_index[j] = block->nbo;
-			block->pm4[block->pm4_ndwords++] = PKT3(PKT3_NOP, 0, 0);
-			block->pm4[block->pm4_ndwords++] = 0x00000000;
-			block->reloc[block->nbo].bo_pm4_index = block->pm4_ndwords - 1;
-		}
-	}
-	/* check that we stay in limit */
-	assert(block->pm4_ndwords < R600_BLOCK_MAX_REG);
-}
-
-int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg, unsigned nreg,
-			   unsigned opcode, unsigned offset_base)
-{
-	struct r600_block *block;
-	struct r600_range *range;
-	int offset;
-
-	for (unsigned i = 0, n = 0; i < nreg; i += n) {
-		/* ignore new block balise */
-		if (reg[i].offset == GROUP_FORCE_NEW_BLOCK) {
-			n = 1;
-			continue;
-		}
-
-		/* register that need relocation are in their own group */
-		/* find number of consecutive registers */
-		n = 0;
-		offset = reg[i].offset;
-		while (reg[i + n].offset == offset) {
-			n++;
-			offset += 4;
-			if ((n + i) >= nreg)
-				break;
-			if (n >= (R600_BLOCK_MAX_REG - 2))
-				break;
-		}
-
-		/* allocate new block */
-		block = calloc(1, sizeof(struct r600_block));
-		if (block == NULL) {
-			return -ENOMEM;
-		}
-		ctx->nblocks++;
-		for (int j = 0; j < n; j++) {
-			range = &ctx->range[CTX_RANGE_ID(reg[i + j].offset)];
-			/* create block table if it doesn't exist */
-			if (!range->blocks)
-				range->blocks = calloc(1 << HASH_SHIFT, sizeof(void *));
-			if (!range->blocks)
-				return -1;
-
-			range->blocks[CTX_BLOCK_ID(reg[i + j].offset)] = block;
-		}
-
-		r600_init_block(ctx, block, reg, i, n, opcode, offset_base);
-
-	}
-	return 0;
-}
-
-
 /* initialize */
-void r600_context_fini(struct r600_context *ctx)
-{
-	struct r600_block *block;
-	struct r600_range *range;
-
-	for (int i = 0; i < NUM_RANGES; i++) {
-		if (!ctx->range[i].blocks)
-			continue;
-		for (int j = 0; j < (1 << HASH_SHIFT); j++) {
-			block = ctx->range[i].blocks[j];
-			if (block) {
-				for (int k = 0, offset = block->start_offset; k < block->nreg; k++, offset += 4) {
-					range = &ctx->range[CTX_RANGE_ID(offset)];
-					range->blocks[CTX_BLOCK_ID(offset)] = NULL;
-				}
-				for (int k = 1; k <= block->nbo; k++) {
-					pipe_resource_reference((struct pipe_resource**)&block->reloc[k].bo, NULL);
-				}
-				free(block);
-			}
-		}
-		free(ctx->range[i].blocks);
-	}
-	free(ctx->range);
-	free(ctx->blocks);
-	ctx->ws->cs_destroy(ctx->cs);
-}
-
-int r600_setup_block_table(struct r600_context *ctx)
-{
-	/* setup block table */
-	int c = 0;
-	ctx->blocks = calloc(ctx->nblocks, sizeof(void*));
-	if (!ctx->blocks)
-		return -ENOMEM;
-	for (int i = 0; i < NUM_RANGES; i++) {
-		if (!ctx->range[i].blocks)
-			continue;
-		for (int j = 0, add; j < (1 << HASH_SHIFT); j++) {
-			if (!ctx->range[i].blocks[j])
-				continue;
-
-			add = 1;
-			for (int k = 0; k < c; k++) {
-				if (ctx->blocks[k] == ctx->range[i].blocks[j]) {
-					add = 0;
-					break;
-				}
-			}
-			if (add) {
-				assert(c < ctx->nblocks);
-				ctx->blocks[c++] = ctx->range[i].blocks[j];
-				j += (ctx->range[i].blocks[j]->nreg) - 1;
-			}
-		}
-	}
-
-	return 0;
-}
-
 void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw,
 			boolean count_draw_in)
 {
@@ -344,150 +184,7 @@ void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw,
 	}
 }
 
-void r600_context_dirty_block(struct r600_context *ctx,
-			      struct r600_block *block,
-			      int dirty, int index)
-{
-	if ((index + 1) > block->nreg_dirty)
-		block->nreg_dirty = index + 1;
-
-	if ((dirty != (block->status & R600_BLOCK_STATUS_DIRTY)) || !(block->status & R600_BLOCK_STATUS_ENABLED)) {
-		block->status |= R600_BLOCK_STATUS_DIRTY;
-		ctx->pm4_dirty_cdwords += block->pm4_ndwords;
-		if (!(block->status & R600_BLOCK_STATUS_ENABLED)) {
-			block->status |= R600_BLOCK_STATUS_ENABLED;
-			LIST_ADDTAIL(&block->enable_list, &ctx->enable_list);
-		}
-		LIST_ADDTAIL(&block->list,&ctx->dirty);
-
-		if (block->flags & REG_FLAG_FLUSH_CHANGE) {
-			r600_context_ps_partial_flush(ctx);
-		}
-	}
-}
-
-void r600_context_pipe_state_set(struct r600_context *ctx, struct r600_pipe_state *state)
-{
-	struct r600_block *block;
-	int dirty;
-	for (int i = 0; i < state->nregs; i++) {
-		unsigned id, reloc_id;
-		struct r600_pipe_reg *reg = &state->regs[i];
-
-		block = reg->block;
-		id = reg->id;
-
-		dirty = block->status & R600_BLOCK_STATUS_DIRTY;
-
-		if (reg->value != block->reg[id]) {
-			block->reg[id] = reg->value;
-			dirty |= R600_BLOCK_STATUS_DIRTY;
-		}
-		if (block->flags & REG_FLAG_DIRTY_ALWAYS)
-			dirty |= R600_BLOCK_STATUS_DIRTY;
-		if (block->pm4_bo_index[id]) {
-			/* find relocation */
-			reloc_id = block->pm4_bo_index[id];
-			pipe_resource_reference((struct pipe_resource**)&block->reloc[reloc_id].bo, &reg->bo->b.b);
-			block->reloc[reloc_id].bo_usage = reg->bo_usage;
-			/* always force dirty for relocs for now */
-			dirty |= R600_BLOCK_STATUS_DIRTY;
-		}
-
-		if (dirty)
-			r600_context_dirty_block(ctx, block, dirty, id);
-	}
-}
-
-struct r600_resource *r600_context_reg_bo(struct r600_context *ctx, unsigned offset)
-{
-	struct r600_range *range;
-	struct r600_block *block;
-	unsigned id;
-
-	range = &ctx->range[CTX_RANGE_ID(offset)];
-	block = range->blocks[CTX_BLOCK_ID(offset)];
-	offset -= block->start_offset;
-	id = block->pm4_bo_index[offset >> 2];
-	if (block->reloc[id].bo) {
-		return block->reloc[id].bo;
-	}
-	return NULL;
-}
-
-void r600_context_block_emit_dirty(struct r600_context *ctx, struct r600_block *block)
-{
-	struct radeon_winsys_cs *cs = ctx->cs;
-	int optional = block->nbo == 0 && !(block->flags & REG_FLAG_DIRTY_ALWAYS);
-	int cp_dwords = block->pm4_ndwords, start_dword = 0;
-	int new_dwords = 0;
-	int nbo = block->nbo;
-
-	if (block->nreg_dirty == 0 && optional) {
-		goto out;
-	}
-
-	if (nbo) {
-		ctx->flags |= R600_CONTEXT_CHECK_EVENT_FLUSH;
-
-		for (int j = 0; j < block->nreg; j++) {
-			if (block->pm4_bo_index[j]) {
-				/* find relocation */
-				struct r600_block_reloc *reloc = &block->reloc[block->pm4_bo_index[j]];
-				block->pm4[reloc->bo_pm4_index] =
-					r600_context_bo_reloc(ctx, reloc->bo, reloc->bo_usage);
-				nbo--;
-				if (nbo == 0)
-					break;
-			}
-		}
-		ctx->flags &= ~R600_CONTEXT_CHECK_EVENT_FLUSH;
-	}
-
-	optional &= (block->nreg_dirty != block->nreg);
-	if (optional) {
-		new_dwords = block->nreg_dirty;
-		start_dword = cs->cdw;
-		cp_dwords = new_dwords + 2;
-	}
-	memcpy(&cs->buf[cs->cdw], block->pm4, cp_dwords * 4);
-	cs->cdw += cp_dwords;
-
-	if (optional) {
-		uint32_t newword;
-
-		newword = cs->buf[start_dword];
-		newword &= PKT_COUNT_C;
-		newword |= PKT_COUNT_S(new_dwords);
-		cs->buf[start_dword] = newword;
-	}
-out:
-	block->status ^= R600_BLOCK_STATUS_DIRTY;
-	block->nreg_dirty = 0;
-	LIST_DELINIT(&block->list);
-}
-
-void r600_inval_shader_cache(struct r600_context *ctx)
-{
-	ctx->atom_surface_sync.flush_flags |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
-	ctx->atom_surface_sync.flush_flags |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
-	r600_atom_dirty(ctx, &ctx->atom_surface_sync.atom);
-}
-
-void r600_inval_texture_cache(struct r600_context *ctx)
-{
-	ctx->atom_surface_sync.flush_flags |= S_0085F0_TC_ACTION_ENA(1);
-	r600_atom_dirty(ctx, &ctx->atom_surface_sync.atom);
-}
-
-void r600_inval_vertex_cache(struct r600_context *ctx)
-{
-	/* Some GPUs don't have the vertex cache and must use the texture cache instead. */
-	ctx->atom_surface_sync.flush_flags |= S_0085F0_TC_ACTION_ENA(1);
-	r600_atom_dirty(ctx, &ctx->atom_surface_sync.atom);
-}
-
-void r600_flush_framebuffer(struct r600_context *ctx, bool flush_now)
+static void r600_flush_framebuffer(struct r600_context *ctx, bool flush_now)
 {
 	if (!(ctx->flags & R600_CONTEXT_DST_CACHES_DIRTY))
 		return;
@@ -556,14 +253,6 @@ void r600_context_flush(struct r600_context *ctx, unsigned flags)
 	/* set all valid group as dirty so they get reemited on
 	 * next draw command
 	 */
-	LIST_FOR_EACH_ENTRY(enable_block, &ctx->enable_list, enable_list) {
-		if(!(enable_block->status & R600_BLOCK_STATUS_DIRTY)) {
-			LIST_ADDTAIL(&enable_block->list,&ctx->dirty);
-			enable_block->status |= R600_BLOCK_STATUS_DIRTY;
-		}
-		ctx->pm4_dirty_cdwords += enable_block->pm4_ndwords;
-		enable_block->nreg_dirty = enable_block->nreg;
-	}
 	si_pm4_reset_emitted(ctx);
 }
 
diff --git a/src/gallium/drivers/radeonsi/r600_hw_context_priv.h b/src/gallium/drivers/radeonsi/r600_hw_context_priv.h
index f5ad4abceeb..01dddb65437 100644
--- a/src/gallium/drivers/radeonsi/r600_hw_context_priv.h
+++ b/src/gallium/drivers/radeonsi/r600_hw_context_priv.h
@@ -35,28 +35,9 @@
 #define PKT_COUNT_C                     0xC000FFFF
 #define PKT_COUNT_S(x)                  (((x) & 0x3FFF) << 16)
 
-/* these flags are used in register flags and added into block flags */
-#define REG_FLAG_NEED_BO 1
-#define REG_FLAG_DIRTY_ALWAYS 2
-#define REG_FLAG_RV6XX_SBU 4
-#define REG_FLAG_NOT_R600 8
-#define REG_FLAG_ENABLE_ALWAYS 16
-#define REG_FLAG_FLUSH_CHANGE 64
-
-struct r600_reg {
-	unsigned			offset;
-	unsigned			flags;
-};
-
 /*
  * r600_hw_context.c
  */
-struct r600_resource *r600_context_reg_bo(struct r600_context *ctx, unsigned offset);
-int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg, unsigned nreg,
-			   unsigned opcode, unsigned offset_base);
-void r600_context_dirty_block(struct r600_context *ctx, struct r600_block *block,
-			      int dirty, int index);
-int r600_setup_block_table(struct r600_context *ctx);
 void r600_init_cs(struct r600_context *ctx);
 
 /*
diff --git a/src/gallium/drivers/radeonsi/r600_state_common.c b/src/gallium/drivers/radeonsi/r600_state_common.c
index 04a592f29ed..ea12914931d 100644
--- a/src/gallium/drivers/radeonsi/r600_state_common.c
+++ b/src/gallium/drivers/radeonsi/r600_state_common.c
@@ -83,45 +83,3 @@ unsigned r600_get_cb_flush_flags(struct r600_context *rctx)
 
 	return flags;
 }
-
-void _r600_pipe_state_add_reg(struct r600_context *ctx,
-			      struct r600_pipe_state *state,
-			      uint32_t offset, uint32_t value,
-			      uint32_t range_id, uint32_t block_id,
-			      struct r600_resource *bo,
-			      enum radeon_bo_usage usage)
-{
-	struct r600_range *range;
-	struct r600_block *block;
-
-	if (bo) assert(usage);
-
-	range = &ctx->range[range_id];
-	block = range->blocks[block_id];
-	state->regs[state->nregs].block = block;
-	state->regs[state->nregs].id = (offset - block->start_offset) >> 2;
-
-	state->regs[state->nregs].value = value;
-	state->regs[state->nregs].bo = bo;
-	state->regs[state->nregs].bo_usage = usage;
-
-	state->nregs++;
-	assert(state->nregs < R600_BLOCK_MAX_REG);
-}
-
-void r600_pipe_state_add_reg_noblock(struct r600_pipe_state *state,
-				     uint32_t offset, uint32_t value,
-				     struct r600_resource *bo,
-				     enum radeon_bo_usage usage)
-{
-	if (bo) assert(usage);
-
-	state->regs[state->nregs].id = offset;
-	state->regs[state->nregs].block = NULL;
-	state->regs[state->nregs].value = value;
-	state->regs[state->nregs].bo = bo;
-	state->regs[state->nregs].bo_usage = usage;
-
-	state->nregs++;
-	assert(state->nregs < R600_BLOCK_MAX_REG);
-}
diff --git a/src/gallium/drivers/radeonsi/radeonsi_pipe.c b/src/gallium/drivers/radeonsi/radeonsi_pipe.c
index d3547467ef9..2558f947f84 100644
--- a/src/gallium/drivers/radeonsi/radeonsi_pipe.c
+++ b/src/gallium/drivers/radeonsi/radeonsi_pipe.c
@@ -175,14 +175,8 @@ static void r600_destroy_context(struct pipe_context *context)
 	rctx->context.delete_depth_stencil_alpha_state(&rctx->context, rctx->custom_dsa_flush);
 	util_unreference_framebuffer_state(&rctx->framebuffer);
 
-	r600_context_fini(rctx);
-
 	util_blitter_destroy(rctx->blitter);
 
-	for (int i = 0; i < R600_PIPE_NSTATES; i++) {
-		free(rctx->states[i]);
-	}
-
 	if (rctx->uploader) {
 		u_upload_destroy(rctx->uploader);
 	}
diff --git a/src/gallium/drivers/radeonsi/radeonsi_pipe.h b/src/gallium/drivers/radeonsi/radeonsi_pipe.h
index ff68b50fe81..f67c33364f2 100644
--- a/src/gallium/drivers/radeonsi/radeonsi_pipe.h
+++ b/src/gallium/drivers/radeonsi/radeonsi_pipe.h
@@ -74,17 +74,6 @@ struct r600_atom_surface_sync {
 	unsigned flush_flags; /* CP_COHER_CNTL */
 };
 
-enum r600_pipe_state_id {
-	R600_PIPE_STATE_CONFIG,
-	R600_PIPE_STATE_SEAMLESS_CUBEMAP,
-	R600_PIPE_STATE_PS_SHADER,
-	R600_PIPE_STATE_VS_SHADER,
-	R600_PIPE_STATE_CONSTANT,
-	R600_PIPE_STATE_SAMPLER,
-	R600_PIPE_STATE_RESOURCE,
-	R600_PIPE_NSTATES
-};
-
 struct r600_pipe_fences {
 	struct r600_resource		*bo;
 	unsigned			*data;
@@ -153,7 +142,6 @@ struct r600_context {
 	void				*custom_dsa_flush;
 	struct r600_screen		*screen;
 	struct radeon_winsys		*ws;
-	struct r600_pipe_state		*states[R600_PIPE_NSTATES];
 	struct si_vertex_element	*vertex_elements;
 	struct pipe_framebuffer_state	framebuffer;
 	unsigned			pa_sc_line_stipple;
@@ -162,7 +150,6 @@ struct r600_context {
 	unsigned			pa_cl_vs_out_cntl;
 	/* for saving when using blitter */
 	struct pipe_stencil_ref		stencil_ref;
-	struct r600_pipe_state		config;
 	struct si_pipe_shader		*ps_shader;
 	struct si_pipe_shader		*vs_shader;
 	struct pipe_query		*current_render_cond;
@@ -193,13 +180,7 @@ struct r600_context {
 	 */
 	struct radeon_winsys_cs	*cs;
 
-	struct r600_range	*range;
-	unsigned		nblocks;
-	struct r600_block	**blocks;
-	struct list_head	dirty;
-	struct list_head	enable_list;
 	unsigned		pm4_dirty_cdwords;
-	unsigned		ctx_pm4_ndwords;
 	unsigned		init_dwords;
 
 	/* The list of active queries. Only one query of each type can be active. */
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
index 211956ef787..1648cce40a9 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -479,7 +479,6 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
 	struct pipe_draw_info info = *dinfo;
 	struct r600_draw rdraw = {};
 	struct pipe_index_buffer ib = {};
-	struct r600_block *dirty_block = NULL, *next_block = NULL;
 	struct r600_atom *state = NULL, *next_state = NULL;
 
 	if ((!info.count && (info.indexed || !info.count_from_stream_output)) ||
@@ -546,9 +545,6 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
 	LIST_FOR_EACH_ENTRY_SAFE(state, next_state, &rctx->dirty_states, head) {
 		r600_emit_atom(rctx, state);
 	}
-	LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &rctx->dirty,list) {
-		r600_context_block_emit_dirty(rctx, dirty_block);
-	}
 	si_pm4_emit_dirty(rctx);
 	rctx->pm4_dirty_cdwords = 0;