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authorTom Stellard <[email protected]>2012-02-28 17:32:28 -0500
committerTom Stellard <[email protected]>2012-04-23 09:34:04 -0400
commitfa52aeb3964e38b8e7b9e34c427fa1b5a42f358f (patch)
treeb2bbf800315283c730d5ffa58e4fe454861c4fe8 /src/gallium/drivers
parentced73ea5df306156e5383b438d6858e58b1479e5 (diff)
r600/llvm: Add LOAD_VTX instruction
Diffstat (limited to 'src/gallium/drivers')
-rw-r--r--src/gallium/drivers/radeon/R600Instructions.td13
1 files changed, 13 insertions, 0 deletions
diff --git a/src/gallium/drivers/radeon/R600Instructions.td b/src/gallium/drivers/radeon/R600Instructions.td
index 913e27f1f9c..af6b8be5190 100644
--- a/src/gallium/drivers/radeon/R600Instructions.td
+++ b/src/gallium/drivers/radeon/R600Instructions.td
@@ -918,6 +918,19 @@ def LOCAL_SIZE_Z : R600PreloadInst <"LOCAL_SIZE_Z",
+let isPseudo = 1 in {
+
+def LOAD_VTX : AMDGPUShaderInst <
+ (outs R600_Reg32:$dst),
+ (ins MEMri:$mem),
+ "LOAD_VTX",
+ [(set (i32 R600_Reg32:$dst), (load_param ADDRParam:$mem))]
+>;
+
+
+} //End isPseudo
+
+
include "R600ShaderPatterns.td"
// We need this pattern to avoid having real registers in PHI nodes.