diff options
author | Chia-I Wu <[email protected]> | 2014-03-02 13:36:08 +0800 |
---|---|---|
committer | Chia-I Wu <[email protected]> | 2014-03-10 16:43:53 +0800 |
commit | 8fc2f0c874929a391c0369c8a12839caf786dfc6 (patch) | |
tree | 8fc781fa17ae0bce62a64aa9f4443f0041264fe5 /src/gallium/drivers | |
parent | d8b2e3c25eca4e1cc96b004216f433cbfd73e5f7 (diff) |
ilo: add ILO_3D_PIPELINE_WRITE_STATISTICS
The command writes statistics registers to the specified bo.
Diffstat (limited to 'src/gallium/drivers')
-rw-r--r-- | src/gallium/drivers/ilo/ilo_3d_pipeline.c | 11 | ||||
-rw-r--r-- | src/gallium/drivers/ilo/ilo_3d_pipeline.h | 8 | ||||
-rw-r--r-- | src/gallium/drivers/ilo/ilo_3d_pipeline_gen6.c | 53 | ||||
-rw-r--r-- | src/gallium/drivers/ilo/ilo_3d_pipeline_gen6.h | 4 | ||||
-rw-r--r-- | src/gallium/drivers/ilo/ilo_3d_pipeline_gen7.c | 14 |
5 files changed, 90 insertions, 0 deletions
diff --git a/src/gallium/drivers/ilo/ilo_3d_pipeline.c b/src/gallium/drivers/ilo/ilo_3d_pipeline.c index a821282e4fe..e5f82d0a580 100644 --- a/src/gallium/drivers/ilo/ilo_3d_pipeline.c +++ b/src/gallium/drivers/ilo/ilo_3d_pipeline.c @@ -257,6 +257,17 @@ ilo_3d_pipeline_emit_write_depth_count(struct ilo_3d_pipeline *p, p->emit_write_depth_count(p, bo, index); } +/** + * Emit MI_STORE_REGISTER_MEM to store statistics registers. + */ +void +ilo_3d_pipeline_emit_write_statistics(struct ilo_3d_pipeline *p, + struct intel_bo *bo, int index) +{ + handle_invalid_batch_bo(p, true); + p->emit_write_statistics(p, bo, index); +} + void ilo_3d_pipeline_emit_rectlist(struct ilo_3d_pipeline *p, const struct ilo_blitter *blitter) diff --git a/src/gallium/drivers/ilo/ilo_3d_pipeline.h b/src/gallium/drivers/ilo/ilo_3d_pipeline.h index 0574d7479e6..90c626e5274 100644 --- a/src/gallium/drivers/ilo/ilo_3d_pipeline.h +++ b/src/gallium/drivers/ilo/ilo_3d_pipeline.h @@ -50,6 +50,7 @@ enum ilo_3d_pipeline_action { ILO_3D_PIPELINE_FLUSH, ILO_3D_PIPELINE_WRITE_TIMESTAMP, ILO_3D_PIPELINE_WRITE_DEPTH_COUNT, + ILO_3D_PIPELINE_WRITE_STATISTICS, ILO_3D_PIPELINE_RECTLIST, }; @@ -83,6 +84,9 @@ struct ilo_3d_pipeline { void (*emit_write_depth_count)(struct ilo_3d_pipeline *pipeline, struct intel_bo *bo, int index); + void (*emit_write_statistics)(struct ilo_3d_pipeline *pipeline, + struct intel_bo *bo, int index); + void (*emit_rectlist)(struct ilo_3d_pipeline *pipeline, const struct ilo_blitter *blitter); @@ -177,6 +181,10 @@ ilo_3d_pipeline_emit_write_depth_count(struct ilo_3d_pipeline *p, struct intel_bo *bo, int index); void +ilo_3d_pipeline_emit_write_statistics(struct ilo_3d_pipeline *p, + struct intel_bo *bo, int index); + +void ilo_3d_pipeline_emit_rectlist(struct ilo_3d_pipeline *p, const struct ilo_blitter *blitter); diff --git a/src/gallium/drivers/ilo/ilo_3d_pipeline_gen6.c b/src/gallium/drivers/ilo/ilo_3d_pipeline_gen6.c index 2cfde297a9a..6cc5e039c8d 100644 --- a/src/gallium/drivers/ilo/ilo_3d_pipeline_gen6.c +++ b/src/gallium/drivers/ilo/ilo_3d_pipeline_gen6.c @@ -1524,6 +1524,45 @@ ilo_3d_pipeline_emit_write_depth_count_gen6(struct ilo_3d_pipeline *p, true, p->cp); } +void +ilo_3d_pipeline_emit_write_statistics_gen6(struct ilo_3d_pipeline *p, + struct intel_bo *bo, int index) +{ + uint32_t regs[] = { + IA_VERTICES_COUNT, + IA_PRIMITIVES_COUNT, + VS_INVOCATION_COUNT, + GS_INVOCATION_COUNT, + GS_PRIMITIVES_COUNT, + CL_INVOCATION_COUNT, + CL_PRIMITIVES_COUNT, + PS_INVOCATION_COUNT, + p->dev->gen >= ILO_GEN(7) ? HS_INVOCATION_COUNT : 0, + p->dev->gen >= ILO_GEN(7) ? DS_INVOCATION_COUNT : 0, + 0, + }; + int i; + + p->emit_flush(p); + + for (i = 0; i < Elements(regs); i++) { + const uint32_t bo_offset = (index + i) * sizeof(uint64_t); + + if (regs[i]) { + /* store lower 32 bits */ + gen6_emit_MI_STORE_REGISTER_MEM(p->dev, + bo, bo_offset, regs[i], p->cp); + /* store higher 32 bits */ + gen6_emit_MI_STORE_REGISTER_MEM(p->dev, + bo, bo_offset + 4, regs[i] + 4, p->cp); + } + else { + gen6_emit_MI_STORE_DATA_IMM(p->dev, + bo, bo_offset, 0, true, p->cp); + } + } +} + static void gen6_rectlist_vs_to_sf(struct ilo_3d_pipeline *p, const struct ilo_blitter *blitter, @@ -1883,6 +1922,19 @@ ilo_3d_pipeline_estimate_size_gen6(struct ilo_3d_pipeline *p, size = ilo_gpe_gen6_estimate_command_size(p->dev, ILO_GPE_GEN6_PIPE_CONTROL, 1) * 3; break; + case ILO_3D_PIPELINE_WRITE_STATISTICS: + { + const int num_regs = 8; + const int num_pads = 3; + + size = ilo_gpe_gen6_estimate_command_size(p->dev, + ILO_GPE_GEN6_PIPE_CONTROL, 1); + size += ilo_gpe_gen6_estimate_command_size(p->dev, + ILO_GPE_GEN6_MI_STORE_REGISTER_MEM, 1) * 2 * num_regs; + size += ilo_gpe_gen6_estimate_command_size(p->dev, + ILO_GPE_GEN6_MI_STORE_DATA_IMM, 1) * num_pads; + } + break; case ILO_3D_PIPELINE_RECTLIST: size = 64 + 256; /* states + commands */ break; @@ -1903,5 +1955,6 @@ ilo_3d_pipeline_init_gen6(struct ilo_3d_pipeline *p) p->emit_flush = ilo_3d_pipeline_emit_flush_gen6; p->emit_write_timestamp = ilo_3d_pipeline_emit_write_timestamp_gen6; p->emit_write_depth_count = ilo_3d_pipeline_emit_write_depth_count_gen6; + p->emit_write_statistics = ilo_3d_pipeline_emit_write_statistics_gen6; p->emit_rectlist = ilo_3d_pipeline_emit_rectlist_gen6; } diff --git a/src/gallium/drivers/ilo/ilo_3d_pipeline_gen6.h b/src/gallium/drivers/ilo/ilo_3d_pipeline_gen6.h index c6f48ebbe7c..7e375919eed 100644 --- a/src/gallium/drivers/ilo/ilo_3d_pipeline_gen6.h +++ b/src/gallium/drivers/ilo/ilo_3d_pipeline_gen6.h @@ -161,6 +161,10 @@ ilo_3d_pipeline_emit_write_depth_count_gen6(struct ilo_3d_pipeline *p, struct intel_bo *bo, int index); void +ilo_3d_pipeline_emit_write_statistics_gen6(struct ilo_3d_pipeline *p, + struct intel_bo *bo, int index); + +void ilo_3d_pipeline_init_gen6(struct ilo_3d_pipeline *p); #endif /* ILO_3D_PIPELINE_GEN6_H */ diff --git a/src/gallium/drivers/ilo/ilo_3d_pipeline_gen7.c b/src/gallium/drivers/ilo/ilo_3d_pipeline_gen7.c index 953e3e32b54..5ed8b7e1e6a 100644 --- a/src/gallium/drivers/ilo/ilo_3d_pipeline_gen7.c +++ b/src/gallium/drivers/ilo/ilo_3d_pipeline_gen7.c @@ -1039,6 +1039,19 @@ ilo_3d_pipeline_estimate_size_gen7(struct ilo_3d_pipeline *p, size = ilo_gpe_gen7_estimate_command_size(p->dev, ILO_GPE_GEN7_PIPE_CONTROL, 1); break; + case ILO_3D_PIPELINE_WRITE_STATISTICS: + { + const int num_regs = 10; + const int num_pads = 1; + + size = ilo_gpe_gen7_estimate_command_size(p->dev, + ILO_GPE_GEN7_PIPE_CONTROL, 1); + size += ilo_gpe_gen7_estimate_command_size(p->dev, + ILO_GPE_GEN7_MI_STORE_REGISTER_MEM, 1) * 2 * num_regs; + size += ilo_gpe_gen7_estimate_command_size(p->dev, + ILO_GPE_GEN7_MI_STORE_DATA_IMM, 1) * num_pads; + } + break; case ILO_3D_PIPELINE_RECTLIST: size = 64 + 256; /* states + commands */ break; @@ -1059,5 +1072,6 @@ ilo_3d_pipeline_init_gen7(struct ilo_3d_pipeline *p) p->emit_flush = ilo_3d_pipeline_emit_flush_gen6; p->emit_write_timestamp = ilo_3d_pipeline_emit_write_timestamp_gen6; p->emit_write_depth_count = ilo_3d_pipeline_emit_write_depth_count_gen6; + p->emit_write_statistics = ilo_3d_pipeline_emit_write_statistics_gen6; p->emit_rectlist = ilo_3d_pipeline_emit_rectlist_gen7; } |