diff options
author | Marek Olšák <[email protected]> | 2015-03-15 20:13:52 +0100 |
---|---|---|
committer | Marek Olšák <[email protected]> | 2015-03-16 12:54:19 +0100 |
commit | dc394136404eafec689874934db0198be6182c59 (patch) | |
tree | e3630c59a281f384694c94025da44a0ea2cc86c6 /src/gallium/drivers | |
parent | 567c8d73008a672cb71a84a4724829d34e1652b2 (diff) |
radeonsi: move scratch reloc state setup
- move it to its own function
- do it after all states are emitted
- bump SI_MAX_DRAW_CS_DWORDS
Reviewed-by: Michel Dänzer <[email protected]>
Diffstat (limited to 'src/gallium/drivers')
-rw-r--r-- | src/gallium/drivers/radeonsi/si_pipe.h | 3 | ||||
-rw-r--r-- | src/gallium/drivers/radeonsi/si_state_draw.c | 34 |
2 files changed, 22 insertions, 15 deletions
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h index 29f01f35d38..422b873db04 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.h +++ b/src/gallium/drivers/radeonsi/si_pipe.h @@ -47,7 +47,8 @@ #define SI_TRACE_CS_DWORDS 6 #define SI_MAX_DRAW_CS_DWORDS \ - (/*derived prim state:*/ 3 + /*draw regs:*/ 16 + /*draw packets:*/ 31) + (/*scratch:*/ 3 + /*derived prim state:*/ 3 + \ + /*draw regs:*/ 16 + /*draw packets:*/ 31) /* Instruction cache. */ #define SI_CONTEXT_INV_ICACHE (R600_CONTEXT_PRIVATE_FLAG << 0) diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c index e186694c5c3..2e77d85a80d 100644 --- a/src/gallium/drivers/radeonsi/si_state_draw.c +++ b/src/gallium/drivers/radeonsi/si_state_draw.c @@ -149,6 +149,25 @@ static unsigned si_get_ia_multi_vgt_param(struct si_context *sctx, S_028AA8_WD_SWITCH_ON_EOP(sctx->b.chip_class >= CIK ? wd_switch_on_eop : 0); } +static void si_emit_scratch_reloc(struct si_context *sctx) +{ + struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs; + + if (!sctx->emit_scratch_reloc) + return; + + r600_write_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE, + sctx->spi_tmpring_size); + + if (sctx->scratch_buffer) { + r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, + sctx->scratch_buffer, RADEON_USAGE_READWRITE, + RADEON_PRIO_SHADER_RESOURCE_RW); + + } + sctx->emit_scratch_reloc = false; +} + /* rast_prim is the primitive type after GS. */ static void si_emit_rasterizer_prim_state(struct si_context *sctx) { @@ -575,20 +594,6 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info) if (sctx->b.flags) sctx->atoms.s.cache_flush->dirty = true; - if (sctx->emit_scratch_reloc) { - struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs; - r600_write_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE, - sctx->spi_tmpring_size); - - if (sctx->scratch_buffer) { - r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, - sctx->scratch_buffer, RADEON_USAGE_READWRITE, - RADEON_PRIO_SHADER_RESOURCE_RW); - - } - sctx->emit_scratch_reloc = false; - } - si_need_cs_space(sctx, 0, TRUE); /* Emit states. */ @@ -600,6 +605,7 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info) } si_pm4_emit_dirty(sctx); + si_emit_scratch_reloc(sctx); si_emit_rasterizer_prim_state(sctx); si_emit_draw_registers(sctx, info); si_emit_draw_packets(sctx, info, &ib); |