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authorBen Skeggs <[email protected]>2020-06-07 09:52:37 +1000
committerMarge Bot <[email protected]>2020-06-10 22:52:42 +0000
commit7458e21e2b9ba4395bf16a1b03e04380438424a5 (patch)
tree626f5d9469de10c4b317c67fbd82d4d3a8e44422 /src/gallium/drivers
parent78103abe8784e788c7d04b807bc47527b504121e (diff)
nvir/gv100: enable support for tu1xx
SM75 has a bunch more stuff, but is otherwise backwards-compatible with SM70 SASS. Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Karol Herbst <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5377>
Diffstat (limited to 'src/gallium/drivers')
-rw-r--r--src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp2
-rw-r--r--src/gallium/drivers/nouveau/codegen/nv50_ir_target.cpp1
2 files changed, 3 insertions, 0 deletions
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp
index 272c591ff0a..4e5b21d9176 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp
@@ -989,6 +989,7 @@ GCRA::coalesce(ArrayList& insns)
case 0x120:
case 0x130:
case 0x140:
+ case 0x160:
ret = doCoalesce(insns, JOIN_MASK_UNION);
break;
default:
@@ -2499,6 +2500,7 @@ RegAlloc::InsertConstraintsPass::visit(BasicBlock *bb)
case 0x120:
case 0x130:
case 0x140:
+ case 0x160:
texConstraintGM107(tex);
break;
default:
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_target.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_target.cpp
index 06154a90b07..765375a47df 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_target.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_target.cpp
@@ -154,6 +154,7 @@ Target *Target::create(unsigned int chipset)
STATIC_ASSERT(ARRAY_SIZE(operationSrcNr) == OP_LAST + 1);
STATIC_ASSERT(ARRAY_SIZE(operationClass) == OP_LAST + 1);
switch (chipset & ~0xf) {
+ case 0x160:
case 0x140:
return getTargetGV100(chipset);
case 0x110: