r600g: move CB_SHADER_MASK setup into cb_misc_state

Reviewed-by: Alex Deucher <[email protected]>

6 files changed, 32 insertions, 28 deletions

diff --git a/src/gallium/drivers/r600/evergreen_hw_context.c b/src/gallium/drivers/r600/evergreen_hw_context.c
index dcbe0a47919..53d45824136 100644
--- a/src/gallium/drivers/r600/evergreen_hw_context.c
+++ b/src/gallium/drivers/r600/evergreen_hw_context.c
@@ -66,7 +66,6 @@ static const struct r600_reg evergreen_context_reg_list[] = {
 	{R_028204_PA_SC_WINDOW_SCISSOR_TL, 0, 0},
 	{R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0},
 	{R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0, 0},
-	{R_02823C_CB_SHADER_MASK, 0, 0},
 	{R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0},
 	{R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0},
 	{R_028350_SX_MISC, 0, 0},
@@ -325,7 +324,6 @@ static const struct r600_reg cayman_context_reg_list[] = {
 	{R_028204_PA_SC_WINDOW_SCISSOR_TL, 0, 0},
 	{R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0},
 	{R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0, 0},
-	{R_02823C_CB_SHADER_MASK, 0, 0},
 	{R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0},
 	{R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0},
 	{R_028350_SX_MISC, 0, 0},
diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c
index 61efa287bab..bc8f41298d6 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -1709,11 +1709,6 @@ static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
 		evergreen_db(rctx, rstate, state);
 	}
 
-	rctx->fb_cb_shader_mask = 0;
-	for (int i = 0; i < state->nr_cbufs; i++) {
-		rctx->fb_cb_shader_mask |= 0xf << (i * 4);
-	}
-
 	evergreen_get_scissor_rect(rctx, 0, 0, state->width, state->height, &tl, &br);
 
 	r600_pipe_state_add_reg(rstate,
@@ -1740,9 +1735,11 @@ static void evergreen_emit_cb_misc_state(struct r600_context *rctx, struct r600_
 	struct radeon_winsys_cs *cs = rctx->cs;
 	struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
 	unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
+	unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
 
-	r600_write_context_reg(cs, R_028238_CB_TARGET_MASK,
-			       a->blend_colormask & fb_colormask);
+	r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
+	r600_write_value(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */
+	r600_write_value(cs, (a->dual_src_blend ? ps_colormask : 0) | fb_colormask); /* R_02823C_CB_SHADER_MASK */
 }
 
 static void evergreen_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
@@ -2702,7 +2699,7 @@ void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader
 		/* always at least export 1 component per pixel */
 		exports_ps = 2;
 	}
-	shader->ps_cb_shader_mask = (1ULL << ((unsigned)num_cout * 4)) - 1;
+	shader->nr_ps_color_outputs = num_cout;
 	if (ninterp == 0) {
 		ninterp = 1;
 		have_perspective = TRUE;
diff --git a/src/gallium/drivers/r600/r600_hw_context.c b/src/gallium/drivers/r600/r600_hw_context.c
index a89019de506..b23606913a7 100644
--- a/src/gallium/drivers/r600/r600_hw_context.c
+++ b/src/gallium/drivers/r600/r600_hw_context.c
@@ -335,7 +335,6 @@ static const struct r600_reg r600_context_reg_list[] = {
 	{R_028124_CB_CLEAR_GREEN, 0, 0},
 	{R_028128_CB_CLEAR_BLUE, 0, 0},
 	{R_02812C_CB_CLEAR_ALPHA, 0, 0},
-	{R_02823C_CB_SHADER_MASK, 0, 0},
 	{R_028410_SX_ALPHA_TEST_CONTROL, 0, 0},
 	{R_028414_CB_BLEND_RED, 0, 0},
 	{R_028418_CB_BLEND_GREEN, 0, 0},
diff --git a/src/gallium/drivers/r600/r600_pipe.h b/src/gallium/drivers/r600/r600_pipe.h
index d2ae314b980..608cb101241 100644
--- a/src/gallium/drivers/r600/r600_pipe.h
+++ b/src/gallium/drivers/r600/r600_pipe.h
@@ -87,7 +87,9 @@ struct r600_cb_misc_state {
 	unsigned cb_color_control; /* this comes from blend state */
 	unsigned blend_colormask; /* 8*4 bits for 8 RGBA colorbuffers */
 	unsigned nr_cbufs;
+	unsigned nr_ps_color_outputs;
 	bool multiwrite;
+	bool dual_src_blend;
 };
 
 enum r600_pipe_state_id {
@@ -220,7 +222,7 @@ struct r600_pipe_shader {
 	unsigned	sprite_coord_enable;
 	unsigned	flatshade;
 	unsigned	pa_cl_vs_out_cntl;
-	unsigned	ps_cb_shader_mask;
+	unsigned	nr_ps_color_outputs;
 	unsigned	key;
 	unsigned		db_shader_control;
 	unsigned		ps_depth_export;
@@ -288,10 +290,8 @@ struct r600_context {
 	struct r600_pipe_state		*states[R600_PIPE_NSTATES];
 	struct r600_vertex_element	*vertex_elements;
 	struct pipe_framebuffer_state	framebuffer;
-	unsigned			fb_cb_shader_mask;
 	unsigned			compute_cb_target_mask;
 	unsigned			sx_alpha_test_control;
-	unsigned			cb_shader_mask;
 	unsigned			db_shader_control;
 	unsigned			pa_sc_line_stipple;
 	unsigned			pa_cl_clip_cntl;
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index 9e8880fafc6..9bbb63fc2ae 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -1668,10 +1668,8 @@ static void r600_set_framebuffer_state(struct pipe_context *ctx,
 	}
 
 	shader_control = 0;
-	rctx->fb_cb_shader_mask = 0;
 	for (int i = 0; i < state->nr_cbufs; i++) {
 		shader_control |= 1 << i;
-		rctx->fb_cb_shader_mask |= 0xf << (i * 4);
 	}
 	tl = S_028240_TL_X(0) | S_028240_TL_Y(0) | S_028240_WINDOW_OFFSET_DISABLE(1);
 	br = S_028244_BR_X(state->width) | S_028244_BR_Y(state->height);
@@ -1703,10 +1701,12 @@ static void r600_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom
 	struct radeon_winsys_cs *cs = rctx->cs;
 	struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
 	unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
+	unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
 	unsigned multiwrite = a->multiwrite && a->nr_cbufs > 1;
 
-	r600_write_context_reg(cs, R_028238_CB_TARGET_MASK,
-			       a->blend_colormask & fb_colormask);
+	r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
+	r600_write_value(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */
+	r600_write_value(cs, (a->dual_src_blend ? ps_colormask : 0) | fb_colormask); /* R_02823C_CB_SHADER_MASK */
 	r600_write_context_reg(cs, R_028808_CB_COLOR_CONTROL,
 			       a->cb_color_control |
 			       S_028808_MULTIWRITE_ENABLE(multiwrite));
@@ -2337,7 +2337,7 @@ void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shad
 		exports_ps = 2;
 	}
 
-	shader->ps_cb_shader_mask = (1ULL << ((unsigned)num_cout * 4)) - 1;
+	shader->nr_ps_color_outputs = num_cout;
 
 	spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
 				S_0286CC_PERSP_GRADIENT_ENA(1)|
diff --git a/src/gallium/drivers/r600/r600_state_common.c b/src/gallium/drivers/r600/r600_state_common.c
index cbaaa55a9a6..178ddcc34ac 100644
--- a/src/gallium/drivers/r600/r600_state_common.c
+++ b/src/gallium/drivers/r600/r600_state_common.c
@@ -152,6 +152,7 @@ void r600_bind_blend_state(struct pipe_context *ctx, void *state)
 	struct r600_context *rctx = (struct r600_context *)ctx;
 	struct r600_pipe_blend *blend = (struct r600_pipe_blend *)state;
 	struct r600_pipe_state *rstate;
+	bool update_cb = false;
 
 	if (state == NULL)
 		return;
@@ -162,11 +163,18 @@ void r600_bind_blend_state(struct pipe_context *ctx, void *state)
 
 	if (rctx->cb_misc_state.blend_colormask != blend->cb_target_mask) {
 		rctx->cb_misc_state.blend_colormask = blend->cb_target_mask;
-		r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
+		update_cb = true;
 	}
 	if (rctx->chip_class <= R700 &&
 	    rctx->cb_misc_state.cb_color_control != blend->cb_color_control) {
 		rctx->cb_misc_state.cb_color_control = blend->cb_color_control;
+		update_cb = true;
+	}
+	if (rctx->cb_misc_state.dual_src_blend != blend->dual_src_blend) {
+		rctx->cb_misc_state.dual_src_blend = blend->dual_src_blend;
+		update_cb = true;
+	}
+	if (update_cb) {
 		r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
 	}
 }
@@ -522,6 +530,11 @@ static int r600_shader_select(struct pipe_context *ctx,
 		r600_adjust_gprs(rctx);
 	}
 
+	if (rctx->ps_shader &&
+	    rctx->cb_misc_state.nr_ps_color_outputs != rctx->ps_shader->current->nr_ps_color_outputs) {
+		rctx->cb_misc_state.nr_ps_color_outputs = rctx->ps_shader->current->nr_ps_color_outputs;
+		r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
+	}
 	return 0;
 }
 
@@ -576,6 +589,11 @@ void r600_bind_ps_shader(struct pipe_context *ctx, void *state)
 		if (rctx->vs_shader)
 			r600_adjust_gprs(rctx);
 	}
+
+	if (rctx->cb_misc_state.nr_ps_color_outputs != rctx->ps_shader->current->nr_ps_color_outputs) {
+		rctx->cb_misc_state.nr_ps_color_outputs = rctx->ps_shader->current->nr_ps_color_outputs;
+		r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
+	}
 }
 
 void r600_bind_vs_shader(struct pipe_context *ctx, void *state)
@@ -825,12 +843,6 @@ static void r600_update_derived_state(struct r600_context *rctx)
 	} else {
 		r600_update_dual_export_state(rctx);
 	}
-
-	if (rctx->dual_src_blend) {
-		rctx->cb_shader_mask = rctx->ps_shader->current->ps_cb_shader_mask | rctx->fb_cb_shader_mask;
-	} else {
-		rctx->cb_shader_mask = rctx->fb_cb_shader_mask;
-	}
 }
 
 static unsigned r600_conv_prim_to_gs_out(unsigned mode)
@@ -908,7 +920,6 @@ void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
 		rctx->vgt.nregs = 0;
 		r600_pipe_state_add_reg(&rctx->vgt, R_008958_VGT_PRIMITIVE_TYPE, prim);
 		r600_pipe_state_add_reg(&rctx->vgt, R_028A6C_VGT_GS_OUT_PRIM_TYPE, 0);
-		r600_pipe_state_add_reg(&rctx->vgt, R_02823C_CB_SHADER_MASK, 0);
 		r600_pipe_state_add_reg(&rctx->vgt, R_028408_VGT_INDX_OFFSET, info.index_bias);
 		r600_pipe_state_add_reg(&rctx->vgt, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info.restart_index);
 		r600_pipe_state_add_reg(&rctx->vgt, R_028410_SX_ALPHA_TEST_CONTROL, 0);
@@ -922,7 +933,6 @@ void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
 	rctx->vgt.nregs = 0;
 	r600_pipe_state_mod_reg(&rctx->vgt, prim);
 	r600_pipe_state_mod_reg(&rctx->vgt, r600_conv_prim_to_gs_out(info.mode));
-	r600_pipe_state_mod_reg(&rctx->vgt, rctx->cb_shader_mask);
 	r600_pipe_state_mod_reg(&rctx->vgt, info.index_bias);
 	r600_pipe_state_mod_reg(&rctx->vgt, info.restart_index);
 	r600_pipe_state_mod_reg(&rctx->vgt, rctx->sx_alpha_test_control);