diff options
| author | Nicolai Hähnle <[email protected]> | 2016-09-14 09:43:42 +0200 |
|---|---|---|
| committer | Nicolai Hähnle <[email protected]> | 2016-09-29 11:15:00 +0200 |
| commit | 7a0e543836a69c7f51b264825316215d3f6bae8a (patch) | |
| tree | 0455ac49cd1e40037886a38f4301df7e95a95ab0 /src/gallium/drivers | |
| parent | 15e26611373e6368eb6dd8365007b208668d0508 (diff) | |
radeonsi: enable ARB_query_buffer_object (v2)
v2: enable only when compute is available
Reviewed-by: Edward O'Callaghan <[email protected]>
Reviewed-by: Marek Olšák <[email protected]>
Diffstat (limited to 'src/gallium/drivers')
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_pipe.c | 21 |
1 files changed, 14 insertions, 7 deletions
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c index 730be9d55da..60ef5485855 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.c +++ b/src/gallium/drivers/radeonsi/si_pipe.c @@ -316,6 +316,16 @@ fail: /* * pipe_screen */ +static bool si_have_tgsi_compute(struct si_screen *sscreen) +{ + /* Old kernels disallowed some register writes for SI + * that are used for indirect dispatches. */ + return HAVE_LLVM >= 0x309 && + (sscreen->b.chip_class >= CIK || + sscreen->b.info.drm_major == 3 || + (sscreen->b.info.drm_major == 2 && + sscreen->b.info.drm_minor >= 45)); +} static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param) { @@ -448,12 +458,14 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param) case PIPE_CAP_FAKE_SW_MSAA: case PIPE_CAP_TEXTURE_GATHER_OFFSETS: case PIPE_CAP_VERTEXID_NOBASE: - case PIPE_CAP_QUERY_BUFFER_OBJECT: case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES: case PIPE_CAP_TGSI_VOTE: case PIPE_CAP_MAX_WINDOW_RECTANGLES: return 0; + case PIPE_CAP_QUERY_BUFFER_OBJECT: + return si_have_tgsi_compute(sscreen); + case PIPE_CAP_DRAW_PARAMETERS: case PIPE_CAP_MULTI_DRAW_INDIRECT: case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS: @@ -567,12 +579,7 @@ static int si_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enu case PIPE_SHADER_CAP_SUPPORTED_IRS: { int ir = 1 << PIPE_SHADER_IR_NATIVE; - /* Old kernels disallowed some register writes for SI - * that are used for indirect dispatches. */ - if (HAVE_LLVM >= 0x309 && (sscreen->b.chip_class >= CIK || - sscreen->b.info.drm_major == 3 || - (sscreen->b.info.drm_major == 2 && - sscreen->b.info.drm_minor >= 45))) + if (si_have_tgsi_compute(sscreen)) ir |= 1 << PIPE_SHADER_IR_TGSI; return ir; |