diff options
| author | Samuel Pitoiset <[email protected]> | 2017-06-28 18:19:09 +0200 |
|---|---|---|
| committer | Samuel Pitoiset <[email protected]> | 2017-08-22 11:34:24 +0200 |
| commit | 50349f404d3e4153c364f21ddc24a57060020003 (patch) | |
| tree | 7273ae963761a2c57776dc06136429e6420bbfa4 /src/gallium/drivers | |
| parent | a5ff4a8e2e5bc1b7107a1d902feaf4d5edb96b3f (diff) | |
radeonsi: add si_emit_global_shader_pointers() helper
To share common code between rw buffers and bindless descriptors.
Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Marek Olšák <[email protected]>
Diffstat (limited to 'src/gallium/drivers')
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_descriptors.c | 57 |
1 files changed, 31 insertions, 26 deletions
diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c index c26b8291cfb..13a9a08ea58 100644 --- a/src/gallium/drivers/radeonsi/si_descriptors.c +++ b/src/gallium/drivers/radeonsi/si_descriptors.c @@ -2195,6 +2195,35 @@ static void si_emit_shader_pointer(struct si_context *sctx, radeon_emit(cs, va >> 32); } +static void si_emit_global_shader_pointers(struct si_context *sctx, + struct si_descriptors *descs) +{ + si_emit_shader_pointer(sctx, descs, + R_00B030_SPI_SHADER_USER_DATA_PS_0); + si_emit_shader_pointer(sctx, descs, + R_00B130_SPI_SHADER_USER_DATA_VS_0); + + if (sctx->b.chip_class >= GFX9) { + /* GFX9 merged LS-HS and ES-GS. + * Set RW_BUFFERS in the special registers, so that + * it's preloaded into s[0:1] instead of s[8:9]. + */ + si_emit_shader_pointer(sctx, descs, + R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS); + si_emit_shader_pointer(sctx, descs, + R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS); + } else { + si_emit_shader_pointer(sctx, descs, + R_00B230_SPI_SHADER_USER_DATA_GS_0); + si_emit_shader_pointer(sctx, descs, + R_00B330_SPI_SHADER_USER_DATA_ES_0); + si_emit_shader_pointer(sctx, descs, + R_00B430_SPI_SHADER_USER_DATA_HS_0); + si_emit_shader_pointer(sctx, descs, + R_00B530_SPI_SHADER_USER_DATA_LS_0); + } +} + void si_emit_graphics_shader_pointers(struct si_context *sctx, struct r600_atom *atom) { @@ -2204,32 +2233,8 @@ void si_emit_graphics_shader_pointers(struct si_context *sctx, descs = &sctx->descriptors[SI_DESCS_RW_BUFFERS]; - if (sctx->shader_pointers_dirty & (1 << SI_DESCS_RW_BUFFERS)) { - si_emit_shader_pointer(sctx, descs, - R_00B030_SPI_SHADER_USER_DATA_PS_0); - si_emit_shader_pointer(sctx, descs, - R_00B130_SPI_SHADER_USER_DATA_VS_0); - - if (sctx->b.chip_class >= GFX9) { - /* GFX9 merged LS-HS and ES-GS. - * Set RW_BUFFERS in the special registers, so that - * it's preloaded into s[0:1] instead of s[8:9]. - */ - si_emit_shader_pointer(sctx, descs, - R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS); - si_emit_shader_pointer(sctx, descs, - R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS); - } else { - si_emit_shader_pointer(sctx, descs, - R_00B230_SPI_SHADER_USER_DATA_GS_0); - si_emit_shader_pointer(sctx, descs, - R_00B330_SPI_SHADER_USER_DATA_ES_0); - si_emit_shader_pointer(sctx, descs, - R_00B430_SPI_SHADER_USER_DATA_HS_0); - si_emit_shader_pointer(sctx, descs, - R_00B530_SPI_SHADER_USER_DATA_LS_0); - } - } + if (sctx->shader_pointers_dirty & (1 << SI_DESCS_RW_BUFFERS)) + si_emit_global_shader_pointers(sctx, descs); mask = sctx->shader_pointers_dirty & u_bit_consecutive(SI_DESCS_FIRST_SHADER, |