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authorMarek Olšák <[email protected]>2016-09-08 20:15:51 +0200
committerMarek Olšák <[email protected]>2016-09-09 22:45:07 +0200
commit08bcbfdc07ed6ba371998b00deb7a2a67357c6af (patch)
tree605f4909486f27f2609014bf4b28509f5fc1e8a2 /src/gallium/drivers
parenta5a2cc530c1f493557c232557ad1910e607712c2 (diff)
radeonsi: flush TC L2 before using a compute indirect buffer
There is no known test for this. Cc: 12.0 <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
Diffstat (limited to 'src/gallium/drivers')
-rw-r--r--src/gallium/drivers/radeonsi/si_compute.c12
1 files changed, 10 insertions, 2 deletions
diff --git a/src/gallium/drivers/radeonsi/si_compute.c b/src/gallium/drivers/radeonsi/si_compute.c
index f43c616b272..d9882141444 100644
--- a/src/gallium/drivers/radeonsi/si_compute.c
+++ b/src/gallium/drivers/radeonsi/si_compute.c
@@ -464,10 +464,18 @@ static void si_launch_grid(
/* Add buffer sizes for memory checking in need_cs_space. */
r600_context_add_resource_size(ctx, &program->shader.bo->b.b);
- if (info->indirect)
- r600_context_add_resource_size(ctx, info->indirect);
/* TODO: add the scratch buffer */
+ if (info->indirect) {
+ r600_context_add_resource_size(ctx, info->indirect);
+
+ /* The hw doesn't read the indirect buffer via TC L2. */
+ if (r600_resource(info->indirect)->TC_L2_dirty) {
+ sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
+ r600_resource(info->indirect)->TC_L2_dirty = false;
+ }
+ }
+
si_need_cs_space(sctx);
if (!sctx->cs_shader_state.initialized)