diff options
| author | Erik Faye-Lund <[email protected]> | 2019-10-29 12:43:56 +0100 |
|---|---|---|
| committer | Erik Faye-Lund <[email protected]> | 2019-10-30 10:29:23 +0000 |
| commit | 6d30abb4f14e238d128ab05479c6d4377a27ebfa (patch) | |
| tree | c2307724f1a1fd72a8dc82d7ad8ad2a43970fbde /src/gallium/drivers/zink/zink_context.c | |
| parent | d2bb63c8d4cdc02b1c33afadea5becd58fb7286c (diff) | |
zink: use dynamic state for line-width
This will lead to fewer pipelines in the cache, which is assumed to
become our most unavoidable performance bottle-neck down the line.
Reviewed-by: Dave Airlie <[email protected]>
Diffstat (limited to 'src/gallium/drivers/zink/zink_context.c')
| -rw-r--r-- | src/gallium/drivers/zink/zink_context.c | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/src/gallium/drivers/zink/zink_context.c b/src/gallium/drivers/zink/zink_context.c index 10706b1a96a..c6f32f83aec 100644 --- a/src/gallium/drivers/zink/zink_context.c +++ b/src/gallium/drivers/zink/zink_context.c @@ -1020,8 +1020,10 @@ zink_draw_vbo(struct pipe_context *pctx, &ctx->gfx_pipeline_state, dinfo->mode); + enum pipe_prim_type reduced_prim = u_reduced_prim(dinfo->mode); + bool depth_bias = false; - switch (u_reduced_prim(dinfo->mode)) { + switch (reduced_prim) { case PIPE_PRIM_POINTS: depth_bias = rast_state->offset_point; break; @@ -1154,6 +1156,13 @@ zink_draw_vbo(struct pipe_context *pctx, vkCmdSetScissor(batch->cmdbuf, 0, 1, &fb_scissor); } + if (reduced_prim == PIPE_PRIM_LINES) { + if (screen->feats.wideLines || ctx->line_width == 1.0f) + vkCmdSetLineWidth(batch->cmdbuf, ctx->line_width); + else + debug_printf("BUG: wide lines not supported, needs fallback!"); + } + vkCmdSetStencilReference(batch->cmdbuf, VK_STENCIL_FACE_FRONT_BIT, ctx->stencil_ref.ref_value[0]); vkCmdSetStencilReference(batch->cmdbuf, VK_STENCIL_FACE_BACK_BIT, ctx->stencil_ref.ref_value[1]); |