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authorKenneth Graunke <[email protected]>2019-05-14 20:23:36 -0700
committerKenneth Graunke <[email protected]>2019-05-23 08:13:07 -0700
commita2d783445791363d56d7365ef50f4748840220a2 (patch)
tree32569bd0e7b204a040f4084f20d25bb7e082408e /src/gallium/drivers/virgl
parent7d2b54e3936ded025d5d75246a7c0a3f2712413f (diff)
gallium: Change PIPE_CAP_TGSI_FS_FBFETCH bool to PIPE_CAP_FBFETCH count
TGSI's FBFETCH instruction currently only supports reading from a single render target, but NIR intrinsics can support multiple render targets. radeonsi can only support fetching from RT 0, but other drivers may be able to support fetching from any render target. To express this, this patch renames PIPE_CAP_TGSI_FS_FBFETCH to simply PIPE_CAP_FBFETCH, and converts it from a boolean "is FBFETCH supported?" to an integer number of render targets which can be fetched. Reviewed-by: Marek Olšák <[email protected]>
Diffstat (limited to 'src/gallium/drivers/virgl')
-rw-r--r--src/gallium/drivers/virgl/virgl_screen.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/src/gallium/drivers/virgl/virgl_screen.c b/src/gallium/drivers/virgl/virgl_screen.c
index 66cb6b7a219..2880aa3a4dc 100644
--- a/src/gallium/drivers/virgl/virgl_screen.c
+++ b/src/gallium/drivers/virgl/virgl_screen.c
@@ -246,8 +246,9 @@ virgl_get_param(struct pipe_screen *screen, enum pipe_cap param)
return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_FB_NO_ATTACH;
case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_ROBUST_BUFFER_ACCESS;
- case PIPE_CAP_TGSI_FS_FBFETCH:
- return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_TGSI_FBFETCH;
+ case PIPE_CAP_FBFETCH:
+ return (vscreen->caps.caps.v2.capability_bits &
+ VIRGL_CAP_TGSI_FBFETCH) ? 1 : 0;
case PIPE_CAP_TGSI_CLOCK:
return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_SHADER_CLOCK;
case PIPE_CAP_TGSI_ARRAY_COMPONENTS: