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authorEric Anholt <[email protected]>2016-11-10 15:23:19 -0800
committerEric Anholt <[email protected]>2016-11-12 18:46:35 -0800
commit4f527f12604269f15704bbd14a4962766afdfb9a (patch)
tree4f41e1f564a7f2a7fc702239757e64c7b75db522 /src/gallium/drivers/vc4
parent93cdae44defdcc0a758e2f5376226b9944e1c91e (diff)
vc4: Add a thread switch QIR instruction.
This will eventually be generated at the QIR level, so that vc4_qir_schedule.c can arrange the separation of tex_strb from tex_result correctly. It will also be important so that register allocation set the register classes appropriately for values that are live across the switch.
Diffstat (limited to 'src/gallium/drivers/vc4')
-rw-r--r--src/gallium/drivers/vc4/vc4_qir.c2
-rw-r--r--src/gallium/drivers/vc4/vc4_qir.h10
-rw-r--r--src/gallium/drivers/vc4/vc4_qpu_emit.c6
3 files changed, 18 insertions, 0 deletions
diff --git a/src/gallium/drivers/vc4/vc4_qir.c b/src/gallium/drivers/vc4/vc4_qir.c
index a34eccf5091..f9c9703e3f9 100644
--- a/src/gallium/drivers/vc4/vc4_qir.c
+++ b/src/gallium/drivers/vc4/vc4_qir.c
@@ -82,6 +82,8 @@ static const struct qir_op_info qir_op_info[] = {
[QOP_TEX_DIRECT] = { "tex_direct", 0, 2, true },
[QOP_TEX_RESULT] = { "tex_result", 1, 0, true },
+ [QOP_THRSW] = { "thrsw", 0, 0, true },
+
[QOP_LOAD_IMM] = { "load_imm", 0, 1 },
[QOP_LOAD_IMM_U2] = { "load_imm_u2", 0, 1 },
[QOP_LOAD_IMM_I2] = { "load_imm_i2", 0, 1 },
diff --git a/src/gallium/drivers/vc4/vc4_qir.h b/src/gallium/drivers/vc4/vc4_qir.h
index c76aeb2bf4e..7f321c46868 100644
--- a/src/gallium/drivers/vc4/vc4_qir.h
+++ b/src/gallium/drivers/vc4/vc4_qir.h
@@ -156,6 +156,16 @@ enum qop {
*/
QOP_TEX_RESULT,
+ /**
+ * Insert the signal for switching threads in a threaded fragment
+ * shader. No value can be live in an accumulator across a thrsw.
+ *
+ * At the QPU level, this will have several delay slots before the
+ * switch happens. Those slots are the responsibility of the
+ * scheduler.
+ */
+ QOP_THRSW,
+
/* 32-bit immediate loaded to each SIMD channel */
QOP_LOAD_IMM,
diff --git a/src/gallium/drivers/vc4/vc4_qpu_emit.c b/src/gallium/drivers/vc4/vc4_qpu_emit.c
index eedee55a9f5..58fcbc93d97 100644
--- a/src/gallium/drivers/vc4/vc4_qpu_emit.c
+++ b/src/gallium/drivers/vc4/vc4_qpu_emit.c
@@ -500,6 +500,12 @@ vc4_generate_code_block(struct vc4_compile *c,
handle_r4_qpu_write(block, qinst, dst);
break;
+ case QOP_THRSW:
+ queue(block, qpu_NOP());
+ *last_inst(block) = qpu_set_sig(*last_inst(block),
+ QPU_SIG_THREAD_SWITCH);
+ break;
+
case QOP_BRANCH:
/* The branch target will be updated at QPU scheduling
* time.