vc4: Add support for the FLR opcode.

1 files changed, 18 insertions, 0 deletions

diff --git a/src/gallium/drivers/vc4/vc4_program.c b/src/gallium/drivers/vc4/vc4_program.c
index d871dcd88d3..c87ea52c25e 100644
--- a/src/gallium/drivers/vc4/vc4_program.c
+++ b/src/gallium/drivers/vc4/vc4_program.c
@@ -390,6 +390,23 @@ tgsi_to_qir_frc(struct tgsi_to_qir *trans,
                        diff);
 }
 
+/**
+ * Computes floor(x), which is tricky because our FTOI truncates (rounds to
+ * zero).
+ */
+static struct qreg
+tgsi_to_qir_flr(struct tgsi_to_qir *trans,
+                struct tgsi_full_instruction *tgsi_inst,
+                enum qop op, struct qreg *src, int i)
+{
+        struct qcompile *c = trans->c;
+        struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));
+        return qir_CMP(c,
+                       src[0 * 4 + i],
+                       qir_FSUB(c, trunc, qir_uniform_f(trans, 1.0)),
+                       trunc);
+}
+
 static struct qreg
 tgsi_to_qir_dp(struct tgsi_to_qir *trans,
                struct tgsi_full_instruction *tgsi_inst,
@@ -665,6 +682,7 @@ emit_tgsi_instruction(struct tgsi_to_qir *trans,
                 [TGSI_OPCODE_POW] = { 0, tgsi_to_qir_pow },
                 [TGSI_OPCODE_TRUNC] = { 0, tgsi_to_qir_trunc },
                 [TGSI_OPCODE_FRC] = { 0, tgsi_to_qir_frc },
+                [TGSI_OPCODE_FLR] = { 0, tgsi_to_qir_flr },
                 [TGSI_OPCODE_SIN] = { 0, tgsi_to_qir_sin },
                 [TGSI_OPCODE_COS] = { 0, tgsi_to_qir_cos },
         };