diff options
| author | Eric Anholt <[email protected]> | 2014-09-29 15:58:15 -0700 |
|---|---|---|
| committer | Eric Anholt <[email protected]> | 2014-09-29 17:44:15 -0700 |
| commit | 4ceaad14fffed769e04a697afd24f6660b0980b2 (patch) | |
| tree | f175bcf98dbd70f624ec66f8a4fc3bb8c5c42643 /src/gallium/drivers/vc4 | |
| parent | 1d42aa83580df270f53ab3a4e6b78e172107ee5f (diff) | |
vc4: Don't try to do stores to buffers that aren't bound.
The code was kind of mixed up what buffers were getting stored in the case
that a resolve bit was unset (which are set based on the GL state at draw
time) and the buffer wasn't actually bound. In particular, depth-only
rendering would store the color buffer contents, which happen to be
pointing at the depth buffer.
Thanks to clearing out the resolve bits for things we really can't
resolve, now I can drop the safety checks for buffer presence around the
actual stores.
Fixes 42 piglit tests.
Diffstat (limited to 'src/gallium/drivers/vc4')
| -rw-r--r-- | src/gallium/drivers/vc4/vc4_context.c | 13 |
1 files changed, 8 insertions, 5 deletions
diff --git a/src/gallium/drivers/vc4/vc4_context.c b/src/gallium/drivers/vc4/vc4_context.c index 34a100d2ab0..d1b4fbcea00 100644 --- a/src/gallium/drivers/vc4/vc4_context.c +++ b/src/gallium/drivers/vc4/vc4_context.c @@ -43,6 +43,11 @@ vc4_setup_rcl(struct vc4_context *vc4) struct vc4_resource *ctex = csurf ? vc4_resource(csurf->base.texture) : NULL; struct vc4_surface *zsurf = vc4_surface(vc4->framebuffer.zsbuf); struct vc4_resource *ztex = zsurf ? vc4_resource(zsurf->base.texture) : NULL; + + if (!csurf) + vc4->resolve &= ~PIPE_CLEAR_COLOR0; + if (!zsurf) + vc4->resolve &= ~(PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL); uint32_t resolve_uncleared = vc4->resolve & ~vc4->cleared; uint32_t width = vc4->framebuffer.width; uint32_t height = vc4->framebuffer.height; @@ -113,7 +118,7 @@ vc4_setup_rcl(struct vc4_context *vc4) /* Note that the load doesn't actually occur until the * tile coords packet is processed. */ - if (csurf && (resolve_uncleared & PIPE_CLEAR_COLOR)) { + if (resolve_uncleared & PIPE_CLEAR_COLOR) { cl_start_reloc(&vc4->rcl, 1); cl_u8(&vc4->rcl, VC4_PACKET_LOAD_TILE_BUFFER_GENERAL); cl_u8(&vc4->rcl, @@ -133,8 +138,7 @@ vc4_setup_rcl(struct vc4_context *vc4) coords_emitted = true; } - if (zsurf && (resolve_uncleared & (PIPE_CLEAR_DEPTH | - PIPE_CLEAR_STENCIL))) { + if (resolve_uncleared & (PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL)) { cl_start_reloc(&vc4->rcl, 1); cl_u8(&vc4->rcl, VC4_PACKET_LOAD_TILE_BUFFER_GENERAL); cl_u8(&vc4->rcl, @@ -166,8 +170,7 @@ vc4_setup_rcl(struct vc4_context *vc4) cl_reloc(vc4, &vc4->rcl, vc4->tile_alloc, (y * xtiles + x) * 32); - if (zsurf && (vc4->resolve & (PIPE_CLEAR_DEPTH | - PIPE_CLEAR_STENCIL))) { + if (vc4->resolve & (PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL)) { cl_start_reloc(&vc4->rcl, 1); cl_u8(&vc4->rcl, VC4_PACKET_STORE_TILE_BUFFER_GENERAL); cl_u8(&vc4->rcl, |