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authorEric Anholt <[email protected]>2014-12-02 16:31:29 -0800
committerEric Anholt <[email protected]>2014-12-05 10:43:14 -0800
commit042962df2d058c4dd4e45b7deaa3b4519141758e (patch)
treeaa90563a96c5fec696ee809836f9b02704177179 /src/gallium/drivers/vc4
parentbd4057a5d74fd12222801c55ee98346af9c1095d (diff)
vc4: Fix inverted priority of instructions for QPU scheduling.
We were scheduling TLB operations as early as possible, and texture setup as late as possible. When I introduced prioritization, I visually inspected that an independent operation got moved above texture results collection, which tricked me into thinking it was working (but it was just because texture setup was being pushed late). total instructions in shared programs: 57651 -> 57486 (-0.29%) instructions in affected programs: 18532 -> 18367 (-0.89%)
Diffstat (limited to 'src/gallium/drivers/vc4')
-rw-r--r--src/gallium/drivers/vc4/vc4_qpu_schedule.c20
1 files changed, 10 insertions, 10 deletions
diff --git a/src/gallium/drivers/vc4/vc4_qpu_schedule.c b/src/gallium/drivers/vc4/vc4_qpu_schedule.c
index 8aa83741ff5..2b0a6326b8c 100644
--- a/src/gallium/drivers/vc4/vc4_qpu_schedule.c
+++ b/src/gallium/drivers/vc4/vc4_qpu_schedule.c
@@ -439,24 +439,24 @@ get_instruction_priority(uint64_t inst)
uint32_t baseline_score;
uint32_t next_score = 0;
- /* Schedule texture read setup early to hide their latency better. */
- if (is_tmu_write(waddr_add) || is_tmu_write(waddr_mul))
+ /* Schedule TLB operations as late as possible, to get more
+ * parallelism between shaders.
+ */
+ if (qpu_inst_is_tlb(inst))
return next_score;
next_score++;
- /* Default score for things that aren't otherwise special. */
- baseline_score = next_score;
- next_score++;
-
/* Schedule texture read results collection late to hide latency. */
if (sig == QPU_SIG_LOAD_TMU0 || sig == QPU_SIG_LOAD_TMU1)
return next_score;
next_score++;
- /* Schedule TLB operations as late as possible, to get more
- * parallelism between shaders.
- */
- if (qpu_inst_is_tlb(inst))
+ /* Default score for things that aren't otherwise special. */
+ baseline_score = next_score;
+ next_score++;
+
+ /* Schedule texture read setup early to hide their latency better. */
+ if (is_tmu_write(waddr_add) || is_tmu_write(waddr_mul))
return next_score;
next_score++;