vc4: Mostly fix offset calculation for NPOT mipmap levels.

The non-base NPOT levels are stored as POT-aligned images.  We get that
POT alignment by minifying the POT-aligned base level.

This means that level strides are also POT aligned, so we have to tell the
rendering mode config that our resource is larger than the actual
requested area.

Fixes the fbo-generatemipmap-formats NPOT cases.  Regresses
depthstencil-render-miplevels 273 * -- the texture presentation now works
(where it was completely broken before), it looks like there's some
overflow of image bounds happening at the lower miplevels.

1 files changed, 12 insertions, 1 deletions

diff --git a/src/gallium/drivers/vc4/vc4_state.c b/src/gallium/drivers/vc4/vc4_state.c
index 5f5eee8134c..2a123eb0b08 100644
--- a/src/gallium/drivers/vc4/vc4_state.c
+++ b/src/gallium/drivers/vc4/vc4_state.c
@@ -389,10 +389,21 @@ vc4_set_framebuffer_state(struct pipe_context *pctx,
 
         cso->nr_cbufs = framebuffer->nr_cbufs;
 
+        pipe_surface_reference(&cso->zsbuf, framebuffer->zsbuf);
+
         cso->width = framebuffer->width;
         cso->height = framebuffer->height;
 
-        pipe_surface_reference(&cso->zsbuf, framebuffer->zsbuf);
+        /* Nonzero texture mipmap levels are laid out as if they were in
+         * power-of-two-sized spaces.  The renderbuffer config infers its
+         * stride from the width parameter, so we need to configure our
+         * framebuffer.  Note that if the z/color buffers were mismatched
+         * sizes, we wouldn't be able to do this.
+         */
+        if ((cso->cbufs[0] && cso->cbufs[0]->u.tex.level) ||
+             (cso->zsbuf && cso->zsbuf->u.tex.level)) {
+                cso->width = util_next_power_of_two(cso->width);
+        }
 
         vc4->dirty |= VC4_DIRTY_FRAMEBUFFER;
 }