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authorEric Anholt <[email protected]>2014-12-08 16:52:53 -0800
committerEric Anholt <[email protected]>2014-12-09 01:04:46 -0800
commit8420a956924c720b3c4932a577623f836758c21c (patch)
tree09097890b2dabbb4bff4bf81e4b5d55ddcf3bc6a /src/gallium/drivers/vc4/vc4_register_allocate.c
parentab1b1fa6fbd72b05c48f83c9df5036c2bfe893a3 (diff)
vc4: Reserve rb31 instead of r3 for raddr conflict spills.
This increases the cost of a raddr b conflict spill (save r3 to rb31, move src1 to r3, move rb31 back to r3 when done, instead of just move src1 to r3), but on average thanks to instruction pairing it's more worthwhile to have another accumulator. total instructions in shared programs: 46428 -> 46171 (-0.55%) instructions in affected programs: 38030 -> 37773 (-0.68%)
Diffstat (limited to 'src/gallium/drivers/vc4/vc4_register_allocate.c')
-rw-r--r--src/gallium/drivers/vc4/vc4_register_allocate.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/gallium/drivers/vc4/vc4_register_allocate.c b/src/gallium/drivers/vc4/vc4_register_allocate.c
index 3001900c074..85f29e54f94 100644
--- a/src/gallium/drivers/vc4/vc4_register_allocate.c
+++ b/src/gallium/drivers/vc4/vc4_register_allocate.c
@@ -117,10 +117,10 @@ vc4_alloc_reg_set(struct vc4_context *vc4)
vc4->reg_class_any = ra_alloc_reg_class(vc4->regs);
for (uint32_t i = 0; i < ARRAY_SIZE(vc4_regs); i++) {
- /* Reserve r3 for now, since we're using it for spilling-like
- * operations in vc4_qpu_emit.c
+ /* Reserve rb31 for spilling fixup_raddr_conflict() in
+ * vc4_qpu_emit.c
*/
- if (vc4_regs[i].mux == QPU_MUX_R3)
+ if (vc4_regs[i].mux == QPU_MUX_B && vc4_regs[i].addr == 31)
continue;
/* R4 can't be written as a general purpose register. (it's