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authorEric Anholt <[email protected]>2016-03-15 13:43:54 -0700
committerEric Anholt <[email protected]>2016-07-12 17:42:38 -0700
commitc73aa0a09b996feff5aec42e0347b99b35b2f981 (patch)
tree1b1f53fca7af3e18f7361ccef58eeb0fa85350e9 /src/gallium/drivers/vc4/vc4_qpu.c
parent6d343450014e86e22f1d067d79c6fff524d4c8d1 (diff)
vc4: Add QPU support for generating BRANCH instructions.
Diffstat (limited to 'src/gallium/drivers/vc4/vc4_qpu.c')
-rw-r--r--src/gallium/drivers/vc4/vc4_qpu.c18
1 files changed, 17 insertions, 1 deletions
diff --git a/src/gallium/drivers/vc4/vc4_qpu.c b/src/gallium/drivers/vc4/vc4_qpu.c
index 6aa6b24d94c..cf74c424391 100644
--- a/src/gallium/drivers/vc4/vc4_qpu.c
+++ b/src/gallium/drivers/vc4/vc4_qpu.c
@@ -165,6 +165,20 @@ qpu_load_imm_ui(struct qpu_reg dst, uint32_t val)
}
uint64_t
+qpu_branch(uint32_t cond, uint32_t target)
+{
+ uint64_t inst = 0;
+
+ inst |= qpu_a_dst(qpu_ra(QPU_W_NOP));
+ inst |= qpu_m_dst(qpu_rb(QPU_W_NOP));
+ inst |= QPU_SET_FIELD(cond, QPU_BRANCH_COND);
+ inst |= QPU_SET_FIELD(QPU_SIG_BRANCH, QPU_SIG);
+ inst |= QPU_SET_FIELD(target, QPU_BRANCH_TARGET);
+
+ return inst;
+}
+
+uint64_t
qpu_a_alu2(enum qpu_op_add op,
struct qpu_reg dst, struct qpu_reg src0, struct qpu_reg src1)
{
@@ -446,7 +460,9 @@ qpu_merge_inst(uint64_t a, uint64_t b)
if (a_sig == QPU_SIG_LOAD_IMM ||
b_sig == QPU_SIG_LOAD_IMM ||
a_sig == QPU_SIG_SMALL_IMM ||
- b_sig == QPU_SIG_SMALL_IMM) {
+ b_sig == QPU_SIG_SMALL_IMM ||
+ a_sig == QPU_SIG_BRANCH ||
+ b_sig == QPU_SIG_BRANCH) {
return 0;
}