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authorEric Anholt <[email protected]>2015-11-10 15:37:47 -0800
committerEric Anholt <[email protected]>2015-11-17 17:45:23 -0800
commita4bf28178f064082d3b818d2cd48abf9075cc459 (patch)
tree13df51733cb8ee1dd0f0f3acd262bbb384e1e96a /src/gallium/drivers/vc4/vc4_qir.h
parent27b1d344384ef89faf6d321bf4625d08ba6ff3bf (diff)
vc4: Add support for nir_op_uge, using the carry bit on QPU_A_SUB.
It looks like nir_lower_idiv is going to use it soon, so add support. With Ilia's change, this fixes one case in fs-op-div-large-uint-uint (with GL 3.0 forced on). Cc: "11.0" <[email protected]>
Diffstat (limited to 'src/gallium/drivers/vc4/vc4_qir.h')
-rw-r--r--src/gallium/drivers/vc4/vc4_qir.h8
1 files changed, 8 insertions, 0 deletions
diff --git a/src/gallium/drivers/vc4/vc4_qir.h b/src/gallium/drivers/vc4/vc4_qir.h
index a92ad93ee07..ddb35e41fcf 100644
--- a/src/gallium/drivers/vc4/vc4_qir.h
+++ b/src/gallium/drivers/vc4/vc4_qir.h
@@ -99,11 +99,15 @@ enum qop {
QOP_SEL_X_0_ZC,
QOP_SEL_X_0_NS,
QOP_SEL_X_0_NC,
+ QOP_SEL_X_0_CS,
+ QOP_SEL_X_0_CC,
/* Selects the src[0] if the ns flag bit is set, otherwise src[1]. */
QOP_SEL_X_Y_ZS,
QOP_SEL_X_Y_ZC,
QOP_SEL_X_Y_NS,
QOP_SEL_X_Y_NC,
+ QOP_SEL_X_Y_CS,
+ QOP_SEL_X_Y_CC,
QOP_FTOI,
QOP_ITOF,
@@ -567,10 +571,14 @@ QIR_ALU1(SEL_X_0_ZS)
QIR_ALU1(SEL_X_0_ZC)
QIR_ALU1(SEL_X_0_NS)
QIR_ALU1(SEL_X_0_NC)
+QIR_ALU1(SEL_X_0_CS)
+QIR_ALU1(SEL_X_0_CC)
QIR_ALU2(SEL_X_Y_ZS)
QIR_ALU2(SEL_X_Y_ZC)
QIR_ALU2(SEL_X_Y_NS)
QIR_ALU2(SEL_X_Y_NC)
+QIR_ALU2(SEL_X_Y_CS)
+QIR_ALU2(SEL_X_Y_CC)
QIR_ALU2(FMIN)
QIR_ALU2(FMAX)
QIR_ALU2(FMINABS)